A power-on reset circuit and chip

Abstract

The application provides a power-on reset circuit and a chip, and relates to the technical field of integrated circuits. The power-on reset circuit comprises a comparator, a power supply voltage division unit, a reference voltage unit and a power-on / off response unit. The reference voltage unit is used for generating a reference voltage and a reference current after a working state is established. The power-on / off response unit is used for outputting a non-enable signal to an enable end of the comparator to make the comparator not work when the reference voltage and the reference current are not completely established. The power-on / off response unit is also used for outputting an enable signal to the enable end of the comparator to drive the comparator to release a reset signal after the reference voltage and the reference current are established. The power-on reset circuit and the chip provided by the application have the advantages that multiple application scenarios can be considered and the application is more flexible.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to a power-on reset circuit and a chip. BACKGROUND

[0002] A power-on reset circuit (POR) is used to generate a reset signal when a chip is powered on and powered off, so that the internal digital and analog modules can be initialized and started through the generated reset signal, and the internal circuit of the chip can be safely started within an acceptable power supply voltage range. The traditional power-on reset circuit is mainly divided into an RC charging reset circuit and a voltage division comparison reset circuit.

[0003] The reset threshold of the RC charging reset circuit is generally the flip voltage of an inverter or a Schmitt trigger. The architecture of the RC charging reset circuit is simple, and the area and power consumption are small. At the same time, in the fast power-on / off application, the RC charging reset circuit can achieve a faster response speed. However, in the slow power-on application scenario, in order to meet the slow power-on application (hundreds of ms or s level), the value of the capacitor will be very large, which will consume a large chip area. At the same time, the flip threshold of the device is greatly affected by the chip process and temperature, which makes it difficult for the RC charging reset circuit to directly serve as an accurate reset signal generation circuit in the slow power-on scenario.

[0004] Therefore, at present, the RC charging reset circuit is generally only applied to the fast power-on scenario, and in the slow power-on scenario, the voltage division comparison reset circuit is generally used. The principle of the voltage division comparison reset circuit is that the power supply voltage VDD is divided to obtain the same-phase input end voltage of the comparator, and a bandgap reference module generates a stable reference voltage and inputs the reference voltage to the opposite-phase input end of the comparator after power-on. During the chip power-on process, the voltage of the same-phase input end of the comparator rises as VDD rises, and when VDD rises to a certain voltage (POR flip threshold), the voltage of the same-phase input end of the comparator is greater than the voltage of the opposite-phase input end, the comparator output flips to high level, and the POR signal is released; similarly, during the power-off process, when the voltage of the same-phase input end is less than the voltage of the opposite-phase input end, the comparator output flips to low level, the POR signal is reset, and the chip returns to the default state.

[0005] The voltage division comparison reset circuit has the advantage of being able to provide an accurate reset threshold voltage, so it has an advantage in the slow power-on application, but for fast power-on, since the reference voltage needs a certain setup time, and the VDD voltage division can be quickly established, which leads to the fact that the VDD voltage division may always be higher than the reference voltage, and the comparator output is always high, which cannot correctly generate the POR signal. In addition, the comparator and the bandgap reference module need to work at a safe voltage, and when VDD is less than the safe working voltage (for example, 1.2V), the bandgap reference module and the comparator may output errors, so the output of the comparator below the safe working voltage may not be reliable.

[0006] In summary, the application scenarios of the power-on reset circuit in the prior art are relatively single, and multiple application scenarios cannot be considered. SUMMARY

[0007] The purpose of the present application is to provide a power-on reset circuit and a chip to solve the problem that the application scenarios of the power-on reset circuit in the prior art are relatively single and multiple application scenarios cannot be considered.

[0008] In order to achieve the above-mentioned purpose, the technical solutions adopted by the embodiments of the present application are as follows:

[0009] On the one hand, the present application provides a power-on reset circuit, which comprises a comparator, a power supply voltage dividing unit, a reference voltage unit and a power-on and power-off response unit, the power supply voltage dividing unit is connected with the first input end of the comparator, and the power supply voltage dividing unit is also used for connecting a power supply, the reference voltage unit is connected with the second input end of the comparator, the power-on and power-off response unit is connected with the enable end of the comparator and the reference voltage unit, and the output end of the comparator is used as the output of the power-on reset circuit; wherein,

[0010] The reference voltage unit is used to generate a reference voltage and a reference current after a working state is established;

[0011] The power-on and power-off response unit is used to output a non-enable signal to the enable end of the comparator to make the comparator not work when the reference voltage and the reference current are not completely established;

[0012] The power-on and power-off response unit is also used to output an enable signal to the enable end of the comparator to drive the comparator to release a reset signal after the reference voltage and the reference current are established.

[0013] Optionally, the power-on and power-off response unit comprises an input module, a pull-down module and an output module, the input module and the output module are connected to the power supply, and the input module, the pull-down module and the output module are connected in sequence, the input module is used to receive the reference voltage and the reference current, and the output module is connected with the enable end of the comparator; wherein,

[0014] The output module is used to be in a first conduction state and output a low level to the enable end of the comparator when the power supply is powered on and the reference voltage and the reference current are not completely established;

[0015] The output module is also used to be in a second conduction state and output a high level to the enable end of the comparator after the reference voltage and the reference current are established.

[0016] Optionally, the output module comprises a first switch tube, a second switch tube, a driving component and a first capacitor, one end of the first switch tube is connected to a power supply, the other end of the first switch tube is connected to one end of the second switch tube, the other end of the second switch tube is grounded, the control end of the second switch tube is connected to the power supply through the driving component, the driving component is also connected to the pull-down module, the control end of the first switch tube is connected to the input module, the connection between the first switch tube and the second switch tube serves as an output port of the output module, and the output port is grounded through the first capacitor; wherein,

[0017] When the power supply is powered on and the reference voltage and the reference current are not completely established, the first switch tube is turned off and the second switch tube is turned on.

[0018] When the reference voltage and the reference current are established, the first switch tube is turned on and the second switch tube is turned off.

[0019] Optionally, the output module further comprises a first inverter and a second inverter, the input end of the first inverter is connected to the output port of the output module, the output end of the first inverter is connected to the input end of the second inverter, and the output end of the second inverter is connected to the enable end of the comparator.

[0020] Optionally, the driving component comprises a first resistor and a second capacitor, one end of the first resistor is connected to the power supply, the other end of the first resistor is respectively connected to one end of the second capacitor, the control end of the second switch tube and the pull-down module, and the other end of the second capacitor is grounded.

[0021] Optionally, the input module comprises a current mirror, a third switch tube and a third resistor, the current mirror is connected to the power supply, and the current mirror is connected to the output module, one end of the third switch tube is connected to the input end of the current mirror, the other end of the third switch tube is connected to the reference current, the control end of the third switch tube is used for receiving the reference voltage, one end of the third resistor is connected to the output end of the current mirror and the pull-down module, and the other end of the third resistor is grounded; wherein,

[0022] When the reference voltage and the reference current are established, the current mirror is used for copying the input end current to the output end and providing a driving voltage for the pull-down module.

[0023] Optionally, the pull-down module includes a third capacitor, a fourth switch, and a fifth switch. One end of the fourth switch is connected to the output module, and the other end of the fourth switch is connected to one end of the fifth switch. The control terminal of the fourth switch is used to receive the reference voltage. The other end of the fifth switch is grounded. The control terminal of the fifth switch is connected to one end of the third capacitor and the input module, and the other end of the third capacitor is grounded.

[0024] Once the reference voltage and the reference current are established, the fourth switch and the fifth switch are turned on.

[0025] Optionally, the power-on reset circuit further includes a delay unit, which is connected to the output of the comparator; wherein,

[0026] The delay unit is used to filter and shape the output of the comparator.

[0027] Optionally, the delay unit includes a third inverter and a fourth inverter. The input terminal of the third inverter is connected to the output terminal of the comparator, the output terminal of the third inverter is connected to the input terminal of the fourth inverter, and the output terminal of the fourth inverter is used to connect to the subsequent circuit.

[0028] On the other hand, this application also provides a chip that includes the power-on reset circuit described above.

[0029] Compared with the prior art, this application has the following advantages:

[0030] This application provides a power-on reset circuit and chip. The power-on reset circuit includes a comparator, a power supply voltage divider unit, a reference voltage unit, and a power-on / off response unit. The power supply voltage divider unit is connected to the first input terminal of the comparator and is also used to connect to a power supply. The reference voltage unit is connected to the second input terminal of the comparator. The power-on / off response unit is connected to the enable terminal of the comparator and the reference voltage unit. The output terminal of the comparator is used as the output of the power-on reset circuit. The reference voltage unit is used to generate a reference voltage and a reference current after the working state is established. The power-on / off response unit is used to output a de-enabled signal to the enable terminal of the comparator when the reference voltage and reference current are not fully established, so that the comparator does not work. The power-on / off response unit is also used to output an enable signal to the enable terminal of the comparator after the reference voltage and reference current are established, so as to drive the comparator to release the reset signal.

[0031] The power-on reset circuit provided in this application adds a power-on / off response unit to the traditional voltage divider comparison reset circuit architecture. It only outputs an enable signal to the enable terminal of the comparator after the reference voltage and the reference current are fully established. This ensures that the comparator will only release the reset signal within a stable operating voltage range. It can simultaneously accommodate both fast and slow power-on application scenarios, making the use of the power-on reset circuit more flexible.

[0032] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0033] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a circuit diagram of a voltage divider comparison reset circuit in the prior art.

[0035] Figure 2 This is a circuit diagram of the power-on reset circuit provided in an embodiment of this application.

[0036] Figure 3 This is a circuit diagram of the power-on / off response unit provided in an embodiment of this application.

[0037] Figure 4 This is a schematic diagram of the amplitude change during the "power-on-power-off-power-on" process provided in the embodiments of this application.

[0038] Figure 5 A schematic diagram of burr fluctuations provided in the embodiments of this application.

[0039] In the picture:

[0040] 110 - Comparator; 120 - Power supply voltage divider unit; 130 - Reference voltage unit; 140 - Power-on / off response unit; 141 - Input module; 142 - Pull-down module; 143 - Output module; 150 - Delay unit; M1 - First switch transistor; M2 - Second switch transistor; M3 - Third switch transistor; M4 - Fourth switch transistor; M5 - Fifth switch transistor; M6 - Sixth switch transistor; M7 - Seventh switch transistor; R1 - First resistor; R2 - Second resistor; R3 - Third resistor; C1 - First capacitor; C2 - Second capacitor; C3 - Third capacitor; F1 - First inverter; F2 - Second inverter. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0042] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0043] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0044] It should be noted that in this paper, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0045] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0046] Traditional power-on reset circuits are mainly divided into RC charging reset circuits and voltage divider comparison reset circuits. In practical applications, RC charging reset circuits are generally used in fast power-on scenarios, while voltage divider comparison reset circuits are used in slow power-on scenarios. Specifically, slow power-on, as described in this application, refers to a slow rise in power supply voltage (e.g., milliseconds or longer), typically controlled by external circuits (such as RC delay or soft-start circuits); fast power-on, as described in this application, refers to a rapid rise in power supply voltage (microseconds or faster), approaching a step signal.

[0047] like Figure 1The diagram shows a traditional voltage divider comparator reset circuit. Its principle is that the power supply voltage VDD is divided by resistors R10 and R11 to obtain voltage V1. The bandgap reference module generates a stable 1.2V reference voltage Vref after power-on. During chip power-on, V1 increases as VDD increases. When VDD reaches a certain voltage (the POR toggling threshold), the voltage of the divided voltage V1 will be greater than the reference voltage Vref, causing the comparator output POR_OUT to flip to a high level, releasing the POR signal. Similarly, during power-off, when the voltage V1 is lower than Vref, the comparator output POR_OUT flips to a low level, resetting the POR signal and restoring the chip to its default state.

[0048] However, as described in the background section, traditional voltage divider comparator reset circuits have limitations in application scenarios. They cannot simultaneously accommodate applications requiring fast power-on / off, slow power-on / off, small threshold range fluctuations, low power consumption, and rapid power-off and power-on. Therefore, this application provides a power-on reset circuit that optimizes the architecture of traditional voltage divider comparator reset circuits to make them suitable for various fast and slow power-on / off scenarios (1µs~2s), with precisely adjustable power-on and power-off reset thresholds. It can accurately release the reset signal when the required power supply voltage for the system is reached.

[0049] The power-on reset circuit provided in this application is described below by way of example:

[0050] As an optional implementation, please refer to Figure 2 The power-on reset circuit includes a comparator 110, a power supply voltage divider unit 120, a reference voltage unit 130, and a power-on / off response unit 140. The power supply voltage divider unit 120 is connected to the first input terminal of the comparator 110 and is also used to connect to a power supply. The reference voltage unit 130 is connected to the second input terminal of the comparator 110. The power-on / off response unit 140 is connected to the enable terminal of the comparator 110 and the reference voltage unit 130. The output terminal of the comparator 110 is used as the output of the power-on reset circuit. In this application, the first input terminal of the comparator 110 is a non-inverting input terminal, and the second input terminal of the comparator 110 is an inverting input terminal. Of course, in some specific application scenarios, the first input terminal of the comparator 110 can also be an inverting input terminal, and the second input terminal of the comparator 110 can be a non-inverting input terminal; this is not limited here.

[0051] Furthermore, the reference voltage unit 130 generates a reference voltage and a reference current after the operating state is established; the power-on / off response unit 140 outputs a de-enabled signal to the enable terminal of the comparator 110 when the reference voltage and reference current are not fully established, so that the comparator 110 does not work; the power-on / off response unit 140 also outputs an enable signal to the enable terminal of the comparator 110 after the reference voltage and reference current are established, so as to drive the comparator 110 to release the reset signal. The power-on / off response unit is also used to detect the power supply voltage drop during normal operation, and preprocess ripple fluctuations within the design threshold range to prevent the comparator from being falsely triggered; while quickly detecting and outputting excessive drop ripple to ensure rapid reset of POR.

[0052] The power-on / off response unit (POR) has three main functions: reference voltage detection, fast response to power supply voltage fluctuations, and power supply glitch (voltage spikes / transient interference) filtering. By preprocessing and identifying the power supply voltage and reference voltage before enabling the comparator unit, this ensures the comparator operates at an ideal voltage, avoiding most of the drawbacks of traditional voltage divider comparators. Simultaneously, the rapid detection and response to power supply voltage drops allows the POR circuit of this invention to achieve a 1µs-level response in power-off / power-on applications, significantly improving upon the millisecond-level response time of traditional voltage divider comparators. Furthermore, the glitch response circuit design can filter out high-amplitude glitch spikes, meeting the POR circuit's requirements for power supply glitch fluctuations.

[0053] In this application, comparator 110 is enabled at a high level. Based on this, the non-enable signal can be a low-level signal, while the enable signal is a high-level signal. Of course, a comparator 110 enabled at a low level can also be used. Based on this, the non-enable signal can be a high-level signal, while the enable signal is a low-level signal. There is no limitation here.

[0054] Since the comparator 110 in the power-on reset circuit provided in this application can only receive the enable signal after the reference voltage and the reference current are established, and then release the reset signal, it can be ensured that the comparator 110 does not work directly after power-on, but can only work under the ideal voltage. It can simultaneously take into account both fast power-on and slow power-on application scenarios, making the use of the power-on reset circuit more flexible.

[0055] Among them, such as Figure 2As shown, the function of the power supply voltage divider unit 120 is to divide the power supply voltage according to the allocated ratio during power-on. Specifically, resistors R20 and R21 form a voltage divider circuit to divide the power supply voltage VDD, thereby outputting a divided voltage Vcomp to comparator 110. Comparator 110 compares the divided voltage Vcomp with the reference voltage Vref to calculate the threshold voltage point released by the power-on reset circuit. Meanwhile, the structure of the power supply voltage divider unit 120 can employ resistor voltage divider and diode-connected MOSFET voltage divider; this is not limited here. Figure 2 The circuit employs a resistor voltage divider. In the diagram, the two resistors in the power supply voltage divider unit 120 have equal resistance values, resulting in a voltage of 1 / 2 VDD output to the non-inverting input of comparator 110. Of course, in practical applications, the resistance values ​​of the two resistors can be adjusted according to actual needs, thereby adjusting the output voltage divider Vcomp.

[0056] The function of the reference voltage unit 130 is to provide a stable reference voltage whose voltage value is basically unaffected by temperature, process, and power supply fluctuations. A stable reference voltage can reduce the deviation of the power-on reset circuit release voltage value under temperature, process, and power supply fluctuations, making the power-on reset circuit release threshold voltage precisely controllable. The reference voltage unit 130 is usually the reference voltage generated by the bandgap reference module inside the chip.

[0057] Comparator 110 is used to receive the voltages from the power supply voltage divider unit 120 and the reference voltage unit 130 and compare them to output the signal. This ensures that the reset signal is released accurately at the set threshold voltage value, which effectively avoids the problem of the POR being released too early during the fast power-on process of the traditional power-on reset circuit before the power supply voltage has stabilized.

[0058] The power-on / off response unit 140 is used to output an enable signal to the comparator 110. After preprocessing and identifying the power supply voltage and the reference voltage, the power-on / off response unit 140 enables the comparator 110, which can ensure that the comparator 110 works under the ideal voltage and avoid the drawback of the traditional voltage divider comparator 110 starting up immediately upon power-on.

[0059] As one implementation method, please refer to Figure 3The power-on / off response unit 140 includes an input module 141, a pull-down module 142, and an output module 143. The input module 141 and output module 143 are connected to the power supply, and are sequentially connected. The input module 141 receives a reference voltage and a reference current to detect these voltages and currents. The pull-down module 142 provides a fast response to power supply fluctuations (drops). The output module 143 is connected to the enable terminal of the comparator 110. Specifically, when the power supply is powered on and the reference voltage and reference current are not fully established, the output module 143 is in a first conducting state and outputs a low level to the enable terminal of the comparator 110. After the reference voltage and reference current are established, the output module 143 is in a second conducting state and outputs a high level to the enable terminal of the comparator 110.

[0060] Understandably, comparator 110 only operates when its enable pin receives a high level; theoretically, it outputs a continuous low level when not in operation. Therefore, when power is on and the reference voltage and current are not fully established, the power-on / off response unit 140 outputs a low level to comparator 110, and comparator 110 does not operate. Only after the reference voltage and current are established will a high level be output to the enable pin of comparator 110, allowing it to begin operating.

[0061] In one implementation, the output module 143 includes a first switch M1, a second switch M2, a driving component, and a first capacitor C1. One end of the first switch M1 is connected to the power supply, and the other end is connected to one end of the second switch M2. The other end of the second switch M2 is grounded. The control terminal of the second switch M2 is connected to the power supply through the driving component, which is also connected to the pull-down module 142. The control terminal of the first switch M1 is connected to the input module 141. The connection point between the first switch M1 and the second switch M2 serves as the output port of the output module 143, and the output port is grounded through the first capacitor C1. When the power supply is turned on, and the reference voltage and reference current are not fully established, the first switch M1 is turned off, and the second switch M2 is turned on. When the reference voltage and reference current are established, the first switch M1 is turned on, and the second switch M2 is turned off.

[0062] In this application, the first switching transistor M1 can be a P-type switching transistor, and the second switching transistor M2 can be an N-type switching transistor. Furthermore, the driving assembly includes a first resistor R1 and a second capacitor C2. One end of the first resistor R1 is connected to the power supply, and the other end of the first resistor R1 is connected to one end of the second capacitor C2, the control terminal of the second switching transistor M2, and the pull-down module 142, respectively. The other end of the second capacitor C2 is grounded.

[0063] When the power supply is powered on, it charges the second capacitor C2 through the first resistor R1. Once C2 is fully charged, the voltage at the control terminal of the second switch M2 equals the power supply voltage. At this point, the second switch M2 turns on, discharging the charge from the first capacitor C1 to ground, resulting in a low-level output signal to comparator 110. This prevents comparator 110 from operating before vref and ibias are established. Furthermore, when the enable terminal of comparator 110 is low, it does not operate, and its output is 0. Therefore, the output of the entire power-on reset circuit is 0.

[0064] Meanwhile, the output module 143 can filter out voltage fluctuations on the second switching transistor M2 by adjusting the resistance value of the first resistor R1 and the capacitance value of the second capacitor C2, thereby preventing false triggering of the POR circuit caused by the power supply glitch and realizing the identification of power supply glitch fluctuations by the POR circuit (i.e., it can meet the application that the POR output does not reset and the circuit continues to work normally within the design amplitude and duration range of the power supply glitch).

[0065] Furthermore, to achieve signal shaping and buffering, as well as to eliminate glitches or noise, the output module 143 also includes a first inverter F1 and a second inverter F2. The input terminal of the first inverter F1 is connected to the output port of the output module 143, the output terminal of the first inverter F1 is connected to the input terminal of the second inverter F2, and the output terminal of the second inverter F2 is connected to the enable terminal of the comparator 110. For example, if the signal output to the comparator 110 has a brief period of instability (such as glitches), the first inverter F1 may pass it to an intermediate node, but the second inverter F2 will invert the signal again and filter out high-frequency noise through its own delay and threshold characteristics, making the output cleaner.

[0066] In one implementation, the input module 141 includes a current mirror, a third switch M3, and a third resistor R3. The current mirror is connected to a power supply and is also connected to the output module 143. One end of the third switch M3 is connected to the input terminal of the current mirror, and the other end of the third switch M3 is connected to a reference current. The control terminal of the third switch M3 is used to receive a reference voltage. One end of the third resistor R3 is connected to the output terminal of the current mirror and the pull-down module 142, and the other end of the third resistor R3 is grounded. When the reference voltage and the reference current are established, the current mirror is used to copy the input current to the output terminal and provide a drive voltage for the pull-down module 142.

[0067] The pull-down module 142 includes a third capacitor C3, a fourth switch M4, and a fifth switch M5. One end of the fourth switch M4 is connected to the output module 143, and the other end of the fourth switch M4 is connected to one end of the fifth switch M5. The control terminal of the fourth switch M4 is used to receive the reference voltage. The other end of the fifth switch M5 is grounded. The control terminal of the fifth switch M5 is connected to one end of the third capacitor C3 and the input module 141, and the other end of the third capacitor C3 is grounded. When the reference voltage and the reference current are established, the fourth switch M4 and the fifth switch M5 are turned on.

[0068] It should be noted that the current mirror includes a sixth switch M6 and a seventh switch M7. Both the sixth and seventh switches M6 and M7 are P-type switches. One end of the sixth and seventh switches M6 is connected to the power supply. The control terminal of the sixth switch M6 is connected to the other end of the sixth switch M6, the control terminal of the seventh switch M7, and the control terminal of the first switch M1, respectively. Thus, in this circuit, the seventh switch M7, the first switch M1, and the sixth switch M6 together form a current mirror. The other end of the sixth switch M6 is connected to the third switch M3, and the other end of the seventh switch M7 is connected to the third resistor R3 and the pull-down module 142, respectively.

[0069] Furthermore, the fourth switch M4 and the fifth switch M5 can be N-type transistors.

[0070] Understandably, the working principle of the power-on reset circuit provided in this application is as follows:

[0071] After the power supply is turned on, the power supply voltage divider unit 120, the reference voltage unit 130, and the power-on / off response unit 140 start working synchronously. The power supply voltage divider unit 120 generates a voltage divider output to the non-inverting input of the subsequent comparator 110; the reference voltage unit 130 establishes its working state and generates a reference voltage Vref and a reference current Ibias.

[0072] The operation of the power-on / off response unit 140 module consists of two processes. In the first process, before the reference voltage Vref and reference current Ibias are fully established, if the power supply is turned on, the output module 143 operates, achieving a rapid response to the power supply voltage. After the power supply voltage VDD passes through the first resistor R1 and fully charges the second capacitor C2, the control terminal voltage V_glitch of the second switch M2 equals VDD, causing the second switch M2 to conduct and discharge the charge from the first capacitor C1 to ground. At this time, the output port voltage V_respond outputs "0", the comparator 110 does not operate and outputs "0", meaning the entire power-on reset circuit output is also "0".

[0073] The second process involves the input module 141 and the pull-down module 142 starting to operate after the reference voltage unit 130 establishes the reference voltage Vref and the reference current Ibias. Specifically, the reference current Ibias flows through the second resistor R2, the third resistor R3, and the third capacitor C3 after being mirrored by the current mirror. When the current fills the third capacitor C3, it raises the voltage at the control terminal V_start of the fifth switch M5 through the second resistor R2 and the third resistor R3. At this time, the fifth switch M5 and the fourth switch M4 are turned on (the control terminals of the fourth switch M4 and the third switch M3 are both controlled by the reference voltage Vref; when the reference voltage Vref is established, both the fourth switch M4 and the third switch M3 are turned on), and the V_glitch voltage is pulled down. The second switch M2 is turned off, and the voltage of the first capacitor C1 is filled through the first switch M1, causing the inverter to flip. The V_respond voltage outputs "1", realizing the detection of the reference voltage. At this time, the comparator 110 starts to work. Furthermore, the output port of the output module 143 is connected in series with the first inverter F1 and the second inverter F2 to achieve the shaping of the output waveform.

[0074] After comparator 110 starts working, it compares the voltage Vcomp at the non-inverting input terminal and the voltage Vref at the inverting input terminal. When Vcomp > Vref, the output of comparator 110 flips to "1" and after passing through the delay unit 150, the POR circuit releases the reset signal. The power supply voltage at this time is the reset threshold voltage of the POR circuit.

[0075] Furthermore, in order to shape and buffer the POR signal output by the power-on reset circuit, and to eliminate glitches or noise, the power-on reset circuit also includes a delay unit 150, which is connected to the output of the comparator 110; wherein, the delay unit 150 is used to filter and shape the output of the comparator 110.

[0076] In one implementation, the delay unit 150 includes a third inverter and a fourth inverter. The input of the third inverter is connected to the output of the comparator 110, and the output of the third inverter is connected to the input of the fourth inverter. The output of the fourth inverter is used to connect to a subsequent circuit. In other implementations, the delay unit 150 may also include a greater number of inverters, such as... Figure 2 As shown, the delay unit 150 may include four inverters.

[0077] It should be noted that the power-on reset circuit provided in this application only allows the comparator 110 to work after the reference voltage and the reference current are established during the power-on and power-off process. Therefore, the comparator 110 releases the reset signal within a stable operating voltage range, which is suitable for various traditional fast and slow power-on / off scenarios (1us~2s). Moreover, the power-on and power-off reset thresholds are precisely adjustable, and the reset signal can be accurately released when the power supply voltage required by the system is reached.

[0078] And, as Figure 4 As shown, in the "power-on-power-off-power-on" application scenario, due to the power supply VDD being de-energized, the voltage divider comparison voltage Vcomp drops rapidly. When Vcomp is less than Vref, the comparator 110 output should flip to "low," resetting the POR signal. However, for the existing voltage divider comparison reset circuit, due to the rapid drop in power supply VDD, the comparator 110 has a relatively long response time (Tcomp) at low voltage. If the power-off-power-on reconstruction time Td(rst) is less than Tcomp, the comparator 110 output may not have flipped to "low," and the POR signal will still follow the VDD signal without resetting. Therefore, in this scenario, the existing comparator 110 cannot achieve a fast response.

[0079] In this application, since a power-on / off response unit 140 is provided, it can complete the power-on response within 1µs of the "power-off-power-on" interval Td(rst) (that is, the system completes a reset and release process during the "power-off-power-on" process).

[0080] Specifically, please combine Figure 3 In the power-on / off response unit 140, when the power supply VDD drops rapidly, the source voltage of the first switch M1 (the end of the first switch M1 connected to the power supply) in the output module 143 drops faster than the control voltage, thus Vgs (gate-source voltage) drops. When the power supply voltage drops to a certain point, the first switch M1 turns off. Similarly, the seventh switch also turns off, so V_start is pulled to "0", and the fifth switch M5 turns off. At this time, the V_glitch voltage follows the power supply VDD through the resistor, turning on the second switch M2. The charge on the first capacitor C1 is released to "0" through the second switch M2. At this time, the V_respond voltage becomes "0" and is output to the enable terminal of comparator 110. At this time, the comparator 110 enable changes from "1" to "0", and the output of comparator 110 is pulled down to "0", completing the reset of the output signal. Therefore, once the power supply voltage is detected to drop to the threshold, the power-on / off response unit 140 can quickly identify it and output a low level to the enable terminal of the comparator 110, thereby flipping the output of the comparator 110.

[0081] After powering off and waiting for Td(rst) time, the system is powered on again. This process repeats the power-on procedure. During this process, the charge on the first capacitor C1 is first released through the second switch M2, and then accumulated again through the first switch M1 after the reference voltage and the reference current are established, until the POR reset signal is released. Therefore, the power-on reset circuit provided in this application can achieve a fast response and effectively complete the reset and release of the reset signal in a "power-off-power-on" application scenario.

[0082] like Figure 5 As shown, in application scenarios where power supply glitches are present, this application can meet the requirements of glitches with an amplitude of up to 1V and a width of 10µs. That is, within this range, power supply glitches will not trigger a reset (i.e., the comparator output will flip). Figure 5 In the diagram, ΔVDD(gl) represents the difference between the maximum and minimum voltage values ​​of the voltage spike when a spike occurs, i.e., the amplitude of the spike; t w（gl）VDD This indicates the duration of the spike fluctuation.

[0083] Currently, RC architecture POR circuits can adjust the values ​​of resistor R and capacitor C to filter the power supply signal under test, thus achieving the application of power supply voltage glitches. In the comparator 110 structure POR circuit, since the input of comparator 110 is the reference voltage and the power supply voltage divider, when the power supply voltage divider is lower than the reference voltage due to glitches, comparator 110 usually directly compares the results and outputs them to the subsequent circuit.

[0084] In this application, due to the connection between the first switch M1 and the second switch M2 in the output module 143, even if there is a glitch, as long as the fluctuation amplitude does not reach the threshold, the first switch M1 will not be turned off. Therefore, the corresponding power-on and power-off units will not output a low level to the comparator 110, and the comparator 110 will not output a reset signal, thus achieving the effect that power glitch fluctuations will not trigger a reset.

[0085] Therefore, the power-on reset circuit provided in this application has at least the following advantages:

[0086] 1. The power-on reset circuit provided in this application can pre-identify and process the power supply voltage, reference voltage, and reference current during the power-on process, avoiding the drawbacks of traditional voltage divider comparators that require meeting the power-on timing of Vcomp and Vref and the comparator's abnormal operation under low voltage.

[0087] 2. This application, through the design of the power-on / off response unit, ensures rapid response of the power supply during "power-off and power-on" in various scenarios, with a minimum interval Td(rst) of 1µs (i.e., even with a 1µs power-off / power-on interval, the POR circuit can still recognize and complete the reset signal reset and release). Traditional voltage divider comparators typically have long response times (especially at low voltages), often exceeding hundreds of microseconds, with even simple comparator designs requiring milliseconds or more.

[0088] 3. Through the design of the output module and delay unit in the power-on / off response unit, this application can ensure that the POR output does not reset and the circuit continues to operate normally within a certain range of power supply glitches and durations.

[0089] Based on the above implementation method, this application embodiment also provides a chip, which includes the power-on reset circuit described above.

[0090] In summary, this application provides a power-on reset circuit and chip. The power-on reset circuit includes a comparator, a power supply voltage divider unit, a reference voltage unit, and a power-on / off response unit. The power supply voltage divider unit is connected to the first input terminal of the comparator and is also used to connect to a power supply. The reference voltage unit is connected to the second input terminal of the comparator. The power-on / off response unit is connected to the enable terminal of the comparator and the reference voltage unit. The output terminal of the comparator is used as the output of the power-on reset circuit. The reference voltage unit generates a reference voltage and a reference current after the operating state is established. The power-on / off response unit outputs a de-enabled signal to the enable terminal of the comparator when the reference voltage and reference current are not fully established, so that the comparator does not work. The power-on / off response unit also outputs an enable signal to the enable terminal of the comparator after the reference voltage and reference current are established, so as to drive the comparator to release the reset signal. The power-on reset circuit provided in this application adds a power-on / off response unit to the traditional voltage divider comparison reset circuit architecture. It only outputs an enable signal to the enable terminal of the comparator after the reference voltage and the reference current are fully established. This ensures that the comparator will only release the reset signal within a stable operating voltage range. It can simultaneously accommodate both fast and slow power-on application scenarios, making the use of the power-on reset circuit more flexible.

[0091] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0092] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A power-on reset circuit, characterized by comprising: The power-on reset circuit comprises a comparator, a power supply voltage dividing unit, a reference voltage unit and a power-on / off response unit, the power supply voltage dividing unit is connected with a first input end of the comparator, and the power supply voltage dividing unit is also used for connecting a power supply, the reference voltage unit is connected with a second input end of the comparator, the power-on / off response unit is connected with an enable end of the comparator and the reference voltage unit, and an output end of the comparator is used as an output of the power-on reset circuit; The reference voltage unit is used for generating a reference voltage and a reference current after a working state is established; The power-on / off response unit is used for outputting a non-enable signal to the enable end of the comparator to make the comparator not work when the reference voltage and the reference current are not completely established; The power-on / off response unit is also used for outputting an enable signal to the enable end of the comparator to drive the comparator to release a reset signal when the reference voltage and the reference current are established; The power-on / off response unit comprises an input module, a pull-down module and an output module, the input module and the output module are connected with the power supply, and the input module, the pull-down module and the output module are connected in sequence, the input module is used for receiving the reference voltage and the reference current, and the output module is connected with the enable end of the comparator; The output module comprises a first switch tube, a second switch tube, a driving assembly and a first capacitor, one end of the first switch tube is connected with the power supply, the other end is connected with one end of the second switch tube, the other end of the second switch tube is grounded, the control end of the second switch tube is connected to the power supply through the driving assembly, the driving assembly is also connected with the pull-down module, the control end of the first switch tube is connected with the input module, the connection place of the first switch tube and the second switch tube is used as an output port of the output module, and the output port is grounded through the first capacitor; When the power supply is powered on and the reference voltage and the reference current are not completely established, the first switch tube is turned off, and the second switch tube is turned on; When the reference voltage and the reference current are established, the first switch tube is turned on, and the second switch tube is turned off.

2. The power-on reset circuit of claim 1, wherein, The output module further comprises a first inverter and a second inverter, the input end of the first inverter is connected with the output port of the output module, the output end of the first inverter is connected with the input end of the second inverter, and the output end of the second inverter is connected with the enable end of the comparator.

3. The power-on reset circuit of claim 1, wherein, The driving assembly comprises a first resistor and a second capacitor, one end of the first resistor is connected with the power supply, the other end of the first resistor is connected with one end of the second capacitor, the control end of the second switch tube and the pull-down module respectively, and the other end of the second capacitor is grounded.

4. The power-on reset circuit of claim 1, wherein, The input module comprises a current mirror, a third switch tube and a third resistor, the current mirror is connected with the power supply, and the current mirror is connected with the output module, one end of the third switch tube is connected with the input end of the current mirror, the other end of the third switch tube is connected with the reference current, the control end of the third switch tube is used for receiving the reference voltage, one end of the third resistor is connected with the output end of the current mirror and the pull-down module, and the other end of the third resistor is grounded; wherein, When the reference voltage and the reference current are established, the current mirror is used for copying the input end current to the output end, and providing a driving voltage for the pull-down module.

5. The power-on reset circuit of claim 1, wherein, The pull-down module comprises a third capacitor, a fourth switch tube and a fifth switch tube, one end of the fourth switch tube is connected with the output module, the other end of the fourth switch tube is connected with one end of the fifth switch tube, the control end of the fourth switch tube is used for receiving the reference voltage, the other end of the fifth switch tube is grounded, the control end of the fifth switch tube is connected with one end of the third capacitor and the input module, and the other end of the third capacitor is grounded; wherein, When the reference voltage and the reference current are established, the fourth switch tube and the fifth switch tube are turned on.

6. The power-on reset circuit of claim 1, wherein, The power-on reset circuit further comprises a delay unit, and the delay unit is connected with the output end of the comparator; wherein, The delay unit is used for filtering and shaping the output of the comparator.

7. The power-on reset circuit of claim 6, wherein, The delay unit comprises a third inverter and a fourth inverter, the input end of the third inverter is connected with the output end of the comparator, the output end of the third inverter is connected with the input end of the fourth inverter, and the output end of the fourth inverter is used for connecting a subsequent circuit.

8. A chip, characterized by The chip comprises the power-on reset circuit according to any one of claims 1 to 7.

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