A primary voltage reduction and power-on reset circuit

Abstract

The application discloses a primary voltage reduction and power-on reset circuit and belongs to the technical field of power management. The application circuit is applied to an integrated circuit chip with high-voltage input, is used for providing a primary voltage reduction power supply PRE_VCC for internal circuits with higher priority and higher power supply requirement in a system, and integrates a power-on reset function. Through the circuit design of the application, two-stage voltage reduction and smooth switching from high voltage VCC_HV to medium voltage PRE_VCC and then to precision power supply VCC are realized, the system is ensured to start quickly, and the final high-precision power supply requirement is met. The integrated power-on reset function effectively protects the system at low voltage and prevents the chip from malfunctioning when the power supply is insufficient. The high-performance requirement of the whole system on the power supply is met.

Description

Technical Field

[0001] This application belongs to the field of power management technology, and in particular relates to a primary step-down and power-on reset circuit. Background Technology

[0002] In modern high-voltage input integrated circuit systems, it is typically necessary to stably step down an external high-voltage power supply to power the low-voltage analog circuit modules inside the chip. To achieve this, linear regulators (such as low-dropout linear regulators, LDOs) are widely used in the chip's internal power management system. LDOs have advantages such as simple structure, low output ripple, and low noise, making them suitable for providing stable operating voltages for analog circuits with high power quality requirements (such as bandgap references, operational amplifiers, analog-to-digital converters, etc.).

[0003] However, the LDO and its control circuitry also require an initial power supply to start and function properly. During the initial power-up phase, since the LDO has not yet established a stable output voltage, the entire chip's power management system faces a "chicken-or-egg" startup problem. Therefore, a primary buck circuit is typically introduced before the LDO to provide a temporary, initially stable operating voltage for critical modules (such as the bandgap reference, undervoltage lockout circuit, and LDO control logic) during system startup. This primary power supply is usually referred to as the "pre-supply voltage" or "startup power supply," and is denoted as PRE_VCC in this application.

[0004] The setup speed, voltage stability, and switching strategy between PRE_VCC and subsequent main power supplies (such as VCC output from an LDO) directly affect the overall chip's startup reliability, power integrity, and system performance. In traditional solutions, PRE_VCC is typically generated by simple resistor dividers, Zener diode regulators, or basic series regulators. However, these methods have the following technical problems:

[0005] Low voltage accuracy and large temperature drift: Traditional primary step-down circuits lack precise control over the output voltage, resulting in large fluctuations in PRE_VCC under different process angles, temperatures and load conditions, making it difficult to meet the stable operation requirements of modules with strict tolerance requirements for supply voltage (such as bandgap reference sources).

[0006] Lack of smooth switching mechanism: After the system starts up, if there is no reasonable switching control between PRE_VCC and the VCC output by the subsequent LDO, it may cause the power supply voltage to drop or glitches, which may cause internal circuit malfunctions or resets, affecting the reliability of the system.

[0007] Lack of integrated power-on reset function: Existing primary power supply circuits are usually designed independently of the reset circuit and fail to work effectively together, which may lead to problems such as uncertain logic state and uninitialized registers during the power-on process.

[0008] Sensitive to process deviations and device mismatches: Under advanced CMOS processes, there are significant process deviations and random mismatches in parameters such as device threshold voltage and mobility. Traditional circuit structures have not been optimized for this, resulting in significant differences in the output voltage of PRE_VCC between different chips, which reduces product consistency and yield.

[0009] Therefore, there is an urgent need for an integrated, highly reliable primary step-down circuit that can quickly establish a stable PRE_VCC voltage during system startup to power critical modules. At the same time, the circuit should have good process robustness to ensure that the output voltage remains within the allowable deviation range under various process corners and mismatch conditions. In addition, it should support smooth switching between the output VCC of the subsequent LDO and integrate a power-on reset function to improve the startup reliability and performance of the entire power management system. Summary of the Invention

[0010] The purpose of this application is to overcome the problems of the prior art by disclosing a primary step-down and power-on reset circuit, which is used to provide a primary step-down power supply PRE_VCC for internal circuits with high priority and high power supply requirements in the system. The PRE_VCC generated by this invention starts up quickly and supplies power to the primary circuit of the system. After the system starts up, the power supply switches from PRE_VCC to VCC to meet the high performance requirements of the entire system for power supply.

[0011] The objective of this application is achieved through the following technical solution:

[0012] A primary buck converter and power-on reset circuit, comprising: long-channel NMOS devices NLD1, NMOS transistors NM1, NMOS transistors NM2, NMOS transistors NM3, NMOS transistors NM4, NMOS transistors NM5, NMOS transistors NM6, power NMOS transistor NLD2, PMOS current mirror transistors PLD1, PMOS current mirror transistors PLD2, PMOS current mirror transistors PLD3, PMOS switching transistor PMOS1, resistors R1, R2, R3, R4, capacitors C1 and C2, a Schmitt trigger and a buffer, as well as a high-voltage power supply input terminal VCC_HV, a primary buck converter output terminal PRE_VCC, a subsequent power supply input terminal VCC, a power-on reset signal output terminal RSTN_POR, and a power-ready signal input terminal VCC_OK;

[0013] The high-voltage power supply input terminal VCC_HV is connected to the gate of the long-channel NMOS device NLD1 and the drain of the NMOS transistor NM1 through resistor R1, so that the long-channel NMOS device NLD1 is turned on and generates an initial current I_INI.

[0014] The source of the long-channel NMOS device NLD1 is connected to the upper end of resistor R2, and the lower end of resistor R2 is connected to the source of NMOS transistor NM1. The source of NMOS transistor NM1 is grounded.

[0015] The drain of the long-channel NMOS device NLD1 is connected to the drain of PMOS transistor PLD1. The gate and drain of PMOS transistor PLD1 are shorted to form a diode connection. The gates of PMOS transistors PLD1, PMOS transistors PLD2, and PMOS transistors PLD3 are connected to each other. The sources of PMOS transistors PLD1, PMOS transistors PLD2, and PMOS transistors PLD3 are all connected to the high-voltage power supply input terminal VCC_HV, forming a current mirror structure that mirrors the initial current I_INI to the three working branches in a 1:1:1 ratio.

[0016] The drain of PLD2 is connected to the drain of NMOS transistor NM2. NMOS transistors NM2, NMOS transistor NM3, and NMOS transistor NM4 are connected in series and all use diode connections. The source node voltage of NMOS transistor NM2 is defined as the driving voltage PRE_VCCDRV. The driving voltage PRE_VCCDRV is supplied to the gate of NMOS transistor NM5 and the gate of power transistor NLD2. The source of NM5 is grounded and the drain is connected to node VX.

[0017] The source of the PMOS transistor PLD3 is connected to the upper end of resistor R3, and the lower end of R3 is connected to node VX; at the same time, node VX is also connected to the drain of NMOS transistor NM6 and the input of Schmitt trigger; the source of NM6 is grounded, and the gate of NM6 is connected to the output of Schmitt trigger; the output of Schmitt trigger is buffered and outputs the power-on reset signal RSTN_POR.

[0018] The power transistor NLD2 is configured as a source follower. The drain of the power transistor NLD2 is connected to the high-voltage power input terminal VCC_HV, and the source is defined as the output node PRE_VCC. The driving voltage PRE_VCCDRV drives the power transistor NLD2 to generate an output voltage, which is output through the output node PRE_VCC.

[0019] According to a preferred embodiment, after the initial current I_INI flows through the long-channel NMOS device NLD1, it is applied to the resistor R2 to generate a voltage drop, which drives the NMOS transistor NM1 to turn on. After the NMOS transistor NM1 turns on, it pulls down the gate voltage of the long-channel NMOS device NLD1. After reaching equilibrium, the initial current I_INI is equal to the gate-source voltage of the long-channel NMOS device NLD1 divided by the resistor R2.

[0020] According to a preferred embodiment, the gate and drain of the NMOS transistor NM2 are shorted and then connected to the drain of the PMOS transistor PLD2. The source of the NMOS transistor NM2 is connected to the drain of the NMOS transistor NM3. The gate and drain of the NMOS transistor NM3 are shorted. The source of the NMOS transistor NM3 is connected to the drain of the NMOS transistor NM4. The gate and drain of the NMOS transistor NM4 are shorted. The source of the NMOS transistor NM4 is grounded.

[0021] According to a preferred embodiment, the aspect ratio of the NMOS transistor NM5 is designed to be 3 times that of NM2, so that under the same gate drive voltage PRE_VCCDRV, the drain current of the NMOS transistor NM5 is 3 times the current of the NMOS transistor NM2, that is, 3 times I_INI, and the corresponding branch current is amplified by the gate voltage drive.

[0022] According to a preferred embodiment, the output node PRE_VCC is also connected to the source of PMOS transistor PMOS1, the drain of PMOS transistor PMOS1 is connected to the power input terminal VCC, and the gate is connected to the control signal VCC_OK.

[0023] According to a preferred embodiment, the VCC_OK signal turns off PMOS transistor PMOS1 before the power input VCC of the subsequent stage is fully started.

[0024] According to a preferred embodiment, when the power input terminal VCC of the subsequent stage is started up, the output voltage of the power input terminal VCC of the subsequent stage is much greater than the output voltage of the output node PRE_VCC. At the same time, the VCC_OK signal flips, the channel of PMOS transistor PMOS1 is fully turned on, and the output node PRE_VCC is forcibly clamped to the output voltage of the power input terminal VCC of the subsequent stage. At this time, the power supply is completely switched to the power supply voltage of the power input terminal VCC of the subsequent stage.

[0025] According to a preferred embodiment, the gate of the power transistor NLD2 is connected to the positive terminal of capacitor C1, and the negative terminal of capacitor C1 is grounded.

[0026] According to a preferred embodiment, the output node PRE_VCC is connected to one end of resistor R4, and the other end of R4 is grounded.

[0027] According to a preferred embodiment, the output node PRE_VCC is also connected to the positive terminal of the filter capacitor C2, and the negative terminal of C2 is grounded.

[0028] The aforementioned main solution and its various further alternative solutions can be freely combined to form multiple solutions, all of which are solutions that can be adopted and are claimed in this application. Those skilled in the art, after understanding the solution of this application, will realize that there are many combinations based on the prior art and common general knowledge, all of which are technical solutions to be protected in this application, and will not be exhaustively listed here.

[0029] The beneficial effects of this application are:

[0030] This application's circuit is applied in high-voltage input integrated circuit chips to provide a primary step-down power supply PRE_VCC for internal circuits with high priority and high power supply requirements in the system, and integrates a power-on reset function. In high-voltage input chips, a stable step-down module is usually required to power the internal analog circuits. Linear regulators such as LDOs are conventionally used. However, the LDO itself and internal circuits with higher priority than the LDO (such as bandgap reference sources, undervoltage protection modules, etc.) also need to be powered by the stepped-down power supply. This invention is a primary step-down circuit designed to meet this requirement.

[0031] The circuit design of this invention achieves a two-stage step-down and smooth switching from high-voltage VCC_HV to medium-voltage PRE_VCC and then to the precision power supply VCC. This ensures both rapid system startup and meets the final high-precision power supply requirements. Simultaneously, the integrated power-on reset function effectively protects the system under low voltage conditions, preventing chip malfunctions due to insufficient power. This satisfies the high-performance power requirements of the entire system. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the primary step-down and power-on reset circuit of this application.

[0033] Figure 2 This is a schematic diagram of the voltage reduction switching process in this application. Detailed Implementation

[0034] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0035] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0036] In the description of this application, it should also be noted that, unless otherwise expressly specified and limited, the terms "set up," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0037] Furthermore, it should be noted that unless otherwise specified in this application, the specific structures, connections, positions, power sources, etc. involved are all things that a person skilled in the art can know without creative effort based on the prior art.

[0038] Example

[0039] refer to Figure 1 and Figure 2 As shown, this application discloses a primary buck and power-on reset circuit. This circuit is applied to high-voltage input integrated circuit chips to provide a primary buck power supply PRE_VCC for internal circuits with high priority and high power supply requirements, and integrates a power-on reset function. In high-voltage input chips, a stable buck module is typically required to power internal analog circuits. Linear regulators such as LDOs are commonly used, but the LDO itself and internal circuits with higher priority than the LDO (such as bandgap reference sources and undervoltage protection modules) also require a bucked power supply. This application is a primary buck circuit designed to address this requirement. When the system starts up, the PRE_VCC generated by this application is quickly generated and supplies power to the primary circuit of the system. After the system starts up, the power supply switches from PRE_VCC to VCC (generated by the subsequent LDO circuit, which has high accuracy), meeting the high-performance power requirements of the entire system.

[0040] For PRE_VCC to switch smoothly to VCC, the VCC voltage must always be greater than PRE_VCC. Furthermore, PRE_VCC needs to meet the minimum operating voltage requirements of the internal bandgap reference source, which imposes limitations on the operating voltage and deviation range of PRE_VCC. This application optimizes the structure and parameters of the corresponding power supply generation to meet its voltage deviation range limitations under process corner and random mismatch conditions.

[0041] The primary buck and power-on reset circuit of this application includes: long-channel NMOS devices NLD1, NMOS transistors NM1, NMOS transistors NM2, NMOS transistors NM3, NMOS transistors NM4, NMOS transistors NM5, NMOS transistors NM6, power NMOS transistor NLD2, PMOS current mirror transistors PLD1, PMOS current mirror transistors PLD2, PMOS current mirror transistors PLD3, PMOS switching transistor PMOS1, resistors R1, R2, R3, R4, capacitors C1 and C2, a Schmitt trigger and a buffer, as well as a high-voltage power supply input terminal VCC_HV, a primary buck output terminal PRE_VCC, a power supply input terminal VCC, a power-on reset signal output terminal RSTN_POR, and a power-ready signal input terminal VCC_OK.

[0042] Preferably, the high-voltage power supply input terminal VCC_HV is connected to the gate of the long-channel NMOS device NLD1 and the drain of the NMOS transistor NM1 via resistor R1, thereby turning on the long-channel NMOS device NLD1 and generating an initial current I_INI. The resistor R1 serves as a current-limiting protection to prevent excessive inrush current at the moment of power-on.

[0043] Preferably, the source of the long-channel NMOS device NLD1 is connected to the upper end of resistor R2, and the lower end of resistor R2 is connected to the source of NMOS transistor NM1, with the source of NMOS transistor NM1 grounded. After the initial current I_INI flows through the long-channel NMOS device NLD1, it creates a voltage drop across resistor R2, driving NMOS transistor NM1 to turn on. Once NMOS transistor NM1 is turned on, it pulls down the gate voltage of the long-channel NMOS device NLD1. After reaching equilibrium, the initial current I_INI is equal to the gate-source voltage of the long-channel NMOS device NLD1 divided by resistor R2. This current generation method uses a VGS / R current source structure, which is simple and has a fast start-up time.

[0044] Preferably, the drain of the long-channel NMOS device NLD1 is connected to the drain of the PMOS transistor PLD1, the gate and drain of the PMOS transistor PLD1 are shorted to form a diode connection, and the gates of PMOS transistors PLD1, PMOS transistors PLD2 and PMOS transistors PLD3 are connected to each other. The sources of PMOS transistors PLD1, PMOS transistors PLD2 and PMOS transistors PLD3 are all connected to the high-voltage power supply input terminal VCC_HV, forming a current mirror structure that mirrors the initial current I_INI to the three working branches in a 1:1:1 ratio.

[0045] Preferably, the drain of PMOS transistor PLD2 is connected to the drain of NMOS transistor NM2. NMOS transistors NM2, NMOS transistors NM3, and NMOS transistors NM4 are connected in series and all use a diode connection (gate and drain short-circuited). After the current in the PMOS transistor PLD2 branch is applied to NM2, NM3, and NM4, a gate-source voltage VGS is generated across each of the three transistors. Therefore, the source node voltage of NM2 is approximately three times VGS, and this node is defined as the drive voltage PRE_VCCDRV.

[0046] Specifically, the gate and drain of NMOS transistor NM2 are shorted and then connected to the drain of PMOS transistor PLD2. The source of NMOS transistor NM2 is connected to the drain of NMOS transistor NM3. The gate and drain of NMOS transistor NM3 are shorted. The source of NMOS transistor NM3 is connected to the drain of NMOS transistor NM4. The gate and drain of NMOS transistor NM4 are shorted. The source of NMOS transistor NM4 is grounded.

[0047] Preferably, the driving voltage PRE_VCCDRV is supplied to the gate of NMOS transistor NM5 and the gate of power transistor NLD2, wherein the source of NM5 is grounded and the drain is connected to node VX.

[0048] Furthermore, the aspect ratio of the NMOS transistor NM5 is designed to be 3 times that of NM2, so that under the same gate drive voltage PRE_VCCDRV, the drain current of the NMOS transistor NM5 is 3 times that of the NMOS transistor NM2, that is, 3 times I_INI. The corresponding branch current is amplified by the gate voltage drive method, rather than the traditional current mirror method.

[0049] Preferably, the source of PMOS transistor PLD3 is connected to the upper end of resistor R3, and the lower end of R3 is connected to node VX; at the same time, node VX is also connected to the drain of NMOS transistor NM6 and the input of Schmitt trigger; the source of NM6 is grounded, and the gate of NM6 is connected to the output of Schmitt trigger; the output of Schmitt trigger is buffered and outputs a power-on reset signal RSTN_POR.

[0050] The function of resistor R3 is to quickly provide a high-level initial state to node VX before the current source is activated, and to make the initial state of RSTN_POR zero (reset state). When VCC_HV is greater than 3 times VGS voltage, NM5 receives 3 times the mirror current. This current is always greater than the 1 times I_INI current provided by PLD3, which pulls point VX low. After passing through the Schmitt trigger and buffer, the output RSTN_POR signal flips to a high level (reset). At the same time, the Schmitt trigger output signal flips, which turns on NM6. NM6 further pulls point VX low, forming positive feedback to generate hysteresis characteristics and prevent the reset signal from oscillating near the critical voltage.

[0051] Preferably, the power transistor NLD2 is configured as a source follower. The gate of the power transistor NLD2 is connected to the PRE_VCCDRV node, the drain is connected to the high-voltage power supply input terminal VCC_HV, and the source is defined as the output node PRE_VCC. The driving voltage PRE_VCCDRV drives the power transistor NLD2 to generate an output voltage, which is output through the output node PRE_VCC. Since the three transistors NM2, NM3, and NM4 are connected in series to generate a driving voltage of approximately 3 times VGS, after being source-followed by NLD2, the output PRE_VCC is approximately equal to PRE_VCCDRV minus the gate-source voltage of NLD2. Therefore, PRE_VCC is approximately equal to twice the VGS voltage, typically in the range of 2 to 3 volts, which meets the minimum operating voltage requirements of circuits such as bandgap reference sources.

[0052] Preferably, the gate of power transistor NLD2 is connected to the positive terminal of capacitor C1, and the negative terminal of capacitor C1 is grounded. Capacitor C1 is a large-capacity capacitor used to cope with the dynamic response of a large current load. When the load current suddenly increases, C1 provides transient charge to maintain the stability of the output voltage.

[0053] Preferably, the output node PRE_VCC is connected to one end of resistor R4, and the other end of R4 is grounded. R4 is a dummy load with a large resistance; its power consumption is negligible during normal operation. Its function is to prevent abnormal rise in output voltage when the power transistor leaks. The output node PRE_VCC is also connected to the positive terminal of filter capacitor C2, and the negative terminal of C2 is grounded. C2 is used to filter the output voltage, removing high-frequency ripple.

[0054] Preferably, the output node PRE_VCC is also connected to the source of PMOS transistor PMOS1, the drain of PMOS transistor PMOS1 is connected to the power input terminal VCC, and the gate is connected to the control signal VCC_OK.

[0055] Before the power input VCC of the subsequent stage is fully powered on, the VCC_OK signal keeps PMOS transistor PMOS1 in the off state. During the startup process, due to the existence of the parasitic body diode of PMOS1, when VCC minus PRE_VCC is greater than the diode's forward voltage (approximately 0.7 volts), the parasitic body diode begins to conduct, and PRE_VCC is gradually pulled high.

[0056] When the power input VCC of the subsequent stage completes startup, the output voltage of VCC is much higher than the output voltage of the output node PRE_VCC. Simultaneously, the VCC_OK signal flips, the channel of PMOS transistor PMOS1 is fully turned on, and the output node PRE_VCC is forcibly clamped to the output voltage of the power input VCC of the subsequent stage. At this point, the power supply is completely switched to the voltage of the power input VCC of the subsequent stage. This switching method utilizes a parasitic diode to achieve soft start, resulting in a smooth switching process that does not cause voltage surges to the load circuit.

[0057] This invention first simplifies the structure by using a VGS / R current source to generate a bias current, which is then applied to three diode-connected MOSFETs to produce a drive voltage. Since VGS equals the threshold voltage VTH plus the overdrive voltage VOV, the PRE_VCC output voltage is approximately equal to 3 times VGS minus the VGS of NLD2, which is approximately equal to 2 times VGS. Secondly, the parameters are optimized. Because the threshold voltage VTH is drastically affected by process angle variations, inverted ratio transistors with larger aspect ratios are used for the key MOSFETs NM1, NM2, NM3, and NM4 that generate the drive voltage. This increases the overdrive voltage VOV, reducing the proportion of VTH in the VGS voltage and thus minimizing the impact of process variations on the output voltage.

[0058] During circuit operation, when the system is powered on, the high voltage VCC_HV is established first, supplying power to NLD1 and NM1 through resistor R1, and the initial current I_INI begins to be generated. This current is mirrored to the three branches. The current in the PLD2 branch flows through NM2, NM3, and NM4, generating the drive voltage PRE_VCCDRV. This voltage drives the power transistor NLD2 to generate the output voltage PRE_VCC. At this time, PRE_VCC rises rapidly, supplying power to the primary circuitry of the system, such as the bandgap reference source.

[0059] During the initial power-up phase, when VCC_HV is low, PRE_VCCDRV has not yet been fully established, resulting in insufficient drive from NM5. Its drain current is less than the current provided by PLD3, so node VX is pulled high by resistor R3 and the current from PLD3. When VX is high, after passing through the Schmitt trigger and buffer, RSTN_POR outputs low, and the system is in a reset state. Once VCC_HV rises sufficiently (approximately 3 times VGS), PRE_VCCDRV is fully established, and NM5 receives 3 times I_INI current, greater than the 1 times I_INI current from PLD3, rapidly pulling node VX low. After VX goes low, the Schmitt trigger output flips to high, simultaneously enabling NM6 to further pull VX low, forming positive feedback. RSTN_POR output then flips high, releasing the reset state, and the system enters normal operation.

[0060] During the stable power supply of PRE_VCC, the subsequent LDO circuit starts up, generating a more precise power supply VCC. VCC begins to build up and gradually rises. When the voltage difference between VCC and PRE_VCC exceeds approximately 0.7 volts, the parasitic body diode of PMOS1 begins to conduct, and VCC injects current into the PRE_VCC node through the body diode, gradually pulling PRE_VCC high. This process is gradual; PRE_VCC is slowly raised, and the load circuit experiences a smooth voltage change without abrupt changes. Once VCC is fully built up and stable, the VCC_OK signal flips, PMOS1 fully conducts, PRE_VCC is forcibly clamped to the VCC voltage, the power supply switching is complete, and the system is subsequently powered by the high-precision VCC.

[0061] The circuit design of this invention achieves a two-stage step-down and smooth switching from high voltage VCC_HV to medium voltage PRE_VCC and then to precision power supply VCC, ensuring both rapid system startup and meeting the final high-precision power supply requirements. Simultaneously, the integrated power-on reset function effectively protects the system under low voltage conditions, preventing chip malfunctions due to insufficient power.

[0062] In practical implementation, the channel length of long-channel NMOS devices NLD1 and NLD2 can be selected from 1 to 2 micrometers, and the width is designed according to the load current requirements, with typical values ​​ranging from 100 to 500 micrometers. NM1, NM2, NM3, and NM4 adopt a design with a large aspect ratio, which can be selected from 20 to 100, to increase the overdrive voltage VOV and reduce the impact of the threshold voltage VTH. The aspect ratio of NM5 is 3 times that of NM2 to achieve a drive capability of 3 times the current.

[0063] Resistor R1, with a resistance value ranging from 100 kΩ to 1 MΩ, serves as a current-limiting protection. The resistance value of resistor R2 determines the magnitude of the initial current I_INI, and can be selected from 10 kΩ to 100 kΩ, corresponding to an initial current of tens to hundreds of microamps. Resistor R3, with a resistance value ranging from 100 kΩ to 1 MΩ, is used for pull-up at the VX node. Resistor R4, with a resistance value ranging from 100 kΩ to 1 MΩ, acts as a dummy load.

[0064] Capacitor C1 is the gate regulator capacitor for the power transistor, with a capacitance value ranging from 10pF to 100pF. It can be an on-chip MOS capacitor or an external ceramic capacitor. Capacitor C2 is the filter capacitor, with a capacitance value ranging from 10pF to 100pF. In typical applications, the high-voltage input VCC_HV ranges from 7V to 48V, the output PRE_VCC is approximately 2 to 3V, and the typical value of the subsequent power supply VCC is 3.3V or 5V.

[0065] This application's circuit generates a highly accurate front-end buck power supply without requiring a large external energy storage capacitor. This provides a reliable power supply for high-priority internal circuits such as the bandgap reference, simplifying the design process as their voltage withstand capabilities are no longer a concern. The primary buck converter and the subsequent buck converter are effectively connected, utilizing the parasitic body diode of the PMOS transistor for smooth switching without impacting the load circuit. Simultaneously, a low-deviation power-on reset signal is generated, effectively protecting the system at low input voltages and preventing malfunctions when the power supply is unstable. The entire circuit has a simple structure, low power consumption, and is easily integrated into various high-voltage input chips.

[0066] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A primary step-down and power-on reset circuit, characterized in that, The primary voltage reduction and power-on reset circuit comprises a long-channel NMOS device NLD1, NMOS tubes NM1, NM2, NM3, NM4, NM5, NM6, a power NMOS tube NLD2, PMOS current mirror tubes PLD1, PLD2, PLD3, a PMOS switch tube PMOS1, resistors R1, R2, R3, R4, capacitors C1, C2, a Schmitt trigger and a buffer, and a high-voltage power supply input terminal VCC_HV, a primary voltage reduction output terminal PRE_VCC, a secondary power supply input terminal VCC, a power-on reset signal output terminal RSTN_POR and a power ready signal input terminal VCC_OK; The high-voltage power supply input terminal VCC_HV is connected to the gate of the long-channel NMOS device NLD1 and the drain of the NMOS tube NM1 through the resistor R1, so that the long-channel NMOS device NLD1 is turned on to generate an initial current I_INI; The source of the long-channel NMOS device NLD1 is connected to the upper end of the resistor R2, and the lower end of the resistor R2 is connected to the source of the NMOS tube NM1, and the source of the NMOS tube NM1 is grounded. The drain of the long-channel NMOS device NLD1 is connected to the drain of the PMOS tube PLD1, the gate and the drain of the PMOS tube PLD1 are short-circuited to form a diode connection, and the gates of the PMOS tubes PLD1, PLD2 and PLD3 are connected to each other, and the sources of the PMOS tubes PLD1, PLD2 and PLD3 are connected to the high-voltage power supply input terminal VCC_HV to form a current mirror structure, and the initial current I_INI is mirrored in the three working branches in a ratio of 1:1:

1. The drain of the PLD2 is connected to the drain of the NMOS tube NM2, the NMOS tubes NM2, NM3 and NM4 are connected in series and all adopt diode connection, and the source node voltage of the NMOS tube NM2 is defined as a driving voltage PRE_VCCDRV; the driving voltage PRE_VCCDRV is transmitted to the gate of the NMOS tube NM5 and the gate of the power tube NLD2, the source of the NM5 is grounded, and the drain is connected to a node VX; The source of the PMOS tube PLD3 is connected to the upper end of the resistor R3, the lower end of the resistor R3 is connected to the node VX; meanwhile, the node VX is also connected to the drain of the NMOS tube NM6 and the input terminal of the Schmitt trigger; the source of the NM6 is grounded, and the gate of the NM6 is connected to the output terminal of the Schmitt trigger; the output of the Schmitt trigger is outputted as a power-on reset signal RSTN_POR after being buffered. The power tube NLD2 is configured as a source follower, the drain of the power tube NLD2 is connected to a high-voltage power input terminal VCC_HV, and the source is defined as an output node PRE_VCC, wherein a driving voltage PRE_VCCDRV drives the power tube NLD2 to generate an output voltage output through the output node PRE_VCC. The output node PRE_VCC is also connected to the source of a PMOS tube PMOS1, the drain of the PMOS tube PMOS1 is connected to a subsequent power input terminal VCC, and the gate is connected to a control signal VCC_OK.

2. The primary brown-out and power-on reset circuit of claim 1, wherein, After the initial current I_INI flows through the long-channel NMOS device NLD1, a voltage drop is generated on the resistor R2, the NMOS tube NM1 is turned on, and the gate voltage of the long-channel NMOS device NLD1 is pulled low after the NMOS tube NM1 is turned on. After balancing, the initial current I_INI is equal to the gate-source voltage of the long-channel NMOS device NLD1 divided by the resistor R2.

3. The primary brown-out and power-on reset circuit of claim 1, wherein, The gate and drain of the NMOS tube NM2 are connected to the drain of the PMOS tube PLD2 after being short-circuited, the source of the NMOS tube NM2 is connected to the drain of the NMOS tube NM3, the gate and drain of the NMOS tube NM3 are short-circuited, the source of the NMOS tube NM3 is connected to the drain of the NMOS tube NM4, the gate and drain of the NMOS tube NM4 are short-circuited, and the source of the NMOS tube NM4 is grounded.

4. The primary brown-out and power-on reset circuit of claim 1, wherein, The width-length ratio of the NMOS tube NM5 is designed to be 3 times that of the NM2, so that under the same gate driving voltage PRE_VCCDRV, the drain current of the NMOS tube NM5 is 3 times that of the NMOS tube NM2, that is, 3 times I_INI, and the branch current is amplified by means of gate voltage driving.

5. The primary brown-out and power-on reset circuit of claim 1, wherein, Before the subsequent power input terminal VCC is started, the VCC_OK signal makes the PMOS tube PMOS1 in an off state.

6. The primary voltage-buck and power-on reset circuit of claim 5, wherein, When the subsequent power input terminal VCC is started, at this time, the output voltage of the subsequent power input terminal VCC is greater than the output voltage of the output node PRE_VCC, and the VCC_OK signal is inverted, the channel of the PMOS tube PMOS1 is completely turned on, and the output node PRE_VCC is forced to be clamped to the output voltage of the subsequent power input terminal VCC. At this time, the power supply is completely switched to the subsequent power input terminal VCC voltage supply.

7. The primary brown-out and power-on reset circuit of claim 1, wherein, The gate of the power tube NLD2 is connected to the positive electrode of a capacitor C1, and the negative electrode of the capacitor C1 is grounded.

8. The primary brown-out and power-on reset circuit of claim 1, wherein, The output node PRE_VCC is connected to one end of a resistor R4, and the other end of the R4 is grounded.

9. The primary brown-out and power-on reset circuit of claim 1, wherein, The output node PRE_VCC is also connected to the positive electrode of a filter capacitor C2, and the negative electrode of the C2 is grounded.

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