Power-on reset circuit, chip and electronic product

Abstract

The invention provides a power-on reset circuit, a chip and an electronic product, and the circuit comprises a current mirror circuit which is provided with an input end and an output end; the biasing circuit comprises a first branch circuit, a second branch circuit and a resistance circuit, the first end of the first branch circuit is coupled to the input end of the current mirror circuit, the first end of the second branch circuit is coupled to the output end of the current mirror circuit, and the resistance circuit is coupled to the second end of the first branch circuit and the second end of the second branch circuit; and the driving circuit is provided with an input end coupled to the output end of the current mirror circuit and an output end for providing a power-on reset signal. The power-on reset circuit, the chip and the electronic product are simple in structure, high in anti-interference capability, low in power consumption and small in layout area.

Description

Technical Field

[0001] This invention relates to the field of power electronics, and in particular to a power-on reset circuit, a chip, and an electronic product. Background Technology

[0002] A power-on reset (POR) circuit is a circuit that triggers a system reset during power-on or voltage rise, preventing system errors caused by random states during power-on. It serves as the "first line of defense" for reliable startup of electronic systems and is widely used in embedded systems, industrial control, automotive electronics, and other fields.

[0003] Existing power-on reset circuits often have degeneracy points in their bias circuits, requiring a startup circuit to function properly, resulting in complex circuit structures; the circuit's trigger voltage lacks hysteresis when the power supply voltage rises and falls, making it susceptible to noise interference; in addition, they generally suffer from large quiescent current.

[0004] Therefore, how to propose a power-on reset circuit structure that is simple in structure, has strong anti-interference ability, and low power consumption has become one of the problems that urgently need to be solved by those skilled in the art.

[0005] It should be noted that the above description of the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of the present invention and facilitating understanding by those skilled in the art. It should not be assumed that the above technical solutions are known to those skilled in the art simply because they have been described in the background section of this invention. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a power-on reset circuit, chip, and electronic product to solve the problems of complex structure, weak anti-interference ability, and high power consumption of the power-on reset circuit in the prior art.

[0007] To achieve the above and other related objectives, the present invention provides a power-on reset circuit, the power-on reset circuit comprising at least:

[0008] A current mirror circuit has an input terminal and an output terminal;

[0009] A bias circuit includes a first branch, a second branch, and a resistor circuit. A first terminal of the first branch is coupled to the input terminal of the current mirror circuit. A first terminal of the second branch is coupled to the output terminal of the current mirror circuit. The resistor circuit is coupled to the second terminals of both the first and second branches.

[0010] The driving circuit has an input terminal coupled to the output terminal of the current mirror circuit and an output terminal that provides a power-on reset signal.

[0011] Optionally, the bias circuit includes:

[0012] The first branch includes a first NMOS transistor, having a drain coupled to the input terminal of the current mirror circuit and a source coupled to the first terminal of the resistor circuit;

[0013] The second branch includes a second NMOS transistor, having its drain coupled to the output terminal of the current mirror circuit and its source coupled to the first terminal of the resistor circuit; and

[0014] The resistor circuit has a first end coupled to the second end of the first branch and the second end of the second branch, a second end coupled to the ground end, and an intermediate end coupled to the gate of the first NMOS transistor and the second NMOS transistor.

[0015] The first NMOS transistor and the second NMOS transistor include depletion-type NMOS transistors.

[0016] Alternatively, the resistor circuit may include a first resistor between its first terminal and its intermediate terminal.

[0017] Alternatively, an adjustable resistor is included between the middle and second terminals of the resistor circuit, the adjustable resistor adjusting its resistance value based on the voltage at the output terminal of the current mirror circuit.

[0018] Alternatively, the resistor circuit includes a second resistor and a third resistor connected in series between the middle terminal and the second terminal, and the power-on reset circuit further includes a resistor adjustment circuit, which includes:

[0019] A control switch having a first terminal coupled to a second resistor and a third resistor, and a control terminal coupled to the output terminal of the current mirror circuit; and

[0020] The fourth resistor has a first end coupled to the second end of the control switch and a second end coupled to the ground.

[0021] Alternatively, the power-on reset circuit further includes a variable resistor circuit, the variable resistor circuit comprising:

[0022] A bypass switch has a first terminal coupled to the input terminal of the current mirror circuit, a second terminal coupled to the first terminal of the first branch of the bias circuit, and a control terminal for receiving the power-on reset signal.

[0023] The fifth resistor is connected in parallel with the bypass switch.

[0024] Alternatively, the fifth resistor includes a third NMOS transistor, the drain of which is coupled to the input terminal of the current mirror circuit, the source of which is coupled to the first terminal of the first branch of the bias circuit, and the gate of which receives the power supply voltage.

[0025] Optionally, the power-on reset circuit further includes a pull-up circuit, which is coupled between the power supply voltage and the output terminal of the current mirror circuit, and is turned on or off based on the power-on reset signal, wherein when the pull-up circuit is turned on, the output terminal of the current mirror circuit is pulled up to the power supply voltage.

[0026] Optionally, the power-on reset circuit further includes a first enable circuit, which is connected in series in the path between the second terminal of the first branch and the ground terminal and is controlled by an enable signal.

[0027] Optionally, the power-on reset circuit further includes a second enable circuit, which is coupled between the power supply voltage and the input terminal of the drive circuit and is controlled by an enable signal.

[0028] Optionally, a first PMOS transistor and a second PMOS transistor are used; the sources of the first PMOS transistor and the second PMOS transistor are coupled to a power supply voltage, and the gates are coupled to the drain of the first PMOS transistor; the drain of the first PMOS transistor serves as the input terminal of the current mirror structure, and the drain of the second PMOS transistor serves as the output terminal of the current mirror structure.

[0029] Optionally, the driving circuit includes an inverter.

[0030] To achieve the above and other related objectives, the present invention also provides a chip, the chip comprising at least the above-described power-on reset circuit.

[0031] To achieve the above and other related objectives, the present invention also provides an electronic product, which includes at least the power-on reset circuit described above.

[0032] As described above, the power-on reset circuit, chip, and electronic product of the present invention have the following beneficial effects:

[0033] 1. The power-on reset circuit, chip and electronic product of the present invention use a depletion-type NMOS transistor and a resistor to form a self-biased structure, which achieves low static current while ensuring a relatively small resistance value, thereby ensuring extremely low static power consumption and a small layout area.

[0034] 2. The self-biased structure of the present invention does not require a startup circuit, has a simple structure, and can further reduce the layout area.

[0035] 3. The power-on reset circuit, chip, and electronic product of the present invention control the relationship between the series and parallel resistors and the bias current through the feedback control of the power-on reset signal, thereby adjusting the self-bias resistor and bias current to set different threshold voltages during power-on and power-off to obtain hysteresis and improve the ability to resist noise interference.

[0036] 4. The hysteresis function of the present invention does not require the addition of an extra hysteresis comparator circuit, reducing the use of MOS devices and the consumption of layout area, thereby reducing costs.

[0037] 5. The threshold voltage of the power-on reset circuit, chip, and electronic product of the present invention is less affected by PVT, and can simultaneously accommodate both fast and slow power-on scenarios.

[0038] 6. The power-on reset circuit, chip, and electronic product of the present invention add a positive feedback loop at the output end to avoid the circuit being near the threshold voltage for a long time and reduce the dynamic current. Attached Figure Description

[0039] Figure 1 The diagram shown is a schematic of an existing power-on reset circuit.

[0040] Figure 2 The diagram shown is a schematic diagram of the first structure of the power-on reset circuit of the present invention.

[0041] Figure 3 The diagram shown is a second structural schematic of the power-on reset circuit of the present invention.

[0042] Figure 4 The diagram shown is a third structural schematic of the power-on reset circuit of the present invention.

[0043] Figure 5 The diagram shown is a fourth structural schematic of the power-on reset circuit of the present invention.

[0044] Figure 6 The diagram shown is a fifth structural schematic of the power-on reset circuit of the present invention.

[0045] Figure 7 The diagram shown is a sixth structural schematic of the power-on reset circuit of the present invention.

[0046] Figure 8 The diagram shown is a seventh structural schematic of the power-on reset circuit of the present invention.

[0047] Figure 9 The diagram shown is an eighth structural schematic of the power-on reset circuit of the present invention.

[0048] Figure 10 The diagram shown illustrates the working principle of the power-on reset circuit of this invention.

[0049] Component designation explanation

[0050] 1-Existing power-on reset circuit; 11-Self-biased current generator; 12-Start-up circuit; 13-Output stage; 2-Power-on reset circuit; 21-Current mirror circuit; 22-Bias circuit; 221-First branch; 222-Second branch; 223-Resistor circuit; 22a-First resistor unit; 22b-Second resistor unit; 23-Drive circuit; 24-Resistor adjustment circuit; 25-Variable resistor circuit; 26-Pull-up circuit; 27-First enable circuit; 28-Second enable circuit. Detailed Implementation

[0051] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0052] Please see Figures 1-10 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0053] Figure 1 An existing power-on reset circuit 1 includes a self-biased current generator 11, a startup circuit 12, and an output stage 13. The self-biased current generator 11 consists of NMOS transistors MNa and MNb, PMOS transistors MPa and MPb, and a resistor Ra. The current generated by the self-biased current generator 11 is directly proportional to the threshold voltage of NMOS transistor MNa and inversely proportional to the resistance Ra. The startup circuit 12 includes a resistor Rb, which solves the startup problem of the self-biased current generator 11 by applying a current proportional to the power supply voltage VDD and inversely proportional to the resistance Rb to the degeneracy point of the self-biased current generator 11. The output stage 13 includes NMOS transistors MNc and MPc, an inverter nota, and an inverter notb. This circuit exhibits a power supply insensitive response; however, it consumes a large quiescent current. To reduce the quiescent current, a resistor with a large resistance value Ra is required, which will consume a large layout area. Moreover, the trigger voltage of this circuit is equal during the rise and fall phases of the power supply voltage VDD, and there is no hysteresis. In addition, a startup circuit 12 is required in this circuit.

[0054] To address the aforementioned problems, this invention provides a power-on reset circuit that features low quiescent current, eliminates the need for a startup circuit, has a small layout area, and exhibits strong noise immunity. The structure of this power-on reset circuit is described in detail below.

[0055] Example 1

[0056] like Figure 2 As shown, this embodiment provides a power-on reset circuit 2, which includes:

[0057] Current mirror circuit 21, bias circuit 22 and drive circuit 23.

[0058] like Figure 2 As shown, the current mirror circuit 21 has an input terminal and an output terminal.

[0059] Specifically, the current mirror circuit 21 is used to mirror and amplify the current, with the current at its input terminal being amplified by a factor of n before being output from the output terminal. In this example, the current mirror circuit 21 includes a first PMOS transistor MP1 and a second PMOS transistor MP2. The sources of the first PMOS transistor MP1 and the second PMOS transistor MP2 are coupled to the power supply voltage VDD, and their gates are coupled to the drain of the first PMOS transistor MP1; the drain of the first PMOS transistor MP1 serves as the input terminal of the current mirror circuit 21, and the drain of the second PMOS transistor MP2 serves as the output terminal of the current mirror circuit 21. The width-to-length ratio of the first PMOS transistor MP1 to the second PMOS transistor MP2 is set to 1:n, where n is a number greater than 1. Any circuit structure that can achieve the current mirror function is applicable to the current mirror structure 21 of this invention, and will not be described in detail here.

[0060] like Figure 2 As shown, the bias circuit 22 includes a first branch 221, a second branch 222, and a resistor circuit 223; the first end of the first branch 221 is coupled to the input end of the current mirror circuit 21, the first end of the second branch 222 is coupled to the output end of the current mirror circuit 21, and the resistor circuit 223 is coupled to the second end of the first branch 221 and the second end of the second branch 222.

[0061] Specifically, the bias circuit 22 generates a bias current based on its own structure (no external bias is required). In this embodiment, the first branch 221 includes a first NMOS transistor MN1, the drain of which is coupled to the input terminal of the current mirror circuit 21, the source of which is coupled to the first terminal of the resistor circuit 223, and the gate of which is coupled to the middle terminal of the resistor circuit 223. The second branch 222 includes a second NMOS transistor MN2, the drain of which is coupled to the output terminal of the current mirror circuit 21, the source of which is coupled to the first terminal of the resistor circuit 223, and the gate of which is coupled to the gate of the first NMOS transistor MN1 (i.e., the middle terminal of the resistor circuit 223). The first end of the resistor circuit 223 is coupled to the source of the first NMOS transistor MN1 and the source of the second NMOS transistor MN2, the second end is coupled to the ground terminal, and the middle end is coupled to the gate of the first NMOS transistor MN1 and the second NMOS transistor MN2. In this example, the resistor circuit 223 is composed of a first resistor unit 22a and a second resistor unit 22b connected in series. The coupling end of the first resistor unit 22a and the second resistor unit 22b is the middle end of the resistor circuit 223. In this example, the first NMOS transistor MN1 and the second NMOS transistor MN2 are depletion-type MOS transistors with low threshold voltages or negative threshold voltages. Due to the presence of the first resistor unit 22a, the gate-source voltages of the first NMOS transistor MN1 and the second NMOS transistor MN2 are negative. Therefore, in the initial power-on stage, even if the gate voltages (i.e., the voltage at point B) of the first NMOS transistor MN1 and the second NMOS transistor MN2 are 0V, a current can be generated in the first NMOS transistor MN1, the first resistor unit 22a, and the second resistor unit 22b without the need for a startup circuit. Furthermore, since the first NMOS transistor MN1 and the second NMOS transistor MN2 are depletion-type MOS transistors, the consumption of quiescent current can be reduced while decreasing the self-biasing resistance (the equivalent resistance of all components used to achieve self-biasing and establish appropriate bias conditions).

[0062] The first resistor unit 22a and the second resistor unit 22b can be implemented using any form of circuit structure, as long as they can achieve the function of resistors, which will not be elaborated here.

[0063] like Figure 2 As shown, the driving circuit 23 has an input terminal and an output terminal. Its input terminal is coupled to the output terminal of the current mirror circuit 21, and its output terminal provides a power-on reset signal POR_OUT.

[0064] Specifically, the drive circuit 23 includes, but is not limited to, a buffer circuit (including at least two cascaded inverters) and a single inverter, which will not be described in detail here.

[0065] Example 2

[0066] This embodiment provides a power-on reset circuit 2, which differs from the first embodiment in that the first resistor unit 22a between the first end and the middle end of the resistor circuit 223 is implemented by a resistor, and the second resistor unit 22b between the middle end and the second end of the resistor circuit 223 is implemented by an adjustable resistor.

[0067] Specifically, such as Figure 3 As shown, the first resistor unit 22a includes a first resistor R1, the first end of the first resistor R1 is coupled to the first end of the resistor circuit 223, and the second end is coupled to the middle end of the resistor circuit 223.

[0068] Specifically, such as Figure 3 As shown, the second resistor unit 22b includes an adjustable resistor RV. The first end of the adjustable resistor RV is coupled to the middle end of the resistor circuit 223, and the second end is coupled to the second end of the resistor circuit 223. The adjustable resistor RV adjusts its resistance value based on the voltage Va at the output of the current mirror circuit 21.

[0069] In this invention, hysteresis is achieved by adjusting the threshold voltage that triggers the power-on reset signal POR_OUT. Specifically, the first threshold voltage Vpor during the rising phase of the power supply voltage VDD is greater than the second threshold voltage Vbor during the falling phase of the power supply voltage VDD. Thus, the circuit obtains a hysteresis voltage that satisfies Vpor - Vbor, thereby improving anti-interference capability through hysteresis. In this embodiment, the adjustable resistor RV adjusts the threshold voltage by changing the self-biasing resistance (in this example, the equivalent resistance of the biasing circuit 22) based on the voltage Va at the output of the current mirror circuit 21. Specifically, the self-biasing resistance value is set to a first resistance value during the rising phase of the power supply voltage VDD, and to a second resistance value during the falling phase of the power supply voltage VDD, with the first resistance value being greater than the second resistance value.

[0070] The other structures are the same as in Embodiment 1, and will not be described in detail here.

[0071] Example 3

[0072] This embodiment provides a power-on reset circuit 2, which differs from embodiments one and two in that the second resistor unit 22b between the middle end and the second end of the resistor circuit 223 is implemented by two resistors connected in series; the power-on reset circuit 2 also includes a resistor adjustment circuit 24.

[0073] Specifically, such as Figure 4 As shown, the second resistor unit 22b includes a second resistor R2 and a third resistor R3 connected in series; the first end of the second resistor R2 is coupled to the middle end of the resistor circuit 223, and the second end is coupled to the first end of the third resistor R3; the second end of the third resistor R3 is coupled to the second end of the resistor circuit 223.

[0074] Specifically, such as Figure 4 As shown, the resistor adjustment circuit 24 includes a control switch and a fourth resistor R4. The first end of the control switch is coupled to the coupling point of the second resistor R2 and the third resistor R3, and the control terminal is coupled to the output terminal (point A) of the current mirror circuit 21. The second end is coupled to the first end of the fourth resistor R4. As an example, the control switch is implemented using a fourth NMOS transistor MN4, with the drain of MN4 serving as the first end of the control switch, the gate as the control terminal, and the source as the second end. In practical applications, any device capable of switching under the control of the output voltage Va of the current mirror circuit 21 is applicable to this invention and is not limited to this embodiment. The first end of the fourth resistor R4 is coupled to the second end of the control switch, and the second end is coupled to ground.

[0075] In this embodiment, the resistor adjustment circuit 24 adjusts the threshold voltage of the trigger power-on reset signal POR_OUT based on the voltage Va at the output of the current mirror circuit 21 to obtain a hysteresis window, thereby improving the anti-interference capability through hysteresis. Its principle is the same as in Embodiment 2. Figure 4 As shown, in this example, during the rising phase of the power supply voltage VDD, the self-biasing resistance value is determined by the first NMOS transistor MN1, the second NMOS transistor MN2, the first resistor R1, the second resistor R2, and the third resistor R3 connected in series; during the falling phase of the power supply voltage VDD, the self-biasing resistance value is determined by the first NMOS transistor MN1, the second NMOS transistor MN2, the first resistor R1, the second resistor R2, the third resistor R3 connected in series, and the fourth resistor R4 connected in parallel across the third resistor R3.

[0076] The other structures are the same as in Embodiments 1 and 2, and will not be described in detail here.

[0077] Example 4

[0078] This embodiment provides a power-on reset circuit 2, which differs from embodiments one to three in that the power-on reset circuit 2 also includes a variable resistor circuit 25.

[0079] like Figure 5 As shown, as an example, the variable resistor circuit 25 includes a bypass switch and a fifth resistor R5.

[0080] Specifically, the first terminal of the bypass switch is coupled to the input terminal of the current mirror circuit 21, and the second terminal is coupled to the first terminal of the first branch 221 of the bias circuit 22. The control terminal receives the power-on reset signal POR_OUT. As an example, the bypass switch is implemented using a third PMOS transistor MP3. The source of the third PMOS transistor MP3 serves as the first terminal of the bypass switch, the drain serves as the second terminal of the bypass switch, and the gate serves as the control terminal of the bypass switch. In actual use, any device that can be controlled by the power-on reset signal POR_OUT to realize the switching function is applicable to this invention and is not limited to this embodiment.

[0081] Specifically, the fifth resistor R5 is connected in parallel with the bypass switch. When the bypass switch is on, the fifth resistor R5 is short-circuited; when the bypass switch is off, the fifth resistor R5 is connected between the input terminal of the current mirror circuit 21 and the first terminal of the first branch 221 of the bias circuit 22. As an example, the fifth resistor R5 is implemented using the third NMOS transistor MN3, such as... Figure 9 As shown; the drain of the third NMOS transistor MN3 is coupled to the input terminal of the current mirror circuit 21, the source is coupled to the first terminal of the first branch 221 of the bias circuit 22, and the gate receives the power supply voltage VDD; in one embodiment, the third NMOS transistor MN3 is set as an inverting ratio transistor, that is, the width-to-length ratio W / L<1, so as to obtain a larger on-resistance.

[0082] like Figure 5 As shown, in this example, the variable resistor circuit 25 controls the bypass switch based on the power-on reset signal POR_OUT to connect the fifth resistor R5 to the circuit during the power-on phase of the power supply voltage VDD (the self-biasing resistance value is determined by the fifth resistor R5 and the equivalent resistance of the bias circuit 22), and short-circuit the fifth resistor R5 during the power-off phase of the power supply voltage VDD (the self-biasing resistance value is determined by the equivalent resistance of the bias circuit 22), thereby generating a hysteresis window. Its principle is similar to that of Embodiment 2, and will not be described in detail here.

[0083] Furthermore, the variable resistor circuit 25 can operate simultaneously with other methods of adjusting the threshold voltage to generate a larger hysteresis window. For example... Figure 6 As shown, as an example, the variable resistor circuit 25 is used in conjunction with the second resistor R2, the third resistor R3 and the resistance adjustment circuit 24 of Embodiment 3.

[0084] The other structures are the same as those in Examples 1 to 3, and will not be described in detail here.

[0085] Example 5

[0086] This embodiment provides a power-on reset circuit 2, which differs from embodiments one through four in that the power-on reset circuit 2 further includes a pull-up circuit 26.

[0087] like Figure 7As shown, the pull-up circuit 26 is coupled between the power supply voltage VDD and the output terminal of the current mirror circuit 21, and is turned on or off based on the power-on reset signal POR_OUT. When the pull-up circuit 26 is turned on, the output terminal of the current mirror circuit 21 is pulled up to the power supply voltage VDD.

[0088] Specifically, as an example, the pull-up circuit 26 includes a pull-up transistor and a second inverter not2. In this example, the pull-up transistor is implemented using a fifth NMOS transistor MN5. The source of the fifth NMOS transistor MN5 is coupled to the output of the current mirror circuit 21, and the drain is coupled to the power supply voltage VDD. The input of the second inverter not2 receives the power-on reset signal POR_OUT, and its output is coupled to the gate of the fifth NMOS transistor MN5 (i.e., the control terminal of the pull-up transistor).

[0089] Specifically, in this embodiment, the driving circuit 23 is implemented using a first inverter not1; the input of the first inverter not1 is coupled to the output of the current mirror circuit 21, and the output outputs a power-on reset signal POR_OUT. The voltage at the output of the current mirror circuit 21 (i.e., the voltage at point A) rises or falls with the change of the power supply voltage VDD. The first inverter not1 performs inverse logic based on this voltage to obtain a power-on reset signal POR_OUT with a corresponding logic high or low level.

[0090] In this embodiment, the fifth NMOS transistor MN5, together with the first inverter not1 and the second inverter not2, forms a positive feedback loop. This loop accelerates the rise of the voltage at point A as it increases from low to high, preventing the voltage at point A from remaining at a low level and causing the first inverter not1 to remain constantly on, thus increasing the dynamic current of the circuit. Any circuit structure that can accelerate the rise of the voltage at point A during its rise phase is applicable to the pull-up circuit 26 of this invention, and is not limited to this embodiment.

[0091] The other structures are the same as those in Examples 1 to 4, and will not be described in detail here.

[0092] Example 6

[0093] This embodiment provides a power-on reset circuit 2, which differs from embodiments one through five in that the power-on reset circuit 2 further includes a first enable circuit 27 and / or a second enable circuit 28.

[0094] like Figure 8As shown, in one implementation of the present invention, the power-on reset circuit 2 further includes a first enable circuit 27. The first enable circuit 27 is connected in series in the path between the second terminal of the first branch 221 and the ground terminal, and is controlled by the enable signal EN. When the enable signal EN is valid, the first enable circuit 27 is turned on, making the path between the second terminal of the first branch 221 and the ground terminal open; when the enable signal EN is invalid, the first enable circuit 27 is turned off, making the path between the second terminal of the first branch 221 and the ground terminal closed. As an example, the first enable circuit 27 is implemented using a sixth NMOS transistor MN6 (as a switch); the drain of the sixth NMOS transistor MN6 is coupled to the source of the first NMOS transistor MN1, the source is coupled to the first terminal of the first resistor unit 22a, and the gate receives the enable signal EN; the enable signal EN is valid at a high level and invalid at a low level. In practical use, the first enabling circuit 27 can be set at any node on the path between the second end of the first branch 221 and the ground end. It is applicable to any position that can control the opening and closing of the path between the second end of the first branch 221 and the ground end, and the structure is not limited. It will not be described in detail here.

[0095] like Figure 8 As shown, in another implementation of the present invention, the power-on reset circuit 2 further includes a second enable circuit 28. The second enable circuit 28 is coupled between the power supply voltage VDD and the input terminal of the drive circuit 23, and is controlled by the enable signal EN. When the enable signal EN is valid, the second enable circuit 28 is turned off, and the power supply voltage VDD has no effect on the voltage at point A. When the enable signal EN is invalid, the second enable circuit 28 is turned on, and the voltage at point A is pulled up to a high voltage. As an example, the second enable circuit 28 is implemented based on a fourth PMOS transistor MP4 (as a switch). The source of the fourth PMOS transistor MP4 is coupled to the power supply voltage VDD, the drain is coupled to the input terminal of the drive circuit 23, and the gate receives the enable signal EN. In practical use, any circuit structure that can realize the function of the second enable circuit 28 is applicable to the present invention and is not limited to this embodiment.

[0096] The other structures are the same as those in Examples 1 to 5, and will not be described in detail here.

[0097] Example 7

[0098] like Figure 9 As shown, this embodiment provides a power-on reset circuit 2, which includes a current mirror circuit 21, a bias circuit 22, a drive circuit 23, a resistor adjustment circuit 24, a variable resistor circuit 25, a pull-up circuit 26, a first enable circuit 27, and a second enable circuit 28. The circuit structures are described in Embodiments 1 to 6, and will not be repeated here.

[0099] based on Figure 9The working principle of the power-on reset circuit 2 of the present invention is explained as follows:

[0100] When the enable signal EN is invalid (low level), the power-on reset circuit 2 does not operate. At this time, the sixth NMOS transistor MN6 is off, and the current mirror circuit 21 and bias circuit 22 are not working; the fourth PMOS transistor MP4 is on, and the voltage at point A is pulled up to the power supply voltage VDD, limiting the power-on reset signal POR_OUT to a low level; therefore, the entire circuit consumes almost no current. When the enable signal EN is valid (high level), the power-on reset circuit 2 operates normally. At this time, the sixth NMOS transistor MN6 is on, and the current mirror circuit 21 and bias circuit 22 operate normally; the fourth PMOS transistor MP4 is off, and the voltage at point A is determined by the current mirror circuit 21 and bias circuit 22 under the influence of the power supply voltage VDD.

[0101] During normal operation, current flows through the first resistor unit 22a and the second resistor unit 22b, generating a voltage drop at point B. This provides gate bias voltage for the first NMOS transistor MN1 and the second NMOS transistor MN2. Since the first NMOS transistor MN1 and the second NMOS transistor MN2 are dissipative transistors, self-biasing can be achieved even when the power supply voltage VDD is very small (in the initial stage of power-on), thereby generating current to complete the startup. Simultaneously, the current flowing through the first PMOS transistor MP1 is amplified n times and output from the drain of the second PMOS transistor MP2.

[0102] like Figure 9 and Figure 10As shown, before the power supply voltage VDD starts to increase from 0V to the first threshold voltage Vpor, the current flowing through the second PMOS transistor MP2 is less than the current flowing through the second NMOS transistor MN2 (i1 < i2). At this time, the voltage at point A is a low voltage, and the power-on reset signal POR_OUT is a high level. After the power supply voltage VDD increases to be greater than the first threshold voltage Vpor, the current flowing through the second PMOS transistor MP2 is greater than the current flowing through the second NMOS transistor MN2 (i1 > i2). At this time, the voltage at point A is a high voltage, and the power-on reset signal POR_OUT is a low level. Before the power supply voltage VDD starts to decrease from a high voltage (greater than the first threshold Vpor) to the second threshold voltage Vbor, the current flowing through the second PMOS transistor MP2 is greater than the current flowing through the second NMOS transistor MN2 (i1 > i2). At this time, the voltage at point A is a high voltage, and the power-on reset signal POR_OUT is a low level. After the power supply voltage VDD is less than the second threshold Vbor, the current flowing through the second PMOS transistor MP2 is less than the current flowing through the second NMOS transistor MN2 (i1 < i2). At this time, the voltage at point A is a low voltage, and the power-on reset signal POR_OUT is a high level. Among them, the first threshold Vpor is the voltage at node A when i1 = i2 in the case where the power supply voltage VDD starts to increase from 0V; the second threshold Vbor is the voltage at node A when i1 = i2 in the case where the power supply voltage VDD starts to decrease from a high voltage; the magnitudes of the first threshold Vpor and the second threshold Vbor are determined by device parameters.

[0103] As an example, when the threshold voltage of the present invention is not adjusted (Example 1), the first threshold Vpor is equal to the second threshold Vbor.

[0104] As another example, as Figure 9 and Figure 10As shown, when the threshold voltage is adjusted according to the present invention (Examples 2 to 9), the first threshold Vpor is not equal to the second threshold Vbor. Specifically, before the power supply voltage VDD increases from 0V to the level of the power-on reset signal POR_OUT, the power-on reset signal POR_OUT is at a high level, the third PMOS transistor MP3 is turned off, and the third NMOS transistor MN3 is connected between the first PMOS transistor MP1 and the first NMOS transistor MN1; at the same time, since the power-on reset signal POR_OUT is at a high level, the voltage at point A is low, therefore, the fourth NMOS transistor MN4 is turned off, and the fourth resistor R4 is not connected to the circuit. Before the power supply voltage VDD decreases from high to the level of the power-on reset signal POR_OUT (which is currently low), the third PMOS transistor MP3 is turned on, and the third NMOS transistor MN3 is short-circuited by MP3 and does not operate. Simultaneously, because POR_OUT is low, the voltage at point A is high, the fourth NMOS transistor MN4 is turned on, and the fourth resistor R4 is connected in parallel with the third resistor R3, further reducing the self-biasing resistance. Therefore, the current flowing through the first PMOS transistor MP1 when the power supply voltage VDD rises is less than the current flowing through it when VDD falls. That is, the power supply voltage VDD needs to reach a higher voltage during its rise than during its fall to make i1 = i2. Therefore, Vpor > Vbor, and this circuit has a hysteresis voltage Vpor - Vbor.

[0105] The present invention also provides a chip including the power-on reset circuit 2 of the present invention. The present invention also provides an electronic product including the power-on reset circuit 2 of the present invention. The power-on reset circuit 2 of the present invention can effectively reduce the area overhead of the chip and the electronic product, reduce the power consumption of the chip and the electronic product, and improve the anti-interference capability during the power-on detection process.

[0106] In summary, this invention provides a power-on reset circuit, a chip, and an electronic product, comprising: a current mirror circuit having an input terminal and an output terminal; a bias circuit including a first branch, a second branch, and a resistor circuit, wherein a first terminal of the first branch is coupled to the input terminal of the current mirror circuit, a first terminal of the second branch is coupled to the output terminal of the current mirror circuit, and the resistor circuit is coupled to the second terminal of the first branch and the second terminal of the second branch; and a driving circuit having an input terminal coupled to the output terminal of the current mirror circuit and an output terminal providing a power-on reset signal. The power-on reset circuit, chip, and electronic product of this invention have a simple structure, strong anti-interference capability, low power consumption, and small layout area. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0107] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A power-on reset circuit, comprising: A current mirror circuit has an input terminal and an output terminal; The bias circuit includes a first branch, a second branch, and a resistor circuit. The first end of the first branch is coupled to the input terminal of the current mirror circuit, the first end of the second branch is coupled to the output terminal of the current mirror circuit, and the resistor circuit is coupled to the second end of the first branch and the second end of the second branch. as well as The driving circuit has an input terminal coupled to the output terminal of the current mirror circuit and an output terminal that provides a power-on reset signal.

2. The power-on reset circuit as described in claim 1, wherein, The bias circuit includes: The first branch includes a first NMOS transistor, having a drain coupled to the input terminal of the current mirror circuit and a source coupled to the first terminal of the resistor circuit; The second branch includes a second NMOS transistor, having its drain coupled to the output terminal of the current mirror circuit and its source coupled to the first terminal of the resistor circuit; and The resistor circuit has a first end coupled to the second end of the first branch and the second end of the second branch, a second end coupled to the ground end, and an intermediate end coupled to the gate of the first NMOS transistor and the second NMOS transistor. The first NMOS transistor and the second NMOS transistor include depletion-type NMOS transistors.

3. The power-on reset circuit as described in claim 2, wherein, The resistor circuit includes a first resistor between its first terminal and its middle terminal.

4. The power-on reset circuit as described in claim 3, wherein, An adjustable resistor is included between the middle and second terminals of the resistor circuit, and the resistance value of the adjustable resistor is adjusted based on the voltage at the output terminal of the current mirror circuit.

5. The power-on reset circuit as described in claim 3, wherein, The resistor circuit includes a second resistor and a third resistor connected in series between the middle terminal and the second terminal. The power-on reset circuit further includes a resistor adjustment circuit, which includes: A control switch having a first terminal coupled to a second resistor and a third resistor, and a control terminal coupled to the output terminal of the current mirror circuit; and The fourth resistor has a first end coupled to the second end of the control switch and a second end coupled to the ground.

6. The power-on reset circuit as described in claim 2 or 5, further comprising a variable resistor circuit, the variable resistor circuit comprising: A bypass switch has a first terminal coupled to the input terminal of the current mirror circuit, a second terminal coupled to the first terminal of the first branch of the bias circuit, and a control terminal for receiving the power-on reset signal. The fifth resistor is connected in parallel with the bypass switch.

7. The power-on reset circuit as described in claim 6, wherein, The fifth resistor includes a third NMOS transistor, the drain of which is coupled to the input terminal of the current mirror circuit, the source of which is coupled to the first terminal of the first branch of the bias circuit, and the gate of which receives the power supply voltage.

8. The power-on reset circuit as claimed in claim 1, further comprising a pull-up circuit, the pull-up circuit being coupled between the power supply voltage and the output terminal of the current mirror circuit, and being turned on or off based on the power-on reset signal, wherein when the pull-up circuit is turned on, the output terminal of the current mirror circuit is pulled up to the power supply voltage.

9. The power-on reset circuit as described in claim 1, wherein the power-on reset circuit further comprises a first enable circuit, the first enable circuit being connected in series in the path between the second terminal of the first branch and the ground terminal, and is controlled by an enable signal.

10. The power-on reset circuit as claimed in claim 1, further comprising a second enable circuit, the second enable circuit being coupled between the power supply voltage and the input terminal of the drive circuit, and controlled by an enable signal.

11. The power-on reset circuit as described in claim 1, wherein, The current mirror circuit includes a first PMOS transistor and a second PMOS transistor; the sources of the first PMOS transistor and the second PMOS transistor are coupled to a power supply voltage, and the gates are coupled to the drain of the first PMOS transistor; the drain of the first PMOS transistor serves as the input terminal of the current mirror structure, and the drain of the second PMOS transistor serves as the output terminal of the current mirror structure.

12. The power-on reset circuit as described in claim 1, wherein, The driving circuit includes an inverter.

13. A chip, comprising: The power-on reset circuit as described in any one of claims 1-12.

14. An electronic product comprising: The power-on reset circuit as described in any one of claims 1-12.

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