A low standby power MCU and its method

Abstract

This invention provides a low-power standby MCU and its method. The MCU includes a power-on reset circuit (POR), a first voltage regulator, a bandgap reference module (Bandgap), a second voltage regulator, an undervoltage reset circuit (BOR), a CPU, and an OR gate (OR). The CPU's output is connected to the enable input of the undervoltage reset circuit (BOR), the second voltage regulator, and the bandgap reference module. The CPU's output is connected to the input of the first voltage regulator. The outputs of the power-on reset circuit (POR) and the undervoltage reset circuit (BOR) are connected to the input of the OR gate (OR). The output of the OR gate (OR) is connected to the CPU's input. The output of the bandgap reference module (Bandgap) is connected to the input of the undervoltage reset circuit (BOR) and the second voltage regulator. The outputs of the second voltage regulator and the first voltage regulator are connected to the CPU's power input. The MCU and method proposed in this invention can reduce MCU power consumption by shutting down some analog circuits during standby.

Description

Technical Field

[0001] This invention relates to the field of microcontroller technology, and in particular to a low standby power MCU and its method. Background Technology

[0002] A microcontroller unit (MCU), also known as a single-chip microcomputer or microcontroller, is a chip-level computer that integrates a central processing unit (CPU) with a reduced frequency and specifications, along with peripheral interfaces such as memory, counters, USB, A / D converters, UART, PLC, DMA, and even LCD driver circuitry, all onto a single chip. This allows for different combinations of control for various applications. MCUs are found in everything from mobile phones and PC peripherals to remote controls, automotive electronics, and industrial applications such as stepper motor and robotic arm control.

[0003] The power consumption of an MCU mainly consists of two parts: static power consumption and operational power consumption. The total power consumption of the MCU during operation is the sum of the power consumption of analog peripherals and the dynamic power consumption of digital peripherals. The power consumption of analog circuits is usually determined by the operating voltage and its performance requirements, while the dynamic power consumption of digital circuits mainly comes from the switching frequency, voltage, and equivalent load capacitance. The static power consumption of an MCU is defined as the leakage current of the digital circuit when the system clock source is turned off. However, in the design of mixed-signal low-power MCUs, the following multiple leakage current sources must be considered simultaneously: leakage current of digital circuits, SRAM leakage current, leakage current of emulation circuits that are turned off in standby mode (e.g., ADC, embedded flash memory), operating current of emulation circuits that are not turned off in standby mode (e.g., LDO, BOD), and leakage current of I / O pins.

[0004] Existing technologies also include methods to reduce MCU power consumption by lowering static power consumption and operating power consumption, but there is no method to reduce MCU power consumption by shutting down part of the analog circuit operating current during standby without affecting MCU performance. Summary of the Invention

[0005] This invention proposes a low-power MCU and its method that can reduce MCU power consumption by shutting down part of the analog circuit operating current during standby without affecting MCU performance.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] In a first aspect, the present invention provides a low standby power consumption MCU, comprising a power-on reset circuit (POR), a first voltage regulator, a bandgap reference module (Bandgap), a second voltage regulator, an undervoltage reset circuit (BOR), a CPU, and an OR gate (OR); the output terminal of the CPU is connected to the enable input terminal of the undervoltage reset circuit (BOR), the second voltage regulator, and the bandgap reference module; the output terminal of the CPU is connected to the input terminal of the first voltage regulator; the output terminals of the power-on reset circuit (POR) and the undervoltage reset circuit (BOR) are connected to the input terminal of the OR gate; the output terminal of the OR gate is connected to the input terminal of the CPU; the output terminal of the bandgap reference module (Bandgap) is connected to the input terminal of the undervoltage reset circuit (BOR) and the second voltage regulator; the output terminal of the second voltage regulator and the output terminal of the first voltage regulator are connected to the power input terminal of the CPU.

[0008] Preferably, the first voltage regulator includes an input terminal, an output terminal, an output transistor, a bias circuit, a trim circuit, a reference voltage circuit, and a ground terminal. The drain of the output transistor is connected to the input terminal, the gate of the output transistor is connected to the reference voltage circuit, the source of the output transistor is connected to the output terminal, the bias circuit is connected between the input terminal and the reference voltage circuit, and the reference voltage circuit is connected to the trim circuit, the bias circuit, the ground terminal, and the gate of the output transistor.

[0009] Preferably, the reference voltage circuit includes one MOSFET.

[0010] Preferably, the second voltage regulator includes an LDO.

[0011] Preferably, it also includes memory and I / O.

[0012] A second aspect of the present invention provides a method for a low standby power MCU, comprising the following steps:

[0013] 1) When the chip power supply is turned on, before the chip power supply drops below the POR reset release point of the power-on reset circuit, the POR is reset, and the chip is in the reset state.

[0014] 2) After the chip power supply is turned on to a value greater than the POR reset release point of the power-on reset circuit, the POR reset of the power-on reset circuit is released, and the first regulator outputs a pre-regulated voltage for use by the CPU and digital logic.

[0015] 3) After the chip power supply is raised above the BOR reset release point of the undervoltage reset circuit, the BOR reset circuit is released, and the Bandgap reference module and LDO regulator can work normally. At this time, the chip is in normal mode.

[0016] 4) The chip shuts down the bandgap reference module, LDO regulator, and undervoltage reset circuit BOR. At this time, the power supply for the CPU and digital logic circuits is provided by the first regulator, and the chip enters low-power mode.

[0017] Preferably, step 3) further includes the CPU reading the calibration code of the first voltage regulator and performing output calibration on the first voltage regulator.

[0018] Compared with the prior art, the beneficial effects of the present invention are: the low standby power consumption MCU provided by the present invention shuts down the bandgap reference module, LDO regulator and undervoltage reset circuit BOR in standby state, and uses the low power consumption first regulator provided by the present invention to maintain the normal standby state of the chip, thereby realizing the low power consumption of the MCU in standby state. Attached Figure Description

[0019] Figure 1 This is a framework diagram of a low standby power MCU proposed in this invention;

[0020] Figure 2 This is a frame diagram of a first voltage regulator proposed in this invention;

[0021] Figure 3 This is a framework diagram of a method for a low standby power consumption MCU proposed in this invention;

[0022] Figure 4 This is a simulation diagram of an existing MCU.

[0023] Figure 5 This is a simulation diagram of a low standby power MCU proposed in this invention.

[0024] The following are the labels in the diagram: 1. CPU, 2. Power-on reset circuit (POR), 3. Undervoltage reset circuit (BOR), 4. Bandgap reference module, 5. LDO regulator, 6. First regulator, 7. I / O pin, 8. OR gate, 6.1. Input terminal, 6.2. Output terminal, 6.3. Output transistor, 6.4. Current source, 6.5. Trim circuit, 6.6. Reference voltage circuit, 6.7. Ground terminal. Detailed Implementation

[0025] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0026] In the description of this invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0027] like Figure 1 The diagram illustrates a low-power standby MCU, comprising a CPU 1, a power-on reset circuit POR 2, an undervoltage reset circuit BOR 3, a bandgap reference module Bandgap 4, an LDO regulator 5, a first regulator 6, an I / O pin 7, and an OR gate OR 8. The output of CPU 1 is connected to the enable input of the undervoltage reset circuit BOR 3, the LDO regulator 5, and the bandgap reference module Bandgap 4. The output of CPU 1 is connected to the input of the first regulator 6. The outputs of the power-on reset circuit POR 2 and the undervoltage reset circuit BOR 3 are connected to the input of the OR gate OR 8, and the output of the OR gate OR 8 is connected to the input of CPU 1. The output of the bandgap reference module Bandgap 4 is connected to the input of the undervoltage reset circuit BOR 3 and the LDO regulator 5. The outputs of the LDO regulator 5 and the first regulator 6 are connected to the power input of CPU 1.

[0028] like Figure 2 As shown, a first voltage regulator includes an input terminal 6.1, an output terminal 6.2, an output transistor 6.3, a current source 6.4, a trim circuit 6.5, a reference voltage circuit 6.6, and a ground terminal 6.7. The drain of the output transistor 6.3 is connected to the input terminal 6.1, the gate of the output transistor 6.3 is connected to the reference voltage circuit 6.6, and the source of the output transistor 6.3 is connected to the output terminal 6.2. The current source 6.4 has one end connected to the input terminal 6.1 and the other end connected to the gate and drain of the NMOS transistor in the reference voltage circuit 6.6 that generates the reference voltage. The trim circuit 6.5 is connected to the reference voltage circuit 6.6. The reference voltage circuit 6.6 is connected to the trim circuit 6.5, the current source 6.4, the ground terminal 6.7, and the gate of the output transistor 6.3.

[0029] The reference voltage circuit generates a reference voltage VGS between the drain and source of an NMOS transistor connected to a diode by allowing current to flow through the drain to the source. For an NMOS transistor in the strong inversion region, the reference voltage of the diode-connected NMOS transistor is:

[0030]

[0031] Where V thWhere is the threshold voltage of the NMOS transistor, I is the current flowing through the drain of the NMOS transistor, μ is the electron mobility, and C is the threshold voltage of the NMOS transistor. ox The capacitance per unit area of ​​the gate oxide layer. This represents the width-to-length ratio of the NMOS transistor.

[0032] After the Trim circuit 6.5 adjusts the W / L of the NMOS transistor in the reference voltage circuit 6.6, the reference voltage circuit 6.6 can output an accurate reference voltage.

[0033] In this embodiment, the reference voltage circuit 6.6 includes one MOSFET, the current source 6.4 has very low power consumption, approximately 100nA, and the trim circuit 6.5 requires no power consumption; therefore, the power consumption of the first regulator is extremely low, which can maintain normal standby power supply in the standby state of the MCU and save power consumption.

[0034] The low-power method of the present invention for a low-standby-power MCU, such as... Figure 3 As shown, the main steps include:

[0035] 1) The chip is powered on;

[0036] 2) Before the chip power supply drops below the POR reset release point, the POR is reset, and the chip is in a reset state.

[0037] 3) After the chip power supply is increased to a value greater than the POR reset release point, the POR reset is released, and the first regulator outputs a pre-regulated voltage for use by the CPU and other digital logic.

[0038] 4) The chip power supply continues to be powered on, and the chip remains in the reset state until the BOR reset release point is reached;

[0039] 5) After the chip power supply is raised above the BOR reset release point, the BOR reset is released, and both the BG circuit and the LDO circuit can work normally. The CPU reads the calibration code of the first regulator and performs output calibration on the first regulator. At this time, the chip is in normal mode.

[0040] 6) Determine if the chip has entered low-power mode. If yes, proceed to step 7); otherwise, keep step 5.

[0041] 7) The chip shuts down the BG circuit, LDO circuit and BOR circuit. At this time, the power supply for digital logic circuits such as the CPU is provided by VPRE, and the chip enters low power mode.

[0042] 8) Determine whether the chip has entered normal power consumption mode. If yes, proceed to step 9); otherwise, keep step 7.

[0043] 9) Enable the BG circuit, LDO circuit and BOR circuit of the chip. At this time, the power supply of digital logic circuits such as CPU is provided by the first regulator and LDO, and the chip enters the normal working mode.

[0044] Example 1

[0045] Simulation experiments were conducted using the low standby power MCU provided by this invention and conventional MCUs in the prior art, with an output voltage of 1.5V as an example.

[0046] like Figure 4 As shown, in conventional MCUs of the prior art, the standby time slot reference module Bandgap, LDO regulator, and undervoltage reset circuit BOR are not turned off, and the typical standby power consumption is 70uA.

[0047] like Figure 5 As shown, the MCU with low standby power consumption provided by the present invention has a typical standby power consumption of approximately 0.84uA.

[0048] It is evident that using the MCU provided by this invention can significantly reduce standby power consumption.

[0049] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. An MCU with low standby power consumption, characterized in that, The power-on reset circuit POR, the first voltage stabilizer, the bandgap reference module Bandgap, the second voltage stabilizer, the brown-out reset circuit BOR, the CPU and the OR gate; the output of the CPU is connected to the enable input of the brown-out reset circuit BOR, the second voltage stabilizer and the bandgap reference module Bandgap, the output of the CPU is connected to the input of the first voltage stabilizer, the outputs of the power-on reset circuit POR and the brown-out reset circuit BOR are connected to the inputs of the OR gate, the output of the OR gate is connected to the input of the CPU, the output of the bandgap reference module Bandgap is connected to the inputs of the brown-out reset circuit BOR and the second voltage stabilizer, the output of the second voltage stabilizer and the output of the first voltage stabilizer are connected to the power input of the CPU; the first voltage stabilizer comprises an input terminal, an output terminal, an output transistor, a bias circuit, a trim circuit, a reference voltage circuit and a ground terminal, the drain of the output transistor is connected to the input terminal, the gate of the output transistor is connected to the reference voltage circuit, the source of the output transistor is connected to the output terminal, the bias circuit is connected between the input terminal and the reference voltage circuit, the reference voltage circuit is connected to the trim circuit, the bias circuit, the ground terminal and the gate of the output transistor. The reference voltage circuit comprises one MOS transistor; the second voltage stabilizer comprises an LDO.

2. The MCU with low standby power consumption according to claim 1, characterized in that, The memory and the I / O are further included.

3. The method of claim 1 or 2, wherein, The method comprises the following steps: 1) when the chip power is powered on, the power-on reset circuit POR is reset before the chip power is powered on to below the power-on reset release point, and the chip is in a reset state; 2) after the chip power is powered on to above the power-on reset release point, the power-on reset circuit POR is released, and the first voltage stabilizer outputs a pre-stabilized voltage to the CPU and the digital logic for use; 3) after the chip power is powered on to above the brown-out reset release point, the brown-out reset circuit BOR is released, the bandgap reference module Bandgap and the LDO voltage stabilizer can work normally, and the chip is in a normal mode; 4) the chip turns off the bandgap reference module Bandgap, the LDO voltage stabilizer and the brown-out reset circuit BOR, the power supply of the CPU and the digital logic circuit is provided by the first voltage stabilizer, and the chip enters a low-power consumption mode.

4. The method of claim 3, wherein, Step 3) further comprises that the CPU reads the calibration code of the first voltage stabilizer and calibrates the output of the first voltage stabilizer.

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