Power-on reset circuit and radio frequency chip
By combining the power-on reset unit and the buffer unit, and utilizing the charging and discharging characteristics of MOSFETs and capacitors, the problems of unstable reset and high power consumption in existing power-on reset circuits during continuous power-on and power-off cycles are solved, achieving a simple structure, zero static power consumption, and reliable reset signal output.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- LANSUS TECH INC
- Filing Date
- 2025-11-10
- Publication Date
- 2026-07-10
AI Technical Summary
Existing power-on reset circuits are prone to problems such as failure to reset properly during continuous power-on and power-off cycles and are easily affected by power-on time. They also have drawbacks such as complex structure or high power consumption.
The system employs a combination of a power-on reset unit and a buffer unit. It utilizes the charging and discharging characteristics of MOSFETs and capacitors to generate an initial reset logic signal and outputs a stable reset signal through the buffer unit, thereby avoiding normally open paths and achieving zero static power consumption.
It can reset normally under conditions of fluctuating power-on time or continuous power-on and power-off, and has no static power consumption, which improves the reliability of the reset circuit and simplifies the structure.
Smart Images
Figure CN121077445B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of communication technology, and in particular to a power-on reset circuit and a radio frequency chip. Background Technology
[0002] The Power-On Reset (POR) circuit, as a key module in an integrated circuit system, has the core function of providing a reliable reset signal to the system during the power-on process and in the initial stage of power-up stabilization. This ensures that all functional modules within the chip start operating from a preset initial state, preventing logic errors or functional failures caused by power-on timing disorder. Currently, two relatively common POR circuit implementation schemes have emerged in the industry, each with its own unique structure and operating principle.
[0003] The first type of POR circuit is an RC delay type power-on reset circuit, such as... Figure 1 As shown, Figure 1 This is a schematic diagram of a power-on reset circuit in related technologies. This type of circuit is the simplest implementation of a POR circuit, and its core design concept is based on the resistor-capacitor (RC) charging and discharging principle. The typical structure of this circuit consists of a resistor, a capacitor, and a subsequent inverter. The specific working process is as follows: When the power supply is turned on, the power supply voltage gradually rises from 0V. Due to the physical characteristic that the voltage across the capacitor cannot change abruptly, the initial voltage of the upper plate of the capacitor remains at a low level. At this time, the reset signal output is low, and the system enters the reset state. As the power supply continues to provide power, current charges the capacitor through the resistor, and the voltage of the upper plate of the capacitor gradually increases. When this voltage rises to the threshold voltage of the subsequent inverter, the inverter output state flips, the reset signal changes from low to high and remains stable, the reset process ends, and the system enters the normal operating state.
[0004] In this structure, the rise rate of the voltage on the upper plate of the capacitor is naturally delayed compared to the rise rate of the power supply voltage due to the charging process. By utilizing the sensitivity of the inverter in the subsequent stage to the threshold voltage, a low-level reset signal of a certain duration can be generated to meet the basic power-on reset requirements.
[0005] The second type of POR circuit is the voltage / current detection comparator type power-on reset circuit. This type of circuit monitors power supply voltage changes in real time through a dedicated voltage detection module (such as a bandgap reference source with a comparator) or a current detection module. When the power supply voltage reaches a preset stability threshold, the reset signal is switched by flipping the comparator output level. The generation and maintenance of its reset signal rely more on accurate voltage / current threshold judgment than on a simple RC delay effect. This type of circuit has significant advantages in terms of the stability and consistency of the reset signal, and can more accurately match the system's requirements for reset timing.
[0006] However, although both types of POR circuits can achieve the basic power-on reset function, they still have significant performance shortcomings and application limitations in practical applications, as follows:
[0007] Because of the RC delay effect, the amount of charge stored in the delay capacitor after it is de-energized will seriously affect the power-on delay of the next power-on. It is also greatly affected by the power-on speed, which can easily lead to problems such as the reset level being too narrow or unable to generate a reset level.
[0008] Voltage / current sensing comparator type power-on reset circuits have a more complex structure and higher power consumption. They often have a constant branch. To reduce power consumption, the impedance of this constant branch needs to be increased, which means a larger area is required.
[0009] Therefore, there is an urgent need for a new power-on reset circuit and RF chip to solve the above-mentioned technical problems. Summary of the Invention
[0010] This invention provides a power-on reset circuit and an RF chip, aiming to solve the problems of existing power-on reset circuit structures being prone to failure to reset properly during continuous power-on and power-off cycles and being easily affected by power-on time. It provides a power-on reset circuit with a simple structure, zero static power consumption, and high reliability.
[0011] In a first aspect, the present invention provides a power-on reset circuit, the power-on reset circuit including a power-on reset unit and a buffer unit;
[0012] The input terminal of the power-on reset unit is used to connect to the power supply voltage, and the output terminal of the power-on reset unit is connected to the input terminal of the buffer unit. The power-on reset unit is used to generate an initial reset logic signal and send it to the buffer unit during the power supply voltage power-on process.
[0013] The output terminal of the buffer unit is used to output a reset signal; the buffer unit is used to generate the reset signal according to the initial reset logic signal and output it.
[0014] Preferably, the power-on reset unit includes a first resistor, a first capacitor, a second capacitor, a first MOSFET, a second MOSFET, and a first inverter;
[0015] The source of the first MOSFET serves as the input terminal of the power-on reset unit. The gate of the first MOSFET is connected to the first terminal of the first resistor. The drain of the first MOSFET is connected to the first terminal of the first capacitor and the gate of the second MOSFET. The second terminal of the first resistor, the second terminal of the first capacitor, and the source of the second MOSFET are all grounded. The drain of the second MOSFET is connected to the input terminal of the first inverter. The output terminal of the first inverter serves as the output terminal of the power-on reset unit. The first terminal of the second capacitor is connected to the source of the first MOSFET, and the second terminal of the second capacitor is connected to the drain of the second MOSFET.
[0016] Preferably, the first MOS transistor is a PMOS transistor.
[0017] Preferably, the second MOS transistor is an NMOS transistor.
[0018] Preferably, the buffer unit is a Schmitt trigger or an even-stage inverter.
[0019] Preferably, the buffer unit includes a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a second inverter, a second resistor, and a third resistor;
[0020] The source of the third MOSFET is connected to the power supply voltage. The gates of the third MOSFET, the fourth MOSFET, the fifth MOSFET, and the sixth MOSFET are interconnected and serve as the input terminal of the buffer unit. The drain of the third MOSFET and the source of the fourth MOSFET are respectively connected to the source of the seventh MOSFET. The drains of the fourth MOSFET, the fifth MOSFET, the seventh MOSFET, and the eighth MOSFET are respectively connected to the input terminal of the second inverter. The source of the fifth MOSFET and the drain of the sixth MOSFET are respectively connected to the source of the eighth MOSFET. The source of the sixth MOSFET is grounded. The drain of the seventh MOSFET is connected to the first terminal of the second resistor, the second terminal of the second resistor is grounded, and the drain of the eighth MOSFET is connected to the first terminal of the third resistor. The second terminal of the third resistor is connected to the power supply voltage. The output terminal of the second inverter serves as the output terminal of the buffer unit.
[0021] Preferably, the third, fourth, and seventh MOS transistors are all PMOS transistors, and the fifth, sixth, and eighth MOS transistors are all NMOS transistors.
[0022] Secondly, the present invention also provides a radio frequency chip, the radio frequency chip including a power-on reset circuit as described in any of the above embodiments.
[0023] Compared with existing technologies, this invention utilizes a power-on reset unit and a buffer unit. The input terminal of the power-on reset unit is connected to the power supply voltage, and the output terminal of the power-on reset unit is connected to the input terminal of the buffer unit. The power-on reset unit generates an initial reset logic signal and sends it to the buffer unit during the power supply voltage power-on process. The output terminal of the buffer unit outputs a reset signal. The buffer unit generates a reset signal output based on the initial reset logic signal. Thus, the power-on reset circuit provided by this invention has a simple structure, no static power consumption after reset, and high reliability, enabling normal reset even under power supply fluctuations or continuous power-on / off cycles. Attached Figure Description
[0024] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and more readily understood through the detailed description following the accompanying drawings. In the drawings:
[0025] Figure 1 This is a circuit diagram of a power-on reset circuit in related technologies;
[0026] Figure 2 This is a circuit diagram of the power-on reset circuit provided in Embodiment 1 of the present invention;
[0027] Figure 3 This is a circuit diagram of the power-on reset circuit provided in Embodiment 2 of the present invention;
[0028] Figure 4 This is a simulation diagram of the power-on reset circuit provided in the embodiments of the present invention under continuous fast power-on, fast power-off and fast power-on conditions;
[0029] Figure 5 This is a simulation diagram of the power-on reset circuit provided in the embodiments of the present invention during continuous slow power-on, slow power-off, and slow power-on. Detailed Implementation
[0030] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.
[0031] Example 1
[0032] Please refer to Figure 2 The present invention provides a power-on reset circuit 100, which includes a power-on reset unit 1 and a buffer unit 2.
[0033] The input terminal of the power-on reset unit 1 is used to connect to the power supply voltage VDD, and the output terminal of the power-on reset unit 1 is connected to the input terminal of the buffer unit 2. The power-on reset unit 1 is used to generate an initial reset logic signal and send it to the buffer unit 2 during the power supply voltage power-on process.
[0034] The output terminal of the buffer unit 2 is used to output the reset signal RST_N; the buffer unit 2 is used to generate the reset signal RST_N according to the initial reset logic signal and output it.
[0035] In this embodiment of the invention, the power-on reset unit 1 includes a first resistor R1, a first capacitor C1, a second capacitor C2, a first MOSFET M1, a second MOSFET M2, and a first inverter INV1;
[0036] The source of the first MOSFET M1 serves as the input terminal of the power-on reset unit 1. The gate of the first MOSFET M1 is connected to the first terminal of the first resistor R1. The drain of the first MOSFET M1 is connected to the first terminal of the first capacitor C1 and the gate of the second MOSFET M2. The second terminal of the first resistor R1, the second terminal of the first capacitor C1, and the source of the second MOSFET M2 are all grounded. The drain of the second MOSFET M2 is connected to the input terminal of the first inverter INV1. The output terminal of the first inverter INV1 serves as the output terminal of the power-on reset unit 1. The first terminal of the second capacitor C2 is connected to the source of the first MOSFET M1, and the second terminal of the second capacitor C2 is connected to the drain of the second MOSFET M2.
[0037] In this embodiment of the invention, the first MOS transistor M1 is a PMOS transistor. Furthermore, the gate length of the first MOS transistor M1 can be increased according to actual needs, thereby improving the impedance, enhancing the delay effect of the power-on reset unit 1, and reversing the threshold.
[0038] In this embodiment of the invention, the second MOS transistor M2 is an NMOS transistor. Furthermore, the gate length of the second MOS transistor M2 can be increased according to actual needs, thereby improving the impedance, enhancing the delay effect of the power-on reset unit 1, and reversing the threshold.
[0039] In this embodiment of the invention, the buffer unit 2 is a Schmitt trigger or an even-stage inverter.
[0040] In this embodiment of the invention, the third MOS transistor M3, the fourth MOS transistor M4 and the seventh MOS transistor M7 are all PMOS transistors, and the fifth MOS transistor M5, the sixth MOS transistor M6 and the eighth MOS transistor M8 are all NMOS transistors.
[0041] Specifically, the working principle of the power-on reset circuit 100 provided by this invention is as follows:
[0042] As the power supply voltage VDD starts from 0, the first MOSFET M1 turns on first, and the first capacitor C1 begins to charge. Before the voltage of the upper plate of the first capacitor C1 rises to the threshold voltage of the second MOSFET M2, the potential of the lower plate of the second capacitor C2 is still high, and the output reset signal RST_N is low. When the voltage of the upper plate of the first capacitor C1 rises to the threshold voltage of the second MOSFET M2, the second MOSFET M2 turns on, pulling down the voltage of the lower plate of the second capacitor C2, and the output reset signal RST_N becomes high, completing the reset.
[0043] After the first reset, the power supply voltage VDD drops, and most of the charge stored in the first capacitor C1 is discharged by the first MOSFET M1 through the power supply voltage VDD. However, a small amount of charge remains, meaning that the upper plate of the first capacitor C1 still has a voltage of about several hundred millivolts, but this is lower than the threshold voltage of the second MOSFET M2. At this time, the second MOSFET M2 is weakly turned on, causing the reset signal RST_N to decrease along with the power supply voltage VDD. When the power supply voltage VDD is turned on for the second time, similarly, before the voltage of the upper plate of the first capacitor C1 rises to the threshold voltage of the second MOSFET M2, the voltage of the lower plate of the second capacitor C2 will rise along with the power supply voltage VDD under the coupling effect of the second capacitor C2, and the reset signal RST_N will decrease. When the voltage of the upper plate of the first capacitor C1 rises to the threshold voltage of the second MOSFET M2, the second MOSFET M2 turns on, pulling down the voltage of the lower plate of the second capacitor C2, and the reset signal RST_N rises again, completing the second reset. This achieves a stable output of the corresponding reset signal RST_N even when the power supply is continuously turned on and off, and as... Figure 2 and Figure 3 The power-on reset circuit 100 shown has no normally open path, so there is no static current after the reset is completed.
[0044] Example 2
[0045] Please refer to Figure 3 , Figure 3 This is a circuit diagram of the power-on reset circuit provided in Embodiment 2 of the present invention. Figure 3 The power-on reset circuit 200 in this embodiment is basically the same as the power-on reset circuit 100 in Embodiment 1 in terms of circuit structure. The differences are as follows:
[0046] The buffer unit 2 includes a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7, an eighth MOS transistor M8, a second inverter INV2, a second resistor R2, and a third resistor R3.
[0047] The source of the third MOSFET M3 is connected to the power supply voltage VDD. The gates of the third MOSFET M3, the fourth MOSFET M4, the fifth MOSFET M5, and the sixth MOSFET M6 are interconnected and serve as the input terminal of the power-on reset circuit 100. The drain of the third MOSFET M3 and the source of the fourth MOSFET M4 are respectively connected to the source of the seventh MOSFET M7. The drains of the fourth MOSFET M4, the drains of the fifth MOSFET M5, the gate of the seventh MOSFET M7, and the gate of the eighth MOSFET M8 are respectively connected to the source of the seventh MOSFET M7. The source of the fifth MOSFET M5 and the drain of the sixth MOSFET M6 are connected to the source of the eighth MOSFET M8, respectively. The source of the sixth MOSFET M6 is grounded. The drain of the seventh MOSFET M7 is connected to the first terminal of the second resistor R2, and the second terminal of the second resistor R2 is grounded. The drain of the eighth MOSFET M8 is connected to the first terminal of the third resistor R3, and the second terminal of the third resistor R3 is used to connect to the power supply voltage VDD. The output terminal of the second inverter INV2 serves as the output terminal of the buffer unit 2.
[0048] Please refer to Figure 4 , Figure 4 This is a schematic diagram illustrating the simulation results of the power-on reset circuit provided in this embodiment of the invention under continuous fast power-on, fast power-off, and fast power-on conditions. The fast power-on and fast power-off times are both 100ms. Please refer to... Figure 5 , Figure 5 This is a schematic diagram illustrating the simulation results of the power-on reset circuit provided in this embodiment of the invention under continuous slow power-on, slow power-off, and slow power-on conditions. The slow power-on and slow power-off times are both 400ms. The simulations above verify that the power-on reset circuit 100 proposed in this invention is essentially unaffected by the power-on time of the power supply voltage VDD, and can still generate the corresponding reset signal RST_N normally during continuous power-on and power-off processes.
[0049] Compared with existing technologies, this invention utilizes a power-on reset unit and a buffer unit. The input terminal of the power-on reset unit is connected to the power supply voltage, and the output terminal of the power-on reset unit is connected to the input terminal of the buffer unit. The power-on reset unit generates an initial reset logic signal and sends it to the buffer unit during the power supply voltage power-on process. The output terminal of the buffer unit outputs a reset signal. The buffer unit generates a reset signal output based on the initial reset logic signal. Thus, the power-on reset circuit proposed in this invention has a simple structure, no static power consumption after reset, and high reliability, enabling normal reset even under power supply fluctuations or continuous power-on / off cycles.
[0050] Example 3
[0051] This invention also provides a radio frequency (RF) chip, which includes the power-on reset circuit 100 as described in Embodiment 1 or the power-on reset circuit 200 as described in Embodiment 2, and can achieve the same technical effect. Refer to the description in the above embodiments, which will not be repeated here.
[0052] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.
[0053] The embodiments of the present invention have been described above with reference to the accompanying drawings. The disclosed embodiments are merely preferred embodiments of the present invention. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many equivalent changes in form without departing from the spirit and scope of the claims of the present invention, and all such changes are within the protection scope of the present invention.
Claims
1. A power-on reset circuit, characterized in that, The power-on reset circuit includes a power-on reset unit and a buffer unit; The input terminal of the power-on reset unit is used to connect to the power supply voltage, and the output terminal of the power-on reset unit is connected to the input terminal of the buffer unit. The power-on reset unit is used to generate an initial reset logic signal and send it to the buffer unit during the power supply voltage power-on process. The output terminal of the buffer unit is used to output a reset signal; the buffer unit is used to generate the reset signal according to the initial reset logic signal and output it. The power-on reset unit includes a first resistor, a first capacitor, a second capacitor, a first MOSFET, a second MOSFET, and a first inverter; The source of the first MOSFET serves as the input terminal of the power-on reset unit. The gate of the first MOSFET is connected to the first terminal of the first resistor. The drain of the first MOSFET is connected to the first terminal of the first capacitor and the gate of the second MOSFET. The second terminal of the first resistor, the second terminal of the first capacitor, and the source of the second MOSFET are all grounded. The drain of the second MOSFET is connected to the input terminal of the first inverter. The output terminal of the first inverter serves as the output terminal of the power-on reset unit. The first terminal of the second capacitor is connected to the source of the first MOSFET, and the second terminal of the second capacitor is connected to the drain of the second MOSFET.
2. The power-on reset circuit as described in claim 1, characterized in that, The first MOS transistor is a PMOS transistor.
3. The power-on reset circuit as described in claim 1, characterized in that, The second MOS transistor is an NMOS transistor.
4. The power-on reset circuit as described in claim 1, characterized in that, The buffer unit is a Schmitt trigger or an even-stage inverter.
5. The power-on reset circuit as described in claim 1, characterized in that, The buffer unit includes a third MOSFET, a fourth MOSFET, a fifth MOSFET, a sixth MOSFET, a seventh MOSFET, an eighth MOSFET, a second inverter, a second resistor, and a third resistor; The source of the third MOSFET is connected to the power supply voltage. The gates of the third MOSFET, the fourth MOSFET, the fifth MOSFET, and the sixth MOSFET are interconnected and serve as the input terminal of the buffer unit. The drain of the third MOSFET and the source of the fourth MOSFET are respectively connected to the source of the seventh MOSFET. The drains of the fourth MOSFET, the fifth MOSFET, the seventh MOSFET, and the eighth MOSFET are respectively connected to the input terminal of the second inverter. The source of the fifth MOSFET and the drain of the sixth MOSFET are respectively connected to the source of the eighth MOSFET. The source of the sixth MOSFET is grounded. The drain of the seventh MOSFET is connected to the first terminal of the second resistor, the second terminal of the second resistor is grounded, and the drain of the eighth MOSFET is connected to the first terminal of the third resistor. The second terminal of the third resistor is connected to the power supply voltage. The output terminal of the second inverter serves as the output terminal of the buffer unit.
6. The power-on reset circuit as described in claim 5, characterized in that, The third, fourth, and seventh MOS transistors are all PMOS transistors, while the fifth, sixth, and eighth MOS transistors are all NMOS transistors.
7. A radio frequency chip, characterized in that, The radio frequency chip includes the power-on reset circuit as described in any one of claims 1-6.