PHY for generating reset signal of dram and apparatus including same

Abstract

Disclosed is a PHY comprising: a buffer that generates a second reset signal; a reset-type D-latch that receives the second reset signal as an input; a transmitter that converts a third reset signal output by the reset-type D-latch to generate a reset signal that can be provided to DRAM; a first POR module that provides a reset signal to a reset terminal of the reset-type D-latch; and a second POR module that provides an enable signal to an enable terminal of the reset-type D-latch. The reset-type D-latch and the transmitter operate in response to a second voltage, and the buffer operates in response to a first voltage. The first POR module is configured such that the reset signal is generated as a pulse waveform having a high level only at a rising edge of the second voltage, and the second POR module is configured such that the enable signal is generated as a waveform having a high level only when both the first voltage and the second voltage have a high level.

Description

PHY that generates a reset signal for DRAM and a device including the same

[0001] The present invention relates to the structure of a PHY that exchanges signals with a DRAM, and in particular to the structure of a circuit that generates a reset signal provided to the DRAM.

[0002] A reset signal for resetting the DRAM can be generated by the PHY and provided to the DRAM. Internally, an internal reset signal having a voltage swing of a first voltage is generated within the PHY, and said internal reset signal is converted by the PHY's transmitter into an I / O reset signal having electrical characteristics that the DRAM can recognize.

[0003] The power consumed by the PHY and DRAM can be provided and controlled by the PMIC. In retention mode, a mode in which the PHY and DRAM do not communicate, the PMIC may withhold some of the multiple power supplies with multiple voltage levels provided to the PHY in order to reduce the power consumption of the PHY. In this case, due to the withheld power in retention mode, some components within the PHY that generate the internal reset signal may not operate, and as a result, the value of the internal reset signal may not be specified in retention mode. Consequently, there is a risk that the I / O reset signal output by the transmitter may enter an unwanted reset state. In retention mode, the DRAM must maintain its existing data values ​​by repeatedly refreshing; however, if an unwanted reset occurs, there is a problem that data loss and errors may occur in the system containing the DRAM.

[0004] The present invention aims to provide a technology that prevents the phenomenon where the value of the internal reset signal of the PHY is not specified, even when some internal components of the PHY fail to operate according to the power management policy of the PHY, from propagating to the I / O reset signal directly provided to the DRAM.

[0005] According to one aspect of the present invention, a device comprising a PHY (101) that provides a reset signal to a DRAM (200) may be provided. The PHY comprises: a buffer (110) that generates a second reset signal (72); a D-latch (30) that receives the second reset signal; a transmitter (120) that generates an I / O reset signal (70) for converting a third reset signal (73) output by the D-latch and providing it to the DRAM (200); a first POR module (10) that provides a first signal (11) to a reset terminal (RST) of the D-latch; and a second POR module (20) that provides a second signal (12) to an enable terminal (G) of the D-latch. The D-latch and the transmitter operate by a second voltage (VH). The buffer operates by a first voltage (VL). The first POR module is configured such that the first signal is generated as a waveform having a reset pulse (111) only at the rising edge of the second voltage (VH). The second POR module is configured such that the second signal is generated as a waveform having an enable level (121) only when both the first voltage and the second voltage are at a high level.

[0006] The above D-latch may be a reset type D-latch.

[0007] At this time, the device may further include a PMIC (510). At this time, the operating mode of the PHY includes a normal mode and a retention mode, and in the normal mode, the PMIC is configured to provide both the first voltage and the second voltage to the PHY, and in the retention mode, the PMIC may be configured to provide only the second voltage to the PHY and stop providing the first voltage.

[0008] At this time, during the time interval in which the PHY operates in the retention mode, the value of the second reset signal generated by the buffer may not be determined.

[0009] At this time, the first voltage may be lower than the second voltage.

[0010] At this time, the device further includes a PMIC, and the PMIC may be configured to raise the second voltage before the first voltage during the cold boot process of the PHY.

[0011] At this time, the first voltage may be a voltage (VDD) that operates the serializer, deserializer, or clock control circuit of the PHY, or the first voltage may be a voltage (VDDQ) that supplies power to the input / output buffer of the PHY.

[0012] At this time, the second voltage may be the voltage (VDD2H) used for driving the word line within the PHY.

[0013] According to another aspect of the present invention, a PHY may be provided comprising: a buffer (110) for generating a second reset signal (72); a D-latch (30) for receiving the second reset signal; a transmitter (120) for generating an I / O reset signal (70) for converting a third reset signal (73) output by the D-latch and providing it to a DRAM (200); a first POR module (10) for providing a first signal (11) to a reset terminal (RST) of the D-latch; and a second POR module (20) for providing a second signal (12) to an enable terminal (G) of the D-latch. In this case, the D-latch and the transmitter are operated by a second voltage (VH). The buffer is operated by a first voltage (VL). The first POR module is configured such that the first signal is generated as a waveform having a reset pulse (111) only at the rising edge of the second voltage (VH), and the second POR module is configured such that the second signal is generated as a waveform having an enable level (121) only when both the first voltage and the second voltage are at a high level.

[0014] According to another aspect of the present invention, a PHY may be provided for generating an I / O reset signal (70) to be provided to a DRAM (200). The PHY is configured to set the level of the I / O reset signal to a level that resets the DRAM during a time interval of a cold boot mode, to set the level of the I / O reset signal to a level corresponding to the level of the internal reset signal of the PHY during a time interval of a normal mode, and to maintain the level of the I / O reset signal at the same level as the level of the I / O reset signal at the time immediately preceding each time interval of a retention mode. The PHY is configured to automatically switch to the normal mode when the cold boot mode ends, and the PHY is configured to switch from the normal mode to the retention mode by a signal from outside the PHY. The above cold boot mode is a mode in which all power supplied to the PHY is switched from an off state to an on state, the above normal mode is a mode in which all power supplied to the PHY is maintained in an on state, and the above retention mode is a mode in which some of the power supplied to the PHY is switched to an off state.

[0015] At this time, the PHY may include a D-latch (30); a first POR module (10) configured to provide a reset pulse (111) to the reset terminal (RST) of the D-latch only during the time interval of the cold boot mode; and a second POR module (20) configured to provide an enable level (121) to the enable terminal (G) of the D-latch only during the time interval of the normal mode.

[0016] At this time, the PHY may further include a buffer (110) that generates a second reset signal (72); and a transmitter (120) that converts a third reset signal (73) output by the D-latch to generate the I / O reset signal (70). At this time, the D-latch is configured to receive the second reset signal, and the D-latch and the transmitter operate by the second voltage (VH), and the buffer can operate by the first voltage (VL). The first POR module is configured to output the reset pulse only at the rising edge of the second voltage (VH), and the second POR module may be configured to output the enable level (121) only when both the first voltage (VL) and the second voltage (VH) are at a high level.

[0017] According to the present invention, even when a phenomenon occurs in which the value of the internal reset signal of the PHY is not specified because some internal components of the PHY do not operate according to the power management policy of the PHY, a technology can be provided to prevent such phenomenon from propagating to the I / O reset signal directly provided to the DRAM.

[0018] Figure 1 shows the basic concept of a configuration in which a PHY provides a reset signal to a DRAM.

[0019] FIG. 2 shows a reset signal control configuration of a PHY provided according to one embodiment of the present invention.

[0020] Figure 3 is a timing diagram of each signal presented in Figure 2.

[0021] FIG. 4 shows an example of the configuration of a computing device including a PHY provided according to one embodiment of the present invention.

[0022] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be implemented in various other forms. The terms used in this specification are intended to aid in understanding the embodiments and are not intended to limit the scope of the present invention. Furthermore, singular forms used below include plural forms unless the phrases clearly indicate otherwise.

[0023] The following explanation will be described with reference to FIGS. 1 to 4.

[0024] <PHY의 전압 상승 시퀀스>

[0025] In DRAM (e.g., DDR memory) technology, the power-up sequence during the cold booting process ensures that the DRAM module and the PHY (Physical Layer) are stably initialized and reach a normal operating state. The power-up sequence prevents initialization errors or instability by clearly defining the order of power supply and signal setup.

[0026] In one embodiment, cold booting is a process of starting the device anew while the power is off, and all hardware including DRAM (200) can be initialized.

[0027] Information regarding the above power rise sequence can be stored, for example, in the SPD data (EEPROM) of the DRAM module, BIOS / UEFI firmware, registers of the PHY (101), etc.

[0028] The entity that reads and executes the above power rise sequence can be controlled by a device, for example, such as BIOS / UEFI firmware during the initialization process. To this end, the PMIC (510), PHY (101), and DRAM (200) can interact.

[0029] The PHY (101) is responsible for the analog and digital interfaces necessary to transmit and receive signals to and from the DRAM (200).

[0030] In one embodiment, in the PHY (101), VDD2H (high voltage power), VDD (core power), VDDQ (I / O power), and VREF power (reference voltage) rise in order and perform the following functions.

[0031] VDD2H can supply power to circuits requiring specific high voltage within the PHY (101). For example, VDD2H is used to drive word lines and high-power transistors within the PHY (101), and this voltage rises first to prepare the PHY (101) to stably transmit data to the DRAM (200). The magnitude of this voltage can have a value between, for example, 2.5V and 3.3V.

[0032] VDD is the primary power supply that drives the main core circuits of the PHY (101), and can provide the power required for signal processing, serializer / deserializer (SerDes), and clock control circuits to operate in the PHY (101), for example. This voltage must be stabilized so that the PHY (101) can operate normally and process signals stably. The magnitude of this voltage can be, for example, 1.2V or 1.35V.

[0033] VDDQ supplies power to the input / output (I / O) buffer of the PHY (101) and sets the I / O signal voltage for data transfer between the PHY (101) and the DRAM (200). After this voltage rises, the PHY (101) can send and receive data to and from the DRAM (200). The magnitude of this voltage may be, for example, 1.2V, 1.1V, or 1.35V, which is equal to or lower than VDD.

[0034] VREF is the voltage referenced by PHY (101) for accurate reading when a voltage swing occurs during signal reading. The magnitude of this voltage is half the level of VDDQ.

[0035] In one embodiment, the power rise sequence of the PHY (101) described above can be controlled by a Power Management IC (PMIC) (510). The PMIC (510) also controls the power used in the DRAM (200) that interacts with the PHY (101). The PMIC (510) raises the power of VDD2H, VDD, VDDQ, and VREF at the required timing and monitors in real time whether each voltage has reached a target level. When each voltage stably reaches a designated level and is maintained without noise, it begins raising the next power. That is, after each power reaches a set level, a waiting time for stabilization is secured. For example, it proceeds by raising VDD after a certain amount of time has passed since VDD2H has fully risen. Since the DRAM (200) and the PHY (101) are closely connected and must operate closely in terms of data transmission and signal stability, the PMIC (510) can be designed to control the power of the DRAM (200) and the PHY (101) simultaneously.

[0036] <DRAM의 동작 모드>

[0037] In DRAM technology, cold booting (T1), normal mode (T2), and retention mode (data retention mode) (T3) refer to various operating states of the DRAM (200), and each mode performs functions related to memory initialization, normal operation, and power saving.

[0038] The above cold boot refers to the process in which the DRAM (200) is initialized after receiving power for the first time or being reset. During the cold boot (T1), not only the DRAM (200) but also the PHY (101) receives power for the first time. In this process, all circuits and registers of the DRAM (200) are set to a default state. In this procedure, the PMIC (510) supplies voltages such as VDD2H, VDD, VDDQ, and VREF in sequence to stably raise the power of the DRAM (200) and PHY (101). During the cold boot process, all circuits and registers are set to an initial state before the DRAM (200) begins normal operation.

[0039] The above normal mode is a basic operation mode in which the DRAM (200) performs read and write operations while in an active state. In this mode, the memory cells of the DRAM (200) remain continuously active, enabling data exchange with the CPU and memory controller. Additionally, each memory cell of the DRAM (200) periodically performs a refresh operation to maintain data. In this mode, all circuits of the DRAM (200) are active, resulting in relatively high power consumption.

[0040] The above retention mode is a power-saving mode in which the DRAM (200) retains only data in a low-power state. Generally, memory data is retained using only retention power. At this time, most of the main circuits of the DRAM (200) are deactivated to minimize power consumption, and only a minimum amount of power is supplied so that periodic refresh operations are performed to retain data. The system may switch to the above retention mode when the CPU or memory controller has stopped accessing data to the DRAM (200).

[0041] <State of PHY in Retention Mode>

[0042] In the above retention mode, some of the power supplied to the PHY (101) is interrupted, thereby minimizing power consumption in the PHY (101). In this mode, most functions of the PHY (101) can be disabled because only data retention in the DRAM (200) is required, and no actual data transmission or communication takes place. Accordingly, the power state required for the PHY (101) can also be changed.

[0043] In one embodiment, VDDQ, which is an I / O voltage for a data transfer signal between the PHY (101) and the DRAM (200), may be de-supplied. This is because I / O power is unnecessary since no data transfer occurs in retention mode.

[0044] <PHY 내부에서 발생하는 언노운 리셋 신호>

[0045] Figure 1 shows the basic concept of a configuration in which a PHY provides a reset signal to a DRAM.

[0046] The PHY (101) may include a buffer (110) and a transmitter (120).

[0047] The buffer (110) can be operated by the first voltage (VL) and the transmitter (120) can be operated by the second voltage (VH).

[0048] In a preferred embodiment, the second voltage (VH) is greater than the first voltage (VL).

[0049] The first voltage (VL) may be, for example, the VDD or VDDQ described above.

[0050] The second voltage (VH) may be, for example, the VDD2H described above.

[0051] The PHY (101) can generate a first reset signal (Reset1) (71) as needed, for example, as part of an initialization sequence.

[0052] The buffer (110) can receive a first reset signal (71) and output a second reset signal (Reset2) (72) with consistency and strength maintained. The second reset signal (72) may have a first voltage swing. For example, the second reset signal (72) may have a value of 0[V] or VL[V]. That is, the magnitude of the first voltage swing may be VL[V].

[0053] The transmitter (120) can receive a second reset signal (72) and convert it into an I / O reset signal (Reset_n) (70) having a voltage that meets the input requirements of the DRAM (200) and output it. The I / O reset signal (70) may have a second voltage swing that is larger than the first voltage swing. For example, the I / O reset signal (70) may have a value of 0[V] or VH[V]. That is, the magnitude of the second voltage swing may be VH[V].

[0054] In this specification, an example is provided in which the DRAM (200) is reset when a low-level voltage is input to the reset input terminal of the DRAM (200). Accordingly, the DRAM (200) is reset when the I / O reset signal (Reset_n) (70) is at a low level.

[0055] At this time, there is a problem that the second reset signal (72) input to the transmitter (120) may have an unknown state for some reason. In this case, the transmitter (120) transmits the second reset signal (72) having an unknown state to the DRAM (200), and as a result, a serious problem arises in that the DRAM (200) may be reset unintentionally.

[0056] Therefore, it is necessary to control the second reset signal (72) input to the transmitter (120) so that it does not have an unknown state.

[0057] There may be various situations in which the second reset signal (72) input to the transmitter (120) may be in an unknown state. A typical example is a situation in which the PHY (101) operates in retention mode.

[0058] According to one embodiment, when the PHY (101) is in retention mode as described above, VDDQ may not be provided to the PHY (101). Therefore, when the first voltage (VL), which is the operating voltage of the buffer (110), is VDDQ, since VDDQ is not provided, the buffer (110) does not operate normally, and as a result, the output of the buffer (110) has an unknown state.

[0059] Through the examples described above, it can be understood that the second reset signal (72) input to the transmitter (120) may have an unknown state. Additionally, it can be sufficiently inferred that there may be other situations in which the second reset signal (72) input to the transmitter (120) has an unknown state. Some of these situations may be unknown to the designer of the device.

[0060] The reason the second reset signal (72) input to the transmitter (120) has an unknown state is that the buffer (110) outputs the second reset signal (72) in an unknown state. Therefore, it is necessary to design the PHY (101) so that even if the buffer (110) outputs the second reset signal (72) in an unknown state, the I / O reset signal (70) provided to the DRAM (200) is not affected by this.

[0061] In addition, the main situation in which the buffer (110) outputs the second reset signal (72) in an unknown state is a situation in which the first voltage (VL), which is the operating power input to the buffer (110), is not supplied. Therefore, it is necessary to design the PHY (101) so that the I / O reset signal (70) provided to the DRAM (200) is not affected even if the first voltage (VL), which is the operating power input to the buffer (110), is not supplied. Accordingly, in one embodiment of the present invention, a configuration utilizing the first voltage (VL), which is the operating power input to the buffer (110), is presented.

[0062] FIG. 2 shows a reset signal control configuration of a PHY provided according to one embodiment of the present invention.

[0063] Figure 3 is a timing diagram of each signal presented in Figure 2.

[0064] The following explanation will be provided with reference to FIGS. 2 and FIGS. 3.

[0065] The PHY (101) may include a first POR module (10), a second POR module (20), a D-latch (30), a buffer (110), and a transmitter (120).

[0066] Among the terms presented in this specification, 'POR' in 'first POR module' and 'second POR module' is a designation given to distinguish it from other functional parts. In this specification, the first POR module (10) and the second POR module (20) may be simply referred to as the first module (10) and the second module (20), respectively, or may be referred to as the first reset module (10) and the second reset module (20), respectively.

[0067] The buffer (110) can be operated by the first voltage (VL) and the transmitter (120) can be operated by the second voltage (VH). The D-latch (30) and the first POR module (10) can be operated by the second voltage (VH). The second POR module (20) can be operated by the first voltage (VL) and the second voltage (VH).

[0068] The first voltage (VL) above may be, for example, the VDD or VDDQ described above.

[0069] The second voltage (VH) above may be, for example, VDD2H described above.

[0070] PHY (101) can generate the first reset signal (71) described above.

[0071] The buffer (110) can receive the first reset signal (71) and output the second reset signal (72) described above. The second reset signal (72) may have the first voltage swing.

[0072] The first POR module (10) can generate a first POR output (POR1 out) (11) determined by the second voltage (VH).

[0073] The second POR module (20) can generate a second POR output (POR2 out) (12) determined by the first voltage (VL) and the second voltage (VH).

[0074] In the present specification, the first POR output (11) and the second POR output (12) may be referred to as the first output (11) and the second output (12), or as the first signal (11) and the second signal (12), or as the reset signal (11) and the enable signal (12).

[0075] The D-latch (30) may be a resettable D-latch having a reset input. The D-latch (30) may receive a second reset signal (72) and generate and output a third reset signal (73). The third reset signal (73) may have the second voltage swing. The value of the third reset signal (73) may be determined by the second reset signal (72) input to the D input terminal of the D-latch (30), the first POR output (11) input to the reset input terminal (RST), and the second POR output (12) input to the enable input terminal (G).

[0076] The D-latch (30) is a form of the basic D-latch with a reset input (RST) added, providing a data storage function and the ability to initialize the output to a specific value (typically 0). This latch is controlled via the D input, the enable (or clock) input (G), and the reset input (RST).

[0077] The D-latch (30) performs the following basic operations. That is, when the enable signal (G) (= second POR output (12)) is activated, the value of the D input is transmitted to the Q output. That is, as described below, when the second POR output (12) is at the enable level (121), the value of the D input is transmitted to the Q output. When the enable signal (G) is activated, if the D value changes, the Q output also changes immediately. This can be called the transparent state of the latch. When the enable signal (G) is deactivated, the value of the D input does not affect the Q output, and the Q output maintains the last stored value.

[0078] When the reset input (RST) (= first POR output (11)) of the D-latch (30) is disabled, for example, when RST = first POR output (11) = '0', the D-latch (30) performs the basic operation described above. That is, depending on the enable signal (G), the D input is reflected in the Q output, or the last stored value of the Q output is maintained.

[0079] In contrast, when the reset input (RST) (= first POR output (11)) of the D-latch (30) is activated, for example, in the state where RST = first POR output (11) = '1', the Q output is set to a specific value immediately, regardless of the specific value of the second voltage (VH) applied to the D-latch (30). In one embodiment of the present invention, the specific value may be 0. In this state, the Q output is maintained in the reset state (0) regardless of the state of the D input and the enable signal (G). The Q output continues to maintain the 0 state until the reset signal (RST) is deactivated again. After the reset signal (RST) is deactivated, the D input is reflected in the Q output again according to the enable signal.

[0080] To explain this again with reference to FIG. 3, the first POR output (11), i.e., the first signal (11), is generated as a waveform having a reset pulse (111) during the first time (t1) from the initial time (t0). In FIG. 3, the reset pulse is shown rising together with the rise of the second voltage (VH). Although FIG. 3 shows the reset pulse (111) as a sawtooth of a general sawtooth wave, the first POR module (10) may be configured so that the reset pulse maintains a high level for a predetermined time interval from the first time (t1).

[0081] The transmitter (120) can receive the third reset signal (73) and convert it into an I / O reset signal (Reset_n) (70) having a voltage that meets the input requirements of the DRAM (200) and output it. The I / O reset signal (70) may have the second voltage swing.

[0082] At this time, even if the second reset signal (72) input to the D-latch (30) has an unknown state, the D-latch (30) may not reflect the unknown state of the second reset signal (72) in the third reset signal (73). As a result, the third reset signal (73) input to the transmitter (120) may not have an unknown state, and thus the problem of the DRAM (200) being unintentionally reset during the time interval when the second reset signal (72) has an unknown state can be resolved.

[0083] Figure 3 illustrates the operation characteristics of the circuit configuration of Figure 2 in which, when the second reset signal, which is an internal signal of the PHY, has an unknown state, the unknown state is not transmitted to the transmitter of the PHY.

[0084] The first time interval (T1) is the cold boot time interval. In the first time interval (T1), the second voltage (VH) rises first according to the power rise sequence of the cold boot, and the first voltage (VL) rises subsequently.

[0085] Between the first time (t0) and the first time (t1), the second voltage (VH) rises, and at the first time (t1), the rise of the second voltage (VH) ends and the risen state is maintained.

[0086] The first POR module (10) is configured to output a single pulse at the rising edge of the second voltage (VH). When the rising edge period of the second voltage (VH) ends, the single pulse output also ends, and during other time periods excluding the rising edge period of the second voltage (VH), the first POR module (10) is configured to output a value of a specific state, such as a low state.

[0087] To this end, the specific internal circuit configuration of the first POR module (10) can be designed in various ways. The present invention is not necessarily limited to the specific internal circuit configuration of the first POR module (10). However, since the input / output characteristics of the first POR module (10) are clearly defined, the feasibility of implementing the present invention is guaranteed.

[0088] In this way, the first POR output (11), which is the output signal of the first POR module (10), has one pulse at the rising edge of the second voltage (VH). Since the first POR output (11) is a reset signal (RST) input to the D-latch (30), when the rising edge of the second voltage (VH) occurs, the Q output of the D-latch (30) is immediately set to a specific value of 0.

[0089] Between the first time point (t1) and the second time point (t2), the first voltage (VL) rises, and at the second time point (t2), the rise of the first voltage (VL) ends and the risen state is maintained.

[0090] The second POR module (20) may be configured to apply an enable level (121) to the second POR output (12), which is the output signal, only during the time interval when both the first voltage (VL) and the second voltage (VH) are in a high state, and to apply a disable level (122) to the second POR output (12) during other time intervals. FIG. 3 illustrates an example in which the enable level (121) is a high level and the disable level (122) is a low level.

[0091] To this end, the specific internal circuit configuration of the second POR module (20) can be designed in various ways. The present invention is not necessarily limited by the specific internal circuit configuration of the second POR module (20). However, since the input / output characteristics of the second POR module (20) are clearly defined, the feasibility of implementing the present invention is guaranteed.

[0092] In this way, from the second time point (t2), the second POR output (12) has an enable level (121). Since the second POR output (12) is an enable signal (G) input to the D-latch (30), from the second time point (t2), the D-latch (30) has a transparent state in which the Q output changes immediately when the D value changes.

[0093] FIG. 3 presents an example in which the second reset signal (72) changes from a low state to a high state between the second time (t2) and the third time (t3). At this time, since the D-latch (30) operates in a transparent state during the second time interval (T2) between the second time (t2) and the third time (t3), it can be confirmed that the state of the second reset signal (D) (72) is reflected in the third reset signal (Q) (73) as is.

[0094] At this time, it can be assumed that retention started at the third time (t3). For example, retention of PHY (101) can be started by an external device of PHY (101) providing a retention start command to PHY (101).

[0095] When retention begins, the PMIC (510) outside the PHY (101) may stop supplying the first voltage (VL) to the PHY (101) as described above. Thus, from the third time (t3), the first voltage (VL) has a low state.

[0096] At this time, since the operation of the buffer (110) operated by the first voltage (VL) is interrupted, the second reset signal (72) output by the buffer (110) becomes unknown from the third time (t3).

[0097] However, since the first voltage (VL) has a low state from the third time (t3), the second POR output (12) output by the second POR module (20) is set to a disabled level (122). This is because the second POR module (20) is configured so that if either the first voltage (VL) or the second voltage (VH) has a low state, the second POR output (12) is set to a disabled level (122).

[0098] Since the second POR output (12) is the enable signal (G) of the D-latch (30), the D-latch (30) maintains the previous output from the third time (t3). In the example of FIG. 3, the value of the third reset signal (73) that the D-latch (30) was outputting immediately before the third time (t3) was in a high state, so the value of the third reset signal (73) remains in a high state even after the third time (t3). That is, the D input input to the D-latch (30) after the third time (t3) is in an unknown state, but the D-latch (30) provides a high-level output regardless of the D input in an unknown state. Therefore, despite the unknown state of the reset signal (72) inside the PHY due to the retention mode, the effect is that the PHY (101) in the retention mode does not provide an unintended I / O reset signal (70) to the DRAM (200).

[0099] In one embodiment of the present invention, the PHY (101) is provided in a separate package from the DRAM (200) and may be integrated into the SoC together with the memory controller or configured as an external module distinct from the SoC.

[0100] Examples of SoCs with integrated PHY (101) include Qualcomm Snapdragon TM Series, Apple A TM Series and M TM Series, Samsung Exynos TM Series, NVIDIA Tegra TM There are series, Intel and AMD's latest CPU SoCs, etc.

[0101] FIG. 4 shows an example of the configuration of a computing device including a PHY provided according to one embodiment of the present invention.

[0102] The computing device (1) may include a processor (100), DRAM (200), non-volatile storage (300), a display unit (400), a power supply unit (500), a PMIC (510), a communication module (600), a sensor module (700), an audio module (800), and an input / output interface (900).

[0103] In FIG. 4, the PMIC (510) is shown as being distinct from the other components shown in FIG. 4, but it may also be seen as being integrated into other components, such as the power supply (500).

[0104] The processor (100) may include a PHY (101) and a memory controller (102).

[0105] The computing device (1) may be a user device such as, for example, a smartphone, tablet, laptop (notebook), smartwatch and wearable device, smart TV and streaming device, game console and portable game console, desktop all-in-one PC, automotive infotainment system, smart home device, and virtual reality (VR) and augmented reality (AR) device.

[0106] Generally, PHY (Physical Layer) is understood as an abstract concept representing an abstract layer in communication technology, but in this specification, PHY (101) may refer to a device or an electronic circuit. Since PHY (101) is responsible for the function of generating and processing physical signals in a communication system, this layer may be implemented in hardware. In some embodiments, the PHY function is often provided in the form of an independent chip. Also, in one embodiment of the present invention, since PHY (101) acts as an interface connecting a higher layer and a physical medium, PHY (101) may be implemented as a specific physical electronic circuit. Also, in one embodiment of the present invention, PHY (101) performs a specific signal processing as a hardware block included in a System on Chip (SoC).

[0107] Using the embodiments of the present invention described above, those skilled in the art will be able to easily make various changes and modifications within the scope of the essential characteristics of the present invention. The content of each claim of the patent claims may be combined with other claims that are not related by reference within the scope of what can be understood from this specification.

Claims

1. A device including a PHY that provides a reset signal to a DRAM, The above PHY is, A buffer that generates a second reset signal; A D-latch receiving the above second reset signal; A transmitter that generates an I / O reset signal for providing to a DRAM by converting the third reset signal output by the above D-latch; A first POR module that provides a first signal to the reset terminal of the above D-latch; and A second POR module that provides a second signal to the enable terminal of the above D-latch; Includes, The above D-latch and the above transmitter are operated by a second voltage, and The above buffer operates by a first voltage, and The first POR module is configured such that the first signal is generated as a waveform having a reset pulse only at the rising edge of the second voltage, and The second POR module is configured such that the second signal is generated as a waveform having an enable level only when both the first voltage and the second voltage are at a high level. device.

2. In Paragraph 1, The above device further includes a PMIC, and The operation modes of the above PHY include a normal mode and a retention mode, and In the above normal mode, the PMIC is configured to provide both the first voltage and the second voltage to the PHY, and In the above retention mode, the PMIC is configured to provide only the second voltage to the PHY and stop providing the first voltage, device.

3. A device according to claim 2, characterized in that the value of the second reset signal generated by the buffer is not determined during the time interval in which the PHY operates in the retention mode.

4. A device according to claim 1, wherein the first voltage is lower than the second voltage.

5. In Paragraph 1, The above device further includes a PMIC, and The above PMIC is configured to raise the second voltage before the first voltage during the cold boot process of the above PHY, device.

6. In Paragraph 1, The first voltage is a voltage that operates the serializer, deserializer, or clock control circuit of the PHY, or The first voltage above is a voltage that supplies power to the input / output buffer of the PHY, device.

7. A device according to claim 1, wherein the second voltage is a voltage used to drive the word line within the PHY.

8. A buffer that generates a second reset signal; A D-latch receiving the above second reset signal; A transmitter that generates an I / O reset signal for providing to a DRAM by converting the third reset signal output by the above D-latch; A first POR module that provides a first signal to the reset terminal of the above D-latch; and A second POR module that provides a second signal to the enable terminal of the above D-latch; Includes, The above D-latch and the above transmitter are operated by a second voltage, and The above buffer operates by a first voltage, and The first POR module is configured such that the first signal is generated as a waveform having a reset pulse only at the rising edge of the second voltage, and The second POR module is configured such that the second signal is generated as a waveform having an enable level only when both the first voltage and the second voltage are at a high level. PHY.

9. As a PHY that generates an I / O reset signal to be provided to DRAM, During the time interval of the cold boot mode, the level of the I / O reset signal is set to a level that resets the DRAM, and During the time interval of normal mode, the level of the I / O reset signal is set to a level corresponding to the level of the internal reset signal of the PHY, and, During the retention mode time interval, the level of the I / O reset signal is maintained at a constant level equal to the level of the I / O reset signal at the time of entry into the retention mode time interval, and The above PHY is configured to automatically switch to the normal mode when the cold boot mode is terminated, and the above PHY is configured to switch from the normal mode to the retention mode by a signal from outside the PHY. The above cold boot mode is a mode in which all power supplied to the PHY is switched from an off state to an on state, the above normal mode is a mode in which all power supplied to the PHY is maintained in an on state, and the above retention mode is a mode in which some of the power supplied to the PHY is switched to an off state. PHY.

10. In Paragraph 9, The above PHY is, D-latch; A first POR module configured to provide a reset pulse to the reset terminal of the D-latch only during the time interval of the above cold boot mode; and A second POR module configured to provide an enable level to the enable terminal of the D-latch only during the time interval of the above normal mode; including, PHY.

11. In Paragraph 10, A buffer that generates a second reset signal; and A transmitter that converts the third reset signal output by the D-latch to generate the I / O reset signal; Includes more, The above D-latch is configured to receive the above second reset signal, and The above D-latch and the above transmitter are operated by a second voltage, and The above buffer operates by a first voltage, and The first POR module is configured to output the reset pulse only at the rising edge of the second voltage, and The second POR module is configured to output the enable level only when both the first voltage and the second voltage are at a high level. PHY.

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