Multi-power management integrated circuit (PMIC) with shared output

Abstract

A multi-power management integrated circuit (PMIC) with a shared output is disclosed herein. More specifically, two or more PMICs can generate a shared output while balancing the current provided by the PMICs without being affected by device and component mismatches and inter-component variations. This balancing is accomplished by providing a current feedback loop and a shared voltage loop to each PMIC when multiple PMICs are active. When only a single PMIC is active, a switch deactivates the shared voltage feedback loop and activates a local voltage feedback loop. The use of multiple PMICs enables higher supply voltages to be provided to power amplifiers in a transmission chain to meet the requirements of emerging wireless standards while also maintaining better efficiency of the transmission chain.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 482,664, filed on February 1, 2023, entitled "Multiple Power Management Integrated Circuits (PMICs) with Shared Output", the disclosure of which is hereby incorporated by reference in its entirety. Technical Field

[0003] The technology of the present disclosure generally relates to power management integrated circuits (PMICs), and more particularly to systems with multiple PMICs having optional shared outputs. Background Art

[0004] Computing devices are abundant in modern society, and in particular, mobile communication devices have become increasingly common. The popularity of these mobile communication devices is due in part to the many functions that can now be performed on such devices. The increased processing power in such devices means that mobile communication devices have evolved from simple communication tools to sophisticated mobile multimedia centers, thus enhancing the user experience. As the number of available functions in such devices has grown, so has the pressure to find ways to reduce power consumption. One way to reduce power consumption is to place a power management integrated circuit (PMIC) or other power converter in the transmission chain to help provide an optimized supply voltage to the power amplifier in the transmission chain. While traditional PMICs have implemented envelope tracking and average power tracking type supply voltage control, recent generations of technology are placing additional burdens on PMICs, and these additional burdens provide room for innovation. Summary of the Invention

[0005] Aspects disclosed in the detailed description include multiple power management integrated circuits (PMICs) with shared outputs. More specifically, exemplary aspects of the present disclosure cover two or more PMICs that are capable of generating a shared output while balancing the current provided by the PMICs, regardless of device and component mismatches and variations between components. This balance is achieved by providing a current feedback loop and a shared voltage loop to each PMIC when multiple PMICs are active. When only a single PMIC is active, a switch deactivates the shared voltage feedback loop and enables a local voltage feedback loop. Using multiple PMICs enables a higher supply voltage to be provided to the power amplifier in the transmission chain to meet the requirements of emerging wireless standards, while also maintaining better efficiency in the transmission chain.

[0006] In this regard, in one aspect, a multi-PMIC system is disclosed. The multi-PMIC system includes a first PMIC configured to receive a target voltage and generate a first output signal. The multi-PMIC system further includes a second PMIC configured to receive the target voltage and generate a second output signal. The multi-PMIC system further includes an output node coupled to the first PMIC and the second PMIC and summing the first output signal and the second output signal to form a combined signal. The multi-PMIC system further includes a first current feedback loop configured to measure a first current of the first output signal and provide a first feedback signal to the first PMIC. The multi-PMIC system further includes a second current feedback loop configured to measure a second current of the second output signal and provide a second feedback signal to the second PMIC. The multi-PMIC system further includes a common voltage feedback loop coupling the output node to the first PMIC and the second PMIC and configured to provide a voltage measurement result from the output node to the first PMIC and the second PMIC.

[0007] In this regard, in another aspect, a mobile communication device is disclosed. The mobile communication device includes a transceiver that includes a multi-PMIC (multiple PMIC) (multi-PMIC) system. The multi-PMIC system includes: a first PMIC configured to receive a target voltage and generate a first output signal; a second PMIC configured to receive the target voltage and generate a second output signal; and an output node coupled to the first PMIC and the second PMIC and summing the first output signal and the second output signal to form a combined signal. The transceiver further includes: a first current feedback loop configured to measure a first current of the first output signal and provide a first feedback signal to the first PMIC; a second current feedback loop configured to measure a second current of the second output signal and provide a second feedback signal to the second PMIC; and a common voltage feedback loop coupling the output node to the first PMIC and the second PMIC and configured to provide a voltage measurement result from the output node to the first PMIC and the second PMIC.

[0008] In this regard, in another aspect, a method of managing power in a power amplifier is disclosed. The method includes: receiving a target voltage at a first PMIC from a remote location; generating a first output signal in response to receiving the target voltage; receiving the target voltage at a second PMIC; and generating a second output signal in response to receiving the target voltage. The method further includes: summing the first output signal and the second output signal to form a combined signal; measuring a first current of the first output signal; providing a first feedback signal to the first PMIC based on the first current; measuring a second current of the second output signal; providing a second feedback signal to the second PMIC based on the second current; and providing a voltage measurement result to the first PMIC and the second PMIC based on the combined signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a hybrid circuit and block diagram of a conventional multi-power management integrated circuit (PMIC) (multi-PMIC) system with a shared output and unbalanced currents;

[0010] Figure 2 is a hybrid circuit and block diagram of a multi-PMIC system with a shared output with balanced currents according to an exemplary aspect of the present disclosure;

[0011] Figure 3 is Figure 2 a more detailed schematic of the multi-PMIC system of

[0012] Figure 4 where some switching paths and more details regarding the control circuit are presented, which help prevent multiple current paths from drawing peak current simultaneously;

[0013] Figure 5 is Figure 2 a more detailed schematic of the multi-PMIC system of

[0014] Figure 6 is Figure 2 a more detailed schematic of the multi-PMIC system of

[0015] Figure 7 is Figure 2 a more detailed schematic of the multi-PMIC system of

[0016] Figure 8A is Figure 2 a more detailed diagram of a multi-PMIC system, which shows a series circuit that limits current to one of the PMICs;

[0017] Figure 8B is Figure 8A a counterpart of , where the series circuit limits current to the other of the PMICs;

[0018] Figure 8C is a graph of current versus time, which shows Figure 8A and Figure 8B how the current in and switches to prevent multiple current paths from drawing peak current simultaneously; and

[0019] Figure 9 is a block diagram of a transceiver that may be present in a mobile terminal, for example, according to an exemplary aspect of the present disclosure, and includes a transmission chain having a multi-PMIC system. Detailed Description

[0020] The embodiments set forth below represent the necessary information that enables those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. After reading the following detailed description with reference to the drawings, those skilled in the art will understand the concepts of the present disclosure and will appreciate applications of these concepts that are not specifically recited herein. It should be understood that these concepts and applications are within the scope of the present disclosure and the appended claims.

[0021] It should be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish different elements. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0022] It should be understood that when an element such as a layer, region, or substrate is referred to as being "on" or extending "onto" another element, it can be directly on the other element or directly extend onto the other element or there can also be intervening elements. In contrast, when an element is referred to as being "directly on" or "directly extending onto" another element, there are no intervening elements. Similarly, when an element such as a layer, region, or substrate is referred to as being "above" or extending "above" another element, the element can be directly above the other element or directly extend above the other element or there can also be intervening elements. In contrast, when an element is referred to as being "directly" above another element or "directly" extending above another element, there are no intervening elements. It should also be understood that when an element is referred to as being "connected" or "coupled" to another element, the element can be directly connected or coupled to the other element or there can be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0023] Relative terms, such as "beneath" or "above" or "over" or "under" or "horizontal" or "vertical", etc., may be used herein to describe the relationship of an element, layer, or region shown in the figures to another element, layer, or region. It should be understood that these terms, as well as the terms discussed above, are intended to cover different orientations of the device in addition to the orientation depicted in the figures.

[0024] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, unless the context clearly dictates otherwise, the singular forms "a", "an", and "the" are also intended to include the plural forms. It should be further understood that when used herein, the terms "comprises", "comprising", "includes", and / or "including" specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0025] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should be further understood that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and the relevant art, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0026] Aspects disclosed in the specific embodiments include multiple power management integrated circuits (PMICs) with shared outputs. More specifically, exemplary aspects of the present disclosure encompass two or more PMICs that are capable of generating a shared output while balancing the current provided by the PMICs without being affected by device and component mismatches and component-to-component variations. This balance is achieved by providing a current feedback loop and a shared voltage loop to each PMIC when multiple PMICs are active. When only a single PMIC is active, a switch disables the shared voltage feedback loop and enables a local voltage feedback loop. The use of multiple PMICs enables higher supply voltages to be provided to power amplifiers in a transmission chain to meet the requirements of emerging wireless standards while also maintaining better efficiency of the transmission chain.

[0027] Before describing exemplary aspects of the present disclosure, reference is made to Figure 1 A brief overview of existing multi-PMIC systems is provided along with a discussion of their shortcomings. Figure 2 A discussion of exemplary aspects of the disclosure begins.

[0028] In mobile terminals such as cellular phones, PMICs can typically provide output currents up to 1.5 amperes (A). However, with emerging phone architectures, higher currents may be required, such as 2.5 A or even 3.0 A. While it is possible to build a single PMIC capable of producing such higher currents, such a monolithic approach is impractical given current size constraints and current battery limitations in mobile terminals. Therefore, achieving such higher currents can be accomplished by combining the outputs from multiple PMICs.

[0029] In this regard, Figure 1 1 is a hybrid circuit and block diagram of a conventional multi-PMIC system 100. The multi-PMIC system 100 includes a first PMIC 102 and a second PMIC 104. Although the term PMIC is used throughout, it should be understood that the PMIC is in the form of a direct current (DC) to DC (DC-DC) converter. Exemplary DC-DC converters are buck converters, boost converters, buck-boost, and the like. The first PMIC 102 generates a first output current Iout1, which passes through a first effective series resistor (ESR1) 106 and is filtered by a first inductor (Lout1) 108 and a first capacitor (Cout1) 110 to provide a voltage at a first node 112. The first node 112 is coupled to an output node 114 via a first switch 116. The first node 112 is also coupled to the first PMIC 102 via a first voltage feedback loop 118.

[0030] Similarly, a second PMIC 104 generates a second output current Iout2 that passes through a second effective series resistance (ESR2) 120 and is filtered by a second inductor (Lout2) 122 and a second capacitor (Cout2) 124 to provide a voltage at a second node 126. The second node 126 is coupled to the output node 114 via a second switch 128. The second node 126 is also coupled to the second PMIC 104 via a second voltage feedback loop 130.

[0031] Currents from the first PMIC 102 and the second PMIC 104 combine at the output node 114 and can be provided to components such as a power amplifier that require higher currents than a typical single PMIC (i.e., given the size and battery limitations at the time) might otherwise be able to provide. However, process variations in the circuitry forming the PMICs 102, 104, tolerance variations in the ESR1 106, ESR2 120, Lout1 108, Lout2 122, Cout1 110, and / or Cout2 124 can all contribute to a significant current mismatch between the two current paths. When such a current mismatch exists, there may be additional strain on the PMICs, generating more current and inefficiencies within the system. Even when the currents match, it is still possible for all PMICs in a multi-PMIC system to draw current from a shared battery simultaneously. This peak in the current drawn from the battery can degrade performance or require worst-case engineering, which also increases inefficiencies.

[0032] Exemplary aspects of the present disclosure add independent current feedback loops to the current paths of multi-PMICs while providing a shared voltage feedback loop. The shared voltage feedback loop helps ensure that the desired supply voltage is generated at the output node, while the individual current feedback loops help regulate the current to compensate for mismatches in the current paths. Variations of this concept include turning on and off the voltage feedback loop for additional PMICs depending on whether the total current is being generated or only a single PMIC is being used. Another variation is to use a series circuit to manage which PMIC is drawing current from the battery at a given time to help prevent multiple PMICs from drawing peak current simultaneously.

[0033] In this regard, Figure 2Hybrid circuit and block diagram of a multi-PMIC system 200 having a shared output node 202 with balanced current, according to an exemplary aspect of the present disclosure. Specifically, the multi-PMIC system 200 includes a first PMIC 204 and a second PMIC 206. The first PMIC 204 provides an output signal that passes through a filter 208 formed by a first inductor (Lout1) 210 and a first capacitor (Cout1) 212 via a first switch 214 to the output node 202. A current detector 216 measures the current across the first inductor 210 to provide a first current feedback loop 218 for the first PMIC 204.

[0034] Similarly, the second PMIC 206 provides an output signal that passes through a second filter 220 formed by a second inductor (Lout2) 222 and a second capacitor (Cout2) 224 via a second switch 226 to the output node 202. A second current detector 228 measures the current across the second inductor 222 to provide a second current feedback loop 230 for the second PMIC 206. A single voltage measurement is made at node 232, which is a common voltage node relative to the output node 202 when switches 214 and 226 are closed. The measurement result from node 232 is fed back to both the first PMIC 204 and the second PMIC 206 as a common voltage feedback loop 234. This voltage feedback can be compared with a target voltage (Vtarget) to drive the PMICs 204, 206 to provide the desired output voltage. At the same time, the current feedback loop is used to balance the current loads between the two PMICs 204, 206.

[0035] Although not shown in Figure 2 and subsequent figures, it should be understood that filters 208 and 220 may include the ESR described above with reference to Figure 1 However, for simplicity, the ESR is omitted.

[0036] As might be expected, there are multiple ways to implement the loops. In this regard, Figure 3 is Figure 2 a more detailed schematic of the multi-PMIC system 200, where some switching paths and more details about the control circuit are presented, which helps prevent multiple current paths from drawing peak current simultaneously. Specifically, the control circuit 300 can be coupled to the PMICs 204 and 206 and the switches 214, 226, 302, and 304. Figure 2 The common voltage feedback loop 234 of

[0037] In a first mode controlled by control circuit 300, the first PMIC 204 can be used as an individual converter, and the second PMIC 206 can be turned off. Thus, control circuit 300 can drive switch 214 to output node (out1) 310. Switch 214 can be a single-pole double-throw (SPDT) switch. At the same time, switch 226 can be opened, so that the second PMIC 206 is decoupled from any output node. Similarly, switch 302 can be closed and switch 304 can be opened, so that the first voltage feedback loop 306 is decoupled from the second voltage feedback loop 308.

[0038] In a second mode controlled by control circuit 300, the second PMIC 206 can be used as an individual converter, and the first PMIC 204 can be turned off. Thus, control circuit 300 can drive switch 226 to output node (out2) 312. Switch 226 can also be an SPDT switch. At the same time, switch 214 can be opened, so that the first PMIC 204 is decoupled from any output nodes 202, 310, 312. Similarly, switch 302 can be closed and switch 304 can be opened, so that the second voltage feedback loop 308 is decoupled from the first voltage feedback loop 306.

[0039] In a third mode, and of more interest to the present disclosure, the PMICs 204, 206 can be combined to provide a combined output. Thus, control circuit 300 can drive both switches 214, 226 to output node 202. Switch 302 is opened and switch 304 is closed, so that the second voltage feedback loop 308 is deactivated, but both comparators 314 and 316 receive the same voltage signal from node 318. Comparators 314 and 316 compare the voltage signal from node 318 with the corresponding current signals and drive the PMICs accordingly.

[0040] Control circuit 300 also includes a series circuit 320 that works with state machines 322, 324 and a common clock signal 326. Series circuit 320 manipulates state machines 322, 324 so that only one of the PMICs 204, 206 draws current from the battery at a time. For example, the first PMIC 204 can draw current in even cycles, and the second PMIC 206 can draw current in odd cycles (or vice versa). A better illustration of this concept is provided below with reference to Figures 8A to 8C A preferred illustration of this concept is provided.

[0041] Although the above discussion has referred to these as multi-PMIC systems, the above figures only show two PMICs. It should be understood that the concepts of the present disclosure can be extended to more than two PMICs. In Figure 4One such system with more than two PMICs is shown by an orthogonal multi-PMIC system 400 having four PMICs 402(1) to 402(4). Each of the PMICs 402(1) to 402(4) has a corresponding filter 404(1) to 404(4), including corresponding inductors 406(1) to 406(4) and capacitors 408(1) to 408(4). Switches 410(1) to 410(4) couple the PMICs 402(1) to 402(4) to a common output node 412. Current detectors 414(1) to 414(4) are associated with the corresponding inductors 406(1) to 406(4), and provide current feedback loops 416(1) to 416(4), while a single voltage feedback loop 418 is shared by the PMICs 402(1) to 402(4). A control circuit 420 is used to control the switches 410(1) to 410(4) and various switches (not shown) that enable or disable various independent voltage feedback loops. Similarly, the control circuit 420 may also include a series circuit (not shown in Figure 4 ), which controls the activation of the PMICs 402(1) to 402(4) in a manner that avoids or minimizes the simultaneous draw on the battery.

[0042] Although Figure 3 the switching arrangement shown is an option, there are other possible switching arrangements for the multi-PMIC system 200. Accordingly, Figure 5 a more detailed diagram of the multi-PMIC system 200 with an alternative switching arrangement for sharing the voltage feedback loop is provided. Specifically, switches 302, 304 are combined into a single SPDT switch 500, which allows the input to the comparator 316 to come from either the voltage feedback loop 306 or the voltage feedback loop 308, as specified by the mode being used.

[0043] It should also be understood that the presence of the switches (whether they are switches 302, 304 or switch 500) can introduce a significant resistance in one branch of the common voltage feedback loop 234 that is not present in the other branch. Such additional resistance can create different values at the inputs of the comparators 314, 316, such that the comparators 314, 316 can no longer be considered to be using the same values to assist in balancing. While it is possible to create switches large enough to reduce the resistance to a non-significant level, this solution is impractical from a size and power consumption perspective. Another solution is to use mirrored dummy switches such that each branch of the common voltage feedback loop 234 has the same amount of resistance. In this regard, Figure 6FIG. 0 is a more detailed schematic of the multi-PMIC system 200 with dummy switches 600, 602, and 604. The dummy switches 600, 602 ensure that the current feedback loops 218, 230 have the same number of switches in place and are balanced with the switches in the voltage feedback loops 306, 308. Similarly, the switch 604 balances the switch 304. The use of the dummy switches 600, 602, 604 is one solution. Alternatively, resistors or the like can be used. Although there are some power and space costs associated with the dummy switches 600, 602, 604, using the dummy switches 600, 602, 604 saves space and power compared to a single larger low-resistance switch.

[0044] In the foregoing discussion, it has been assumed that there is a single clock that provides a single clock signal having a single frequency to both PMICs 204, 206. Using a single clock signal at a single frequency makes switching between the different PMICs 204, 206 relatively simple because the control circuit 300 only needs to consider one period.

[0045] However, there may be cases in a multi-PMIC system where different ones depend on different clock signals preferably shown in Figure 7 . Specifically, the state machine 322 receives the first clock signal 700, and the second state machine 324 receives the second clock signal 702. If the different clock signals are at the same frequency, then the series circuit 320 can still relatively easily arrange to prevent simultaneous current draw. This prevention is possible even when both PMICs 204, 206 are operating but not in total (as shown in Figure 7 ), in Figure 7 , the switch 214 couples the first PMIC 204 to the output node 310, and the switch 226 couples the second PMIC 206 to the output node 312. In this case, the switch 302 is closed and the switch 304 is open, allowing each PMIC 204, 206 to have its respective voltage feedback loop 306, 308.

[0046] Note that when the frequency of the first clock signal 700 (F1) is an integer multiple of the frequency of the second clock signal 702 (F2) (or vice versa), the series circuit 320 can also operate relatively efficiently. When such a proportional relationship (F1 = F2x or F2 = xF1) exists, the series circuit 320 can divide the draw on the battery by using the lower frequency and, for example, drawing in even cycles through the first PMIC 204 and in odd cycles through the second PMIC 206 (or vice versa).

[0047] Note that even when the frequencies are not proportional to each other, it is still possible to reduce the simultaneous draw on the battery. That is, the series circuit 320 can make the optimal fit sequence for switching multiple PMICs. Although there may still be a situation where two or more PMICs draw simultaneously on the battery, compared to the conventional multi-PMIC system 100, the overall number of such situations is reduced, thereby improving the overall efficiency, although not as good as when the frequencies are the same or proportional.

[0048] A more explicit description of how the series circuit 320 operates is provided in Figures 8A to 8C . Specifically, the multi-PMIC system 200 is coupled to a battery or voltage source (Vbatt) 800. The PMICs 204, 206 can draw from the voltage source 800 via a voltage source input node (not specifically labeled, but the node between the voltage source 800 and the PMICs 204, 206). In Figure 8A , the series circuit 320 controls the switches within the PMICs 204, 206 such that the first PMIC 204 draws current 802 from the voltage source 800. In contrast, the second PMIC 206 does not draw current (i.e., 804 (null)).

[0049] After some amount of time (e.g., the difference between even and odd cycles) shown in Figure 8B , the series circuit 320 instructs the switches within the PMICs 204, 206 such that the first PMIC 204 stops drawing current (i.e., 802 (null)), while the second PMIC 206 draws current 804 from the voltage source 800.

[0050] Figure 8C This concept is shown in a different way by graph 806, which shows that the current draws 802 and 804 operate oppositely within windows 810, 812 respectively. That is, current 802 is drawn within window 810, and current 804 is drawn within window 812.

[0051] It should be understood that there are multiple use cases for the multi-PMIC system 200 of the present disclosure. The multi-PMIC system 200 can be used to control power amplifiers used simultaneously by a single transmission, such as when using carrier aggregation (e.g., low band and high band), when using two different technologies (e.g., WIFI and Bluetooth), or the like.

[0052] Refer to Figure 9, the concepts described above can be implemented in various types of user elements 900, such as mobile terminals, smart watches, tablet computers, computers, navigation devices, access points, and similar wireless communication devices that support wireless communication, such as cellular, wireless local area network (WLAN), Bluetooth, and near field communication. The user element 900 will typically include a control system 902, a baseband processor 904, a transmission circuit system 906, a receiving circuit system 908, an antenna switching circuit system 910, a plurality of antennas 912, and a user interface circuit system 914. In a non-limiting example, by way of example, the control system 902 can be a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC). In this regard, the control system 902 can include at least a microprocessor, an embedded memory circuit, and a communication bus interface. The receiving circuit system 908 receives radio frequency signals from one or more base stations via the antenna 912 and via the antenna switching circuit system 910. The low noise amplifier and filter of the receiving circuit system 908 cooperate to amplify and remove broadband interference from the received signal for processing. A downconversion and digitization circuit system (not shown) then downconverts the filtered received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using an analog-to-digital converter (ADC).

[0053] The baseband processor 904 processes the digitized received signal to extract the information or data bits transmitted in the received signal. This processing typically includes demodulation, decoding, and error correction operations, as will be discussed in more detail below. The baseband processor 904 is typically implemented in one or more digital signal processors (DSPs) and ASICs.

[0054] For transmission, the baseband processor 904 receives digitized data from the control system 902 that represents voice, data, or control information encoded by the control system for transmission. The encoded data is output to the transmission circuit system 906, where a digital-to-analog converter (DAC) converts the digitally encoded data into an analog signal, and a modulator modulates the analog signal onto a carrier signal at one or more desired transmission frequencies. A power amplifier amplifies the modulated carrier signal to a level suitable for transmission and delivers the modulated carrier signal to the antenna 912 via the antenna switching circuit system 910 to the antenna 912. The plurality of antennas 912 and the replicated transmission and receiving circuit systems 906, 908 can provide spatial diversity. Those skilled in the art will understand the modulation and processing details.

[0055] It should also be noted that the operating steps described in any of the exemplary aspects herein are described to provide examples and discussion. The described operations may be performed in a number of different orders other than the order shown. In addition, the operations described in a single operating step may actually be performed in a number of different steps. Additionally, one or more of the operating steps discussed in the exemplary aspects may be combined. It should be understood that the operating steps shown in the flowcharts may be subject to many different modifications that will be apparent to those skilled in the art. Those skilled in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, the data, instructions, commands, information, signals, bits, symbols, and chips referred to in the foregoing detailed description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0056] The foregoing description of the disclosure has been provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A multi-power management integrated circuit (PMIC) (multi-PMIC) system, comprising: A first PMIC configured to receive a target voltage and generate a first output signal; A second PMIC configured to receive the target voltage and generate a second output signal; An output node coupled to the first PMIC and the second PMIC, and summing the first output signal and the second output signal to form a combined signal; A first current feedback loop configured to measure a first current of the first output signal and provide a first feedback signal to the first PMIC; A second current feedback loop configured to measure a second current of the second output signal and provide a second feedback signal to the second PMIC; And A common voltage feedback loop that couples the output node to the first PMIC and the second PMIC and is configured to provide voltage measurement results from the output node to the first PMIC and the second PMIC.

2. The multi-PMIC system according to claim 1, further comprising a first filter positioned in series between the first PMIC and the output node.

3. The multi-PMIC system according to claim 2, further comprising a first current detector in the first current feedback loop, the first current detector configured to measure the current across an inductor in the first filter.

4. The multi-PMIC system according to claim 1, further comprising a second voltage feedback loop that couples the output node to the second PMIC.

5. The multi-PMIC system according to claim 4, further comprising at least one switch positioned in the common voltage feedback loop and configured to couple the common voltage feedback loop to the second PMIC when the at least one switch is closed and isolate the second PMIC from the common voltage feedback loop when the at least one switch is open.

6. The multi-PMIC system according to claim 1, further comprising a control circuit coupled to the first PMIC and the second PMIC.

7. The multi-PMIC system according to claim 6, further comprising a voltage source input node coupled to the first PMIC and the second PMIC, wherein the control circuit is configured to prevent the first PMIC from drawing current from the voltage source input node while the second PMIC draws current from the voltage source input node.

8. The multi-PMIC system according to claim 1, further comprising a third PMIC and a fourth PMIC arranged orthogonally to the first PMIC and the second PMIC.

9. The multi-PMIC system according to claim 1, wherein the first PMIC and the second PMIC share a clock source.

10. The multi-PMIC system according to claim 1, wherein the first PMIC is configured to receive a first clock signal, and the second PMIC is configured to receive a separate second clock signal.

11. The multi-PMIC system according to claim 10, wherein the first clock signal has a frequency substantially the same as that of the second clock signal.

12. The multi-PMIC system according to claim 10, wherein the first clock signal has a first frequency that is an integer multiple of a second frequency of the second clock signal.

13. The multi-PMIC system according to claim 1, further comprising an output switch configured to couple the first PMIC to the output node or a second output node isolated from the second PMIC.

14. The multi-PMIC system according to claim 1, further comprising a comparator coupled to the first PMIC, wherein the comparator is configured to compare signals from the first current feedback loop and the common voltage feedback loop.

15. The multi-PMIC system according to claim 1, further comprising a dummy switch in the first current feedback loop.

16. The multi-PMIC system according to claim 15, further comprising a second dummy switch in the common voltage feedback loop.

17. A mobile communication device, comprising: a transceiver including a multi-power management integrated circuit (PMIC) (multi-PMIC) system, the multi-power management integrated circuit comprising: a first PMIC configured to receive a target voltage and generate a first output signal; a second PMIC configured to receive the target voltage and generate a second output signal; an output node coupled to the first PMIC and the second PMIC and summing the first output signal and the second output signal to form a combined signal; a first current feedback loop configured to measure a first current of the first output signal and provide a first feedback signal to the first PMIC; a second current feedback loop configured to measure a second current of the second output signal and provide a second feedback signal to the second PMIC; and a common voltage feedback loop coupling the output node to the first PMIC and the second PMIC and configured to provide a voltage measurement result from the output node to the first PMIC and the second PMIC.

18. The mobile communication device according to claim 17, wherein the multi-PMIC system further comprises a first filter positioned in series between the first PMIC and the output node.

19. The mobile communication device according to claim 18, wherein the multi-PMIC system further comprises a first current detector in the first current feedback loop, the first current detector being configured to measure a current across an inductor in the first filter.

20. A method of managing power in a power amplifier, comprising: Receive a target voltage at a first power management integrated circuit (PMIC) from a remote location; Generate a first output signal in response to receiving the target voltage; Receive the target voltage at a second PMIC; Generate a second output signal in response to receiving the target voltage; Sum the first output signal and the second output signal to form a combined signal; Measure a first current of the first output signal; Provide a first feedback signal to the first PMIC based on the first current; Measure a second current of the second output signal; Provide a second feedback signal to the second PMIC based on the second current; And Provide a voltage measurement result to the first PMIC and the second PMIC based on the combined signal.

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