Clock management unit

A clock management unit and clock terminal technology, applied in the direction of generating/distributing signals, etc., can solve problems such as timing violations, and achieve the effect of preventing timing violations and simplifying back-end design.

Inactive Publication Date: 2012-04-04
SAMSUNG SEMICON CHINA RES & DEV +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

If the release time of the reset signal supplied to the external circuit 20 is w

Method used

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Examples

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Embodiment Construction

[0021] Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings. However, the exemplary embodiments can be implemented in many different forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the exemplary embodiments to those skilled in the art. For clarity, the size and relative sizes of layers and regions are exaggerated in the drawings. In the drawings, the same reference numerals always refer to the same elements.

[0022] image 3 Is a block diagram showing the clock management unit 100 according to an exemplary embodiment.

[0023] The clock management unit 100 according to an exemplary embodiment may receive a clock signal CLK for driving external circuits such as various circuit modules in a chip. The reset signal RESETn that can reset the external circuit can be provided to the c...

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Abstract

The invention provides a clock management unit, which comprises a first trigger, a second trigger, a clock gate and an AND gate, wherein the first trigger comprises a first D terminal for receiving reset signals, a first clock terminal for receiving clock signals, and a first output terminal connected to a second D terminal of the second trigger; the second trigger comprises a second D terminal connected to a first output terminal of the first trigger, a second clock terminal for receiving clock signals and a second output terminal connected to an enable terminal of the clock gate; the clock gate comprises the enable terminal, a clock terminal for receiving clock signals, and an effective clock terminal connected to an external circuit; the clock gate provides the clock signals for the external circuit through the effective block terminal according to the output of the second output terminal of the second trigger; and the AND gate provides the reset signals for the first D terminal of the first trigger according to enable signals. Therefore, in at least two periods of the clock signals after the external circuit receives the reset signals, no clock signals are provided for the external circuit.

Description

Technical field [0001] The exemplary embodiment relates to a clock management unit, and more specifically, the exemplary embodiment relates to a clock management unit capable of maintaining an interval between a time when a reset signal is released and a time when a clock signal is supplied to an external circuit. Background technique [0002] In order to meet the requirements of the continuous enrichment of digital chip functions and continuous improvement of performance, the single-chip application processor integrates processor cores, rich multimedia modules and various peripheral equipment modules, so it usually integrates dozens of circuit modules, and its scale has reached Tens of millions of doors. Because many circuit modules in the chip use different clock sources, there are many circuit modules that reset asynchronously, which leads to the need to test whether there is a timing violation (timing violation) in the back-end design process, such as timing closure. violati...

Claims

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Application Information

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IPC IPC(8): G06F1/12
Inventor 胡伟聪
Owner SAMSUNG SEMICON CHINA RES & DEV
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