34 results about "Timing closure" patented technology

The invention discloses a time sequence convergence method and device based on a clock tree, and relates to the technical field of circuit design. The method comprises the following steps: performing automatic layout on devices; determining a time sequence path needing to be optimized in the one-to-many structure time sequence path; performing establishment time sequence margin optimization, and determining a setting pattern of useful clock skew adjustment based on the optimized establishment time sequence margin; determining the number of buffers based on the setting pattern of useful clock skew adjustment and the optimized setup time sequence margin, and generating a clock tree; on the basis of the generated clock tree, determining whether the time sequence violation of the retention time of the time sequence path needing to be optimized meets a preset requirement or not, and if the preset requirement is not met, adjusting the setting pattern of the useful clock skew adjustment, and returning to the step of generating the clock tree; and completing automatic wiring based on the clock tree meeting the predetermined requirement. According to the invention, the problem of power consumption increase caused by restoration of Hold time sequence violation can be solved.

The application relates to a message verification method and device, a chip, a storage medium and a program product. The method comprises the following steps: acquiring input data and an input data amount of a current clock beat corresponding to a target verification message; selecting N groups of mask numbers corresponding to a target storage value according to the input data amount of the current clock beat, the target storage value being a cyclic redundancy check value stored in a previous clock beat; performing operation on the N groups of mask numbers and the corresponding target storage value respectively to generate a first logic calculation value of the current clock beat; performing cyclic redundancy iteration operation on the input data of the current clock beat according to the first logic calculation value of the current clock beat to obtain a cyclic redundancy check value corresponding to the current clock beat; and obtaining a final cyclic redundancy check value according to the cyclic redundancy check value corresponding to the current clock beat. The method can reduce the timing convergence and chip wiring difficulty.

The invention discloses a time sequence driven macro module layout method, which comprises the following steps of: clustering standard units and macro modules in a circuit netlist to generate a clustering hierarchical tree; abstracting a leaf node cluster of the clustering hierarchical tree into a pseudo macro with a specific area and shape, and generating a global initial layout position of the pseudo macro; aiming at the interior of each cluster, constructing a virtual connection weight model, and solving a relative position relationship of macro modules in the cluster; the intra-cluster macro modules with the relative positions determined are regarded as macro groups, macro group position optimization is carried out, global macro layout is completed, key macro modules are screened out according to a time sequence analysis report, the key macro modules are classified and recognized as array macro or free macro, and position updating is carried out respectively; and then direction optimization is carried out, and a final macro-module layout result is output. According to the method, the layout problem of a large-scale mixed-size circuit can be effectively solved, the layout regularity is kept, meanwhile, the worst negative relaxation and the total negative relaxation are remarkably improved, and the timing convergence of physical design is improved.

The application provides a data transmission circuit and method based on signal conversion, a chip and an electronic device, and belongs to the field of circuits.The data transmission circuit based on signal conversion comprises a first conversion module and a second conversion module.The first conversion module is used for receiving a parallel signal from a first clock domain and converting the parallel signal into a serial signal of a second clock domain, wherein the frequency of the first clock domain is less than the frequency of the second clock domain.The second conversion module is used for receiving the serial signal and converting the serial signal into the parallel signal.The scheme realizes the transmission of the parallel signal from the first conversion module to the second conversion module within a first clock cycle.By applying the data transmission circuit based on signal conversion to transmit signals between FPGAs, a large number of signals can be transmitted from one FPGA to another FPGA within a clock cycle, thereby reducing the difficulty of circuit design and timing convergence.

The present application belongs to the technical field of low power consumption of integrated circuit design, and discloses a multi-threshold voltage unit distribution method, comprising the following steps: step 1: data preparation: obtaining a simplified path set according to a full high threshold circuit, and obtaining unit delay, timing increase / decrease factor and static power consumption value of the full high / low threshold circuit; step 2: distributing threshold according to the path set: distributing threshold point by point in the full high threshold circuit according to path weight and unit weight until the paths in the path set all meet timing requirements; and step 3: updating the path set: applying the threshold distribution result and performing static timing analysis, if the static timing analysis result does not meet timing, updating the path set and performing the threshold distribution operation according to the path set again until the static timing analysis result meets timing. The present application effectively reduces the method running time through the simplified path set, and ensures threshold distribution accuracy and timing convergence through updating the path set.

The invention discloses a system-on-chip (SOC) chip distributed debugging architecture and a method thereof. The debugging architecture comprises a debugging chain logic unit, and the debugging chain logic unit is integrated in each to-be-debugged module in an SOC chip; the debugging chain logic unit comprises a register beating module and a signal branching module; the register beating module is used for performing register beating processing on an input debugging signal; the signal branching module is used for dividing the debugging signal processed by the register beating module into a first-path debugging signal and a second-path debugging signal according to preset address information or mark information, the first-path debugging signal is used for internal debugging of the current to-be-debugged module, and the second-path debugging signal is used as debugging output; and enabling the debugging output of the current to-be-debugged module to be connected with the debugging access inlet of the next to-be-debugged module to form a continuous distributed debugging network. According to the method, the problems of resource occupation, difficulty in time sequence convergence, low debugging efficiency and the like in the chip debugging process are solved.

This application provides a timing control device, system, and method for frequency-scanning radar based on frequency synthesizer and digital logic modules. The frequency synthesizer module serves as the synchronization source and timing reference source for the operating modes of the frequency-scanning radar system. In terms of system hardware architecture, it achieves coherent synchronization between the RF sub-module and the digital logic module. At the RF end, the SYNC signal is used to broaden the pulses of each sub-module, thereby forming the gate signals for each module's corresponding operating mode, which are distributed only by the digital logic module. At the digital end, edge and pulse width detection of the SYNC and MODE signals triggers the sampling and digital signal processing timing. The entire system uses the signal generated by the frequency synthesizer module as the reference, achieving high precision and low phase noise while reducing the external RF cables of the digital logic module. It also achieves strong coupling between the RF and digital ends, which is beneficial for FPGA on-chip resource optimization and timing convergence, reducing design verification costs and subsequent expansion costs.

Systems and related methods for implementing fabric, i.e., correct timing convergence, may include a first semiconductor device providing a thin interface module on a base die, the thin interface module including: an address register mechanism for an address interconnect according to an address clock from an address clock interconnect; the data register mechanism is used for the data interconnects according to the data clocks from the data clock interconnects; and a plurality of bonding mechanisms for communicating with the second semiconductor device via the address interconnects and the data interconnects.

The invention discloses an AI-assisted time sequence report analysis method, and belongs to the technical field of integrated circuit design automation. The method comprises the following steps: acquiring a static time sequence analysis report; analyzing the report through an analysis rule base, and extracting structured information of a time sequence path; performing hierarchical grouping on the plurality of analyzed time sequence paths according to time sequence grouping, clock domains and violation types to generate time sequence statistical characteristics; and identifying a key path according to the time sequence statistical characteristics, and outputting a structured analysis result and an optimization suggestion. Through automatic analysis and intelligent analysis, the time sequence debugging efficiency is remarkably improved, dependence on experience of engineers is reduced, and the method is suitable for time sequence convergence scenes of large-scale integrated circuit design.

The invention discloses a method, a tool and a program product for optimizing time sequence consistency, and relates to the field of chip design. Reading time sequence data from the time sequence database of each stage; creating a violation path group corresponding to each stage based on the time sequence data; analyzing and calculating to obtain corresponding path adjustment parameters of each violation path group in different stages and time sequence difference conditions of the violation path groups in different stages; according to the time sequence difference condition, indicating to adjust the target stage or indicating to enter the next process; if the next process is indicated to be entered, sign-off verification is entered, and if the target stage is indicated to be adjusted, path adjustment parameters are set to run before implementation of the target stage. According to the method, the time sequence consistency and the critical path accuracy of each physical design stage are improved, judgment according to experience of designers is not needed, and the situation that constraints are too strict or too loose does not occur. The iteration speed and the time sequence convergence speed of physical design are well increased, and the automation capacity of the physical design process is improved.

The invention discloses an on-chip clock controller for testability design and an optimization method thereof, based on the thought that asynchronous logics have no time sequence relation and do not need time sequence check, selectors in OCC circuits fixedly select high-speed clock output paths, and a front-end selector is additionally arranged at the front end of each OCC circuit, so that the time sequence check is not needed. A path selection signal of a front-end selector is used for selectively inputting a high-speed function clock signal or a low-speed test clock signal, so that the low-speed test clock signal enters an OCC circuit and then is output through a high-speed clock output path of an internal selector, and therefore, an asynchronous clock domain relationship is kept between clocks output by different OCCs; therefore, the cross-domain time sequence check between different clock domains is not triggered, the time consumption of time sequence convergence iteration performed by the rear end due to the cross-domain time sequence check is saved, and the overall development period of the chip is shortened.

The invention discloses a method for introducing effective clock skew in a chip layout stage, which comprises the following steps of: utilizing an optimized time sequence of the effective clock skew to enable clock signals to arrive at a time sequence unit in a staggered manner, and offering surplus time sequence resources on a non-critical path to an adjacent critical path. According to the method, the effective clock skew is improved into an active optimization strategy in the early stage, and the degree of freedom and effectiveness of optimization are improved; a clear and quantitative optimization target is provided for the clock tree synthesis tool, so that the balance operation has clear time sequence guidance quality, and resource waste on a non-critical path is avoided; the problem of time sequence violation is solved by utilizing time sequence information earlier and more effectively, and higher working frequency is achieved; or the time sequence convergence is realized with lower power consumption, and the chip performance is improved; through effective clock skew, effective linkage of a layout wiring stage, a clock tree synthesis stage, a clock path and a data path is realized, a new normal form of a physical design stage is formed, and seamless connection of different design stages is realized.

This application relates to the field of integrated circuit clock tree optimization technology, and discloses a low-power clock tree optimization method and system for integrated circuit chips. The method includes: acquiring clock signal propagation delay data, extracting branch delay and edge jitter characteristics, and generating synchronization offset distribution characteristics; calculating the deviation peak value based on this, determining the clock buffer density adjustment range and insertion boundary, and generating a dynamic adjustment interval; based on this interval, combined with the clock tree depth and threshold voltage offset, determining the dynamic voltage adjustment target value through a voltage adjustment unit; updating the supply voltage, analyzing the impact of crosstalk between voltage domains on edge jitter and leakage current, and determining the power consumption distribution change trend; extracting the peak-to-peak value of edge jitter from the trend to complete synchronization verification, and determining the propagation delay fluctuation control configuration based on energy consumption data; updating the operating parameters accordingly, iteratively processing the delay distribution, and generating a load balancing optimization scheme. This application improves the timing convergence and power consumption controllability of the clock network.

A bonded multi-die integrated circuit module implements weight-stationary inference with accumulation confined within the module to eliminate emission of intermediate partial sums. The module comprises a compute die with an array of multiply-accumulate processing elements, a control-and-memory die that stages activations and partial sums proximate to the array and distributes activations via a hierarchical fanout network, and an interface die that couples to external memory and chiplet interconnects. The compute die operates in a high-frequency clock domain while other dies operate at lower frequencies with clock-domain crossings confined internally. During operation, weights are stored close to the array, activations are broadcast within the module, results are accumulated locally, and only completed sums egress to the external fabric, improving timing closure and reducing interconnect traffic for transformer inference workloads.

The invention relates to a message verification method and device, a chip, a storage medium and a program product. The method comprises the following steps: acquiring input data and input data volume of a current clock beat corresponding to a target verification message; according to the input data volume of the current clock beat, N groups of shielding numbers corresponding to a target register value are selected, and the target register value is a cyclic redundancy check value registered by the previous clock beat; respectively operating the N groups of shielding numbers and the corresponding target register values to generate a first logic calculation value of the current clock beat; performing cyclic redundancy iterative operation on the input data of the current clock beat according to the first logic calculation value of the current clock beat to obtain a cyclic redundancy check value corresponding to the current clock beat; and obtaining a final cyclic redundancy check according to the cyclic redundancy check value corresponding to the current clock beat. By adopting the method, time sequence convergence and chip wiring difficulty can be reduced.

The application discloses an on-chip clock controller for testability design and an optimization method thereof, based on the thought that there is no timing relationship between asynchronous logics and timing checking is not needed, a selector inside an OCC circuit is fixed to select a high-speed clock output path, a front-end selector is added in front of each OCC circuit, and a path selection signal of the front-end selector is used to select a high-speed function clock signal or a low-speed test clock signal, so that the low-speed test clock signal enters the OCC circuit and is output through the high-speed clock output path of the internal selector, so that the clocks output by different OCCs maintain an asynchronous clock domain relationship, so that cross-domain timing checking between different clock domains is not triggered, time consumption of timing convergence iteration performed at the back end due to the cross-domain timing checking is saved, and the overall development cycle of the chip is shortened.

The invention provides a time sequence optimization method and device, equipment and a storage medium, and the method comprises the steps: firstly obtaining a logic path length, a capture clock length and a transmitting clock length of a register associated with an interface in a first module for solving an interface time sequence convergence problem of the first module and a second module in a chip; and in combination with the clock skew distance between the two modules, determining the clock length of an input / output interface and the skew clock length, and further calculating and optimizing the input time delay information and the output time delay information of the second module in stages. The time sequence optimization is carried out by combining the time sequence characteristics of the register and the clock skew between the modules, the limitation of traditional unified constraint is avoided, the problem of interface time sequence convergence can be efficiently solved, and the physical implementation period of a super-large-scale digital chip is shortened.

The invention provides an on-chip test clock controller and an on-chip test clock control method, in an RTL design stage, a controllable first register and a controllable second register are arranged in the on-chip test clock controller, and in a scanning test stage, the on-chip test clock controller is connected with the first register and the second register. The automatic test vector generation tool can control the first clock gating device and the second clock gating device to be turned on or turned off by controlling the first register and the second register to output an enable signal or a disable signal; the first clock signal can be controlled to only pass through one time sequence path, the problem that time sequence convergence is difficult due to the fact that time sequence deviation between different time sequence paths is too large is solved, complex optimization depending on later physical design is avoided, the design period is remarkably shortened, and tool resource occupation and labor cost are reduced.

The application discloses a clock tree structure and an implementation method thereof, and relates to the technical field of clock trees.The clock tree structure comprises a trunk clock network and a branch clock network.The trunk clock network is introduced from outside and is composed of a first-stage buffer unit and a second-stage buffer unit.The trunk can be horizontal or vertical.The branch clock network is introduced from the trunk clock network and is composed of a second-stage buffer unit to a third-stage buffer unit.The branch clock drives the load in a window with an L*L size, that is, the third-stage buffer unit drives a fourth-stage buffer unit in a tree structure, and so on, to drive an nth-stage buffer unit and a gated clock unit.The beneficial effects are as follows: the clock tree structure is built by establishing the trunk clock network and the branch clock network, the number of buffer units on the clock network is reduced, and the chip power consumption is reduced;the main clock tree and the sub clock network play the role of a common path, the number of stages of the clock tree is reduced, the influence of OCV on the clock is reduced, and the final timing convergence is easy.

The application discloses an asynchronous sampling method and device based on FPGA, a storage medium and a system. The application compares real data with monitoring data continuously to obtain the phase position of a sampling clock edge relative to a real data bit, and adjusts the position of the clock edge in the data bit to an optimal sampling position in real time, so that the timing performance is improved, and the timing convergence pressure is reduced.

This application discloses a triggering system, an FPGA chip, and an oscilloscope, including a hysteresis comparator module, M inverting modules, a signal delay module, M carry chains, and a trigger signal generation module. The M carry chains are cascaded, with the carry output of the previous carry chain connected to the carry input of the next carry chain. The carry output of the last carry chain is connected to the signal delay module, which in turn is connected to the carry input of the first carry chain. Each carry chain's selection signal terminal corresponds to an inverting module and receives the inverted data word output by that module. Each carry chain performs bitwise combinational logic operations based on the data word received from the second data stream at its selection signal terminal, the data word received from the first data stream at its data input terminal, and the data word received from its carry input terminal, and outputs an N-bit data word to the trigger signal generation module. The system consumes minimal logic resources and is easy to place, route, and converge in timing.

The invention discloses a hypergraph optimization method and device, a medium and a product, and the method comprises the steps: obtaining a to-be-tested source code and a time sequence constraint file, converting the source code into a netlist file, carrying out the modeling to obtain a netlist model, and carrying out the static time sequence analysis to obtain a time sequence model; according to each time sequence parameter in the model, setting a time sequence weight value for each node and hyperedge in the netlist model; traversing the connection relationship of the net in the netlist file, counting the number of bottom unit loads driven by each net, obtaining a fan-out value of a hyperedge corresponding to the net in the netlist model, and setting a fan-out weight value for the hyperedge; classifying and merging nodes in the netlist model according to a preset resource constraint and a time sequence weight value to obtain a coarsened hypergraph model; according to the preset resource proportion, the fan-out weight value of the hyperedges and the hyperedges number of the nodes, the segmentation boundary is set, the optimized hypergraph is obtained, the reliability of hypergraph optimization is improved, and time sequence convergence of design after segmentation and back-end circuit layout and wiring are facilitated.

The invention relates to the technical field of integrated circuit testing, and discloses a LOC and LOS mode hybrid control circuit in an ATspeed test, and the circuit comprises a function switching control module, the first input end of which is used for receiving an external scanning enable signal, and the output end of which is used for outputting an internal scanning enable signal to a to-be-tested scanning trigger; the mode control input end is used for receiving a mode control signal; the function switching control module is used for responding to a mode control signal to indicate a first state, and outputting a first control waveform generated based on an external scanning enable signal as an internal scanning enable signal, so that the to-be-tested scanning trigger works in an LOC mode; the function switching control module is also used for responding to the mode control signal to indicate a second state, and outputting a second control waveform generated based on the external scanning enable signal as an internal scanning enable signal, so that the to-be-tested scanning trigger works in an LOS mode; wherein the first control waveform is different from the second control waveform. The problem that the fault detection rate and the time sequence convergence are difficult to balance is solved.

Embodiments of the present application provide a system on chip, a circuit control method and device, which can be applied to artificial intelligence and other scenarios. The system on chip includes a reset control unit and at least one intellectual property (IP) unit. Each IP unit includes a reset synchronization circuit and a clock gating circuit. The reset control unit is configured to generate a reset signal for each IP unit. The reset synchronization circuit is configured to synchronize the reset signal according to a clock signal of each IP unit, to obtain a synchronized reset signal. The synchronized reset signal is used to reset at least one circuit unit included in each IP unit. The reset control unit is further configured to generate a gating signal for each IP unit according to the synchronized reset signal of each IP unit. The gating signal is used to control the clock gating circuit included in each IP unit to enable or disable the clock signal of each IP unit. The design of the reset circuit can be effectively simplified, and the timing convergence of the reset signal can be ensured.

The application relates to the chip technical field and provides a clock control path timing optimization method, equipment, medium and program product.The method comprises the following steps: according to the physical size and target frequency of a target circuit module, a plurality of registers are inserted on the clock control path of the target circuit module to construct a pipeline chain; the last-stage register of the pipeline chain is fixed at a target position; a clock network is constructed under the premise of maintaining the position of the last-stage register fixed, and in the process of constructing the clock network, timing constraints between clock gate units controlled by the last-stage register are shielded; after the clock network is constructed, physical connection between the clock gate units and the last-stage register is established, and timing optimization is performed on the clock control path between the last-stage register and the clock gate units.The application avoids power consumption surge, wiring congestion and violation risks caused by excessively long paths, and significantly improves the timing convergence rate and resource utilization rate of a high-performance chip in a sign-in stage.

The invention provides a circuit global layout-based time sequence optimization method, which comprises the following steps of: S1, giving a layout area and a group of immovable units and movable units to be laid out, and directly laying out the immovable units at fixed positions of the immovable units; for the movable units, performing unit layout based on an electrostatic density model; s2, time sequence evaluation; performing static time sequence analysis on the whole circuit arranged in the step S1 through a delay model based on a virtual buffer; s3, optimizing a time sequence; performing layout reconstruction of time sequence driving, optimizing the time sequence performance of the circuit through a line network weighting algorithm based on a virtual path, and eliminating gradient deviation through gradient preprocessing of time sequence perception so as to accelerate time sequence convergence; and S4, generating a legalization result by using an Abacus algorithm after time sequence convergence, otherwise, returning to the step S1. According to the method, the problem that the optimization result cannot meet the expected requirement due to the fact that the weight is only distributed to the wire network of the key part is effectively solved.

The invention relates to the technical field of integrated circuit design, in particular to a circuit glitch optimization method and device based on static time sequence analysis, electronic equipment and a storage medium. According to the circuit glitch optimization method based on static time sequence analysis, data path time delay is directly analyzed and balanced based on static time sequence analysis; on the premise that time sequence convergence is maintained, multi-channel time delay of an input node of the same device is accurately balanced, competition conditions can be effectively restrained, the occurrence probability and amplitude of burrs are reduced from the source, and therefore dynamic power consumption caused by the occurrence probability and amplitude of the burrs is reduced; furthermore, by embedding a physical design and sign-off tool chain, data conversion and transmission among multiple tools are avoided, the process is remarkably simplified, the error risk is reduced, the optimization period is shortened, optimization can be dynamically implemented according to the design stage, and the efficiency and reliability of chip design are integrally improved.

This application relates to a method, apparatus, and device for determining timing convergence risks of module interfaces in a chip. The method includes: acquiring interface timing information of module interfaces within each module of the chip, a top-level netlist of the chip, and an empty netlist for each module, wherein the empty netlist contains module interface pin information but has no internal logic; determining the interface timing information of module interfaces at both ends of a target transmission path based on the top-level netlist, the empty netlist, and the interface timing information of the module interfaces within each module; determining the interface timing information corresponding to the target transmission path based on the interface timing information of the module interfaces at both ends of the target transmission path; and determining whether there is a timing convergence risk at the module interfaces at both ends of the target transmission path based on the interface timing information corresponding to the target transmission path. This method can improve the efficiency of timing checks between chip modules.

A timing-driven clock tree synthesis method and product based on key node pairs, the timing-driven clock tree synthesis method comprising: constructing an initial clock tree; extracting multiple register transfer paths satisfying a margin requirement based on the initial clock tree; constructing a key node pair file according to the multiple register transfer paths; and generating a start node mapping table and a termination node mapping table according to the key node pair file; dividing multiple node clusters in the initial clock tree into non-key node clusters and key node clusters based on the start node mapping table and the termination node mapping table; and processing the non-key node clusters and the key node clusters in the initial clock tree respectively to obtain a final optimized clock tree. The timing-driven clock tree synthesis method aims to ensure timing convergence while constructing a timing-driven balanced clock tree.

The application relates to the chip technical field, in particular to a low-power-consumption asynchronous handshake circuit with a test circuit, which comprises a clock control circuit, a third selector, a first flip-flop, a second flip-flop, a third flip-flop, an AND gate and an OR gate; the function of the low-power-consumption asynchronous handshake circuit is realized in a function mode, and the low-power-consumption asynchronous handshake circuit is tested in a test mode. The application reduces the power consumption of the asynchronous handshake circuit and improves the timing convergence speed of the asynchronous handshake circuit under the premise of meeting the asynchronous handshake circuit test.