94 results about "Timing closure" patented technology

The invention discloses a time sequence convergence method and device based on a clock tree, and relates to the technical field of circuit design. The method comprises the following steps: performing automatic layout on devices; determining a time sequence path needing to be optimized in the one-to-many structure time sequence path; performing establishment time sequence margin optimization, and determining a setting pattern of useful clock skew adjustment based on the optimized establishment time sequence margin; determining the number of buffers based on the setting pattern of useful clock skew adjustment and the optimized setup time sequence margin, and generating a clock tree; on the basis of the generated clock tree, determining whether the time sequence violation of the retention time of the time sequence path needing to be optimized meets a preset requirement or not, and if the preset requirement is not met, adjusting the setting pattern of the useful clock skew adjustment, and returning to the step of generating the clock tree; and completing automatic wiring based on the clock tree meeting the predetermined requirement. According to the invention, the problem of power consumption increase caused by restoration of Hold time sequence violation can be solved.

The invention relates to a logic comprehensive stage delay prediction method and system based on machine learning, and belongs to the technical field of digital integrated circuit design automation. According to the method, a concept in the field of natural language processing is used for reference, a time sequence path is analogous to a sentence in a natural language processing task, and a basic element forming the sentence is called token. One time sequence path is formed by connecting a plurality of standard units and a wire net, and each token forming one time sequence path contains both the information of the standard units and the information of the wire net. The method comprises the following steps: firstly, predicting the physical size of a line network in a time sequence path by using a graph attention network, and then capturing the time sequence correlation and physical correlation of each part of the whole time sequence path by using an LSTM-Attention network. According to the method, the time sequence performance after wiring is accurately and efficiently fed forward to the logic synthesis process, so that time sequence optimization and time sequence convergence in the logic synthesis stage are guided, and the number of iterations of chip design is greatly reduced.

The invention provides a time sequence analysis method based on integrated circuit post-simulation, electronic equipment and a storage medium, and relates to the technical field of chip design. The method comprises the following steps: constructing an equivalent STA environment according to a post-simulation verification environment corresponding to a to-be-post-simulated module in a target integrated circuit; based on the STA environment, checking whether the interface signal delay of the to-be-simulated module conforms to a preset interface time sequence constraint or not; if not, performing time sequence repair on the interface through a virtual time sequence engineering change list so as to converge the interface time sequence; the method comprises the following steps: configuring a module to be subjected to post-simulation as an STA environment of top design, and outputting a target standard delay format file SDF when determining that an internal path of the module to be subjected to post-simulation meets a preset time sequence requirement, so that the STA environment equivalent to a post-simulation verification environment is constructed; according to the method, the interface time sequence violation of the module to be subjected to post-simulation in the post-simulation environment can be reproduced and repaired, the target SDF is generated for post-simulation, the post-simulation time is saved, and convergence of the verification time sequence of the post-simulation module is accelerated.

The invention relates to the technical field of chips, and provides a time sequence optimization method and device for a clock control path, a medium and a program product, and the method comprises the steps: inserting a multi-stage register on the clock control path of a target circuit module according to the physical size and target frequency of the target circuit module, and constructing to obtain an assembly line chain; fixing a last-stage register of the assembly line chain at a target position; constructing a clock network on the premise of keeping the position of the last-stage register fixed, and in the process of constructing the clock network, shielding a time sequence constraint from the last-stage register to a clock gating unit controlled by the last-stage register; and after the clock network is constructed, physical connection between the clock gating unit and the last-stage register is established, and time sequence optimization is performed on a clock control path between the last-stage register and the clock gating unit. According to the method, power consumption surge, wiring congestion and violation risks caused by an overlong path are avoided, and the time sequence convergence rate and the resource utilization rate of the high-performance chip in the sign-off stage are remarkably improved.

The invention belongs to the field of digital integrated chips, particularly relates to a clock tree generation and optimization method for quickly realizing time sequence convergence, and aims to solve the problems that an existing clock tree does not completely optimize a time sequence violation path and is difficult to realize quick time sequence convergence. The method comprises the following steps: carrying out logic synthesis on RTL codes to obtain a time sequence convergence netlist after logic synthesis; performing chip layout planning and hardware unit placement based on the time sequence convergence netlist; performing clock tree generation and clock tree comprehensive optimization on the chip with the hardware unit to obtain to-be-wired chip data with time sequence convergence; and based on the to-be-wired chip data, wiring of the to-be-wired chip is carried out according to preset parameters, and static time sequence analysis is carried out. According to the method, the frequency index of the chip is effectively optimized by combining an EDA tool, manually adjusting the clock tree structure and guiding the file, the number of iterations in the clock tree generation process and the time sequence optimization process after the clock tree generation process can be reduced, and the method is effective, reliable, convenient and practical.

A unified timing closure system for the simultaneous synthesis of multi-mode clock trees in a system-on-chip architecture, comprising: a timing convergence processor configured to perform simultaneous analysis and optimization of clock distribution paths across a variety of operating modes and process voltage-temperature operating conditions, wherein the timing convergence processor maintains a unified timing graph that correlates all clock sinks with multiple mode vectors representing setup and hold relationships under different conditions; a multitude of distributed computer scaling units distributed across physically distinct sub-areas of the system-on-chip architecture, each distributed computer scaling unit being configured to determine local delay scaling factors corresponding to process variations, voltage fluctuations, and temperature gradients in its respective sub-area, and dynamically adjust the delay buffer characteristics, link impedance, and driver strength in response to the local scaling factors; a clock offset synchronization unit coupled with the timing convergence processor and the numerous distributed clock scaling units, wherein the clock offset synchronization unit is configured to monitor and minimize insertion delay differences between multiple clock sinks by dynamically adjusting capacitive loads and buffer driver strengths throughout the clock network to maintain uniform propagation characteristics across all modes; a multi-mode synchronization processor that is operationally linked to the timing convergence processor and is configured to harmonize clock arrival times across the operating modes of function, test, and power saving by mapping all mode-specific constraints into a unified timing domain, and to correct inter-mode skew divergence by iteratively adjusting clock path latencies; a distributed timing communication interface that establishes a hierarchical interconnection network between the timing convergence processor and the multiple distributed corner scaling units, wherein the distributed timing communication interface is configured to exchange real-time timing information, delay deviation metrics, and control instructions via a synchronized token-based communication protocol; and A physical time-matching circuit consisting of tunable delay lines, programmable capacitive elements and temperature-compensated bias transistors, physically embedded in the clock distribution network, wherein the physical time-matching circuit receives adaptive control signals from the time convergence processor and adjusts local propagation characteristics to achieve time completion simultaneously across all operating modes and process boundaries.

The invention discloses a method and a system for checking a time sequence path based on logic depth splitting. The method comprises the following steps: acquiring the logic depth of the time sequence path; splitting the logic depth to obtain a buffer and inverter level and a register transfer level (RTL) level; based on the logic depth, a buffer and inverter level, and a register transfer level (RTL) level, a timing problem source is located. According to the time sequence path inspection method and system provided by the invention, the logic depth is divided into the buffer and inverter level and the RTL level, and the source of the time sequence problem is accurately positioned, so that the time sequence convergence efficiency is improved, and the chip design complexity is reduced.

The invention provides a logic synthesis optimization method and device, electronic equipment and a computer storage medium, and belongs to the technical field of EDA, and the logic synthesis optimization method comprises the steps: determining a target module included in an optimization strategy based on a time sequence report generated in a logic synthesis process; in the optimization strategy, a register retiming function and a register optimization function of the target module are enabled, so that the electronic design automation tool allows the registers between the modules to be moved when optimizing the target module; and based on the optimization strategy, executing logic synthesis on the to-be-synthesized design. A key bottleneck module influencing time sequence convergence can be optimized in a targeted manner in a logic synthesis process.

The invention relates to a system and a method applied to real-time circulating storage of a high-speed data acquisition system, which are mainly used for solving the technical problems of huge fan-out quantity of a core clock, more cross clock domains and lack of accurate description of sampling data trigger time information in the prior art when the use amount of core clock resources is reduced. The device comprises a control logic unit, a first buffer, a second buffer, a memory, a time measurement unit and at least one clock manager, a double-cache structure of a small-capacity first cache and a large-capacity second cache is adopted, only one clock manager is needed at least, and the problem that a time sequence is not converged in time information of a high-speed sampling data waveform is solved. The double-cache structure can reduce the stored core clock resource quantity, the distributed clock domain and the like as much as possible, time sequence convergence with high robustness is realized, and stable and reliable sampling data storage is ensured.

Apparatus and methods for constructing Network on Chips (NoCs) by algorithmically elaborating one or more of Network on Chips (NoCs) through a hierarchical topology composed of instantiations of sub-NoCs and leaf components, and one or more connectivity definitions. Designing NoCs using one or more instantiations of sub-NoCs reduces overheads during chip backend processes, such as for timing closure.

The present invention relates to a configurable logic system (101) programmed to model a logic design for data pipeline between master and slave; and the method of implementation, wherein said system (101) comprises of at least one first register (112) configured to store and transfer at least one data from said master to said slave; wherein said system (101) is configured to operate on one clock and one reset. The system (101) further comprises of at least one first control logic (118) that controls said first register (112) and fourth register (109) to provide hold to the ready signal from the slave to ease timing closure at high speed.

The application relates to the field of semiconductor counting statistics, and discloses a DDR memory counting statistics method, equipment and a storage medium. The method comprises the following steps: when a counting request is received; performing polling allocation combination processing on a counting statistics ID and a counting request value to generate an allocation array; querying a memory statistics value corresponding to the counting statistics ID from a preset DDR memory; accumulating the memory statistics value and the counting request value to generate a new memory statistics value, and writing the new memory statistics value into the DDR memory; when a reading statistics request is received; querying all statistics values corresponding to the reading statistics ID from the DDR memory according to a reading statistics ID to generate a statistics value set, wherein the reading statistics ID is used to poll a Block counter value in a Block counter value set; and calculating a statistics output value corresponding to the reading statistics request based on the statistics value set. In the embodiment of the application, the characteristics of the DDR address are used for addition and subtraction of statistics values, a complex Cache mechanism is not needed, and the logical complexity and timing convergence difficulty are reduced.

The application relates to a message verification method and device, a chip, a storage medium and a program product. The method comprises the following steps: acquiring input data and an input data amount of a current clock beat corresponding to a target verification message; selecting N groups of mask numbers corresponding to a target storage value according to the input data amount of the current clock beat, the target storage value being a cyclic redundancy check value stored in a previous clock beat; performing operation on the N groups of mask numbers and the corresponding target storage value respectively to generate a first logic calculation value of the current clock beat; performing cyclic redundancy iteration operation on the input data of the current clock beat according to the first logic calculation value of the current clock beat to obtain a cyclic redundancy check value corresponding to the current clock beat; and obtaining a final cyclic redundancy check value according to the cyclic redundancy check value corresponding to the current clock beat. The method can reduce the timing convergence and chip wiring difficulty.

In an embodiment of the present disclosure, a timing optimization method is provided, comprising: performing static timing analysis on the integrated circuit and obtaining a path to be processed in the integrated circuit; determining a network to be processed based on the path to be processed, wherein the network to be processed includes a network appearing on the path to be processed; isolating the load in each network to be processed, wherein the load isolation includes classifying the load in the network to be processed, wherein the classification results include critical loads and non-critical loads, and adding buffer units around the non-critical loads; and the load classification includes trying different load marking schemes, estimating the delay variation of each marking result, and selecting the best scheme to classify the loads. The processing scheme disclosed in the present disclosure can improve the efficiency of timing convergence on critical paths.

The invention discloses a time sequence driven macro module layout method, which comprises the following steps of: clustering standard units and macro modules in a circuit netlist to generate a clustering hierarchical tree; abstracting a leaf node cluster of the clustering hierarchical tree into a pseudo macro with a specific area and shape, and generating a global initial layout position of the pseudo macro; aiming at the interior of each cluster, constructing a virtual connection weight model, and solving a relative position relationship of macro modules in the cluster; the intra-cluster macro modules with the relative positions determined are regarded as macro groups, macro group position optimization is carried out, global macro layout is completed, key macro modules are screened out according to a time sequence analysis report, the key macro modules are classified and recognized as array macro or free macro, and position updating is carried out respectively; and then direction optimization is carried out, and a final macro-module layout result is output. According to the method, the layout problem of a large-scale mixed-size circuit can be effectively solved, the layout regularity is kept, meanwhile, the worst negative relaxation and the total negative relaxation are remarkably improved, and the timing convergence of physical design is improved.

Embodiments of the present disclosure relate to design tools for automatic placement constraint generation, adapter insertion procedures, and local and global congestion capture. A tool is disclosed that automatically generates constraints for placement of network elements, which can be understood by back-end tools that follow the constraints. The tool also constrains placement within a given range, resulting in faster runtime of the back-end tool. In addition, the tool automatically inserts additional elements into the topology to facilitate timed shutdown in downstream or back-end tools. In addition, the tool provides real-time feedback to the user regarding line congestion during editing. The tool also implements a machine-learned model that is trained and receives feedback for the provided solution to further train the model. The tool also includes the ability to use feedback to train a machine learning model for automatic and auxiliary topology analysis and synthesis. The tool generates a physical implementation boot during the physical implementation of the synthetic NoC.

The application provides a data transmission circuit and method based on signal conversion, a chip and an electronic device, and belongs to the field of circuits.The data transmission circuit based on signal conversion comprises a first conversion module and a second conversion module.The first conversion module is used for receiving a parallel signal from a first clock domain and converting the parallel signal into a serial signal of a second clock domain, wherein the frequency of the first clock domain is less than the frequency of the second clock domain.The second conversion module is used for receiving the serial signal and converting the serial signal into the parallel signal.The scheme realizes the transmission of the parallel signal from the first conversion module to the second conversion module within a first clock cycle.By applying the data transmission circuit based on signal conversion to transmit signals between FPGAs, a large number of signals can be transmitted from one FPGA to another FPGA within a clock cycle, thereby reducing the difficulty of circuit design and timing convergence.

The invention provides a layout and wiring method and device, electronic equipment and a storage medium, and the method comprises the steps: obtaining the working frequencies of a plurality of module regions on a target chip according to a chip netlist file, determining a first module region from the plurality of module regions according to the working frequencies, increasing the congestion degree of a logic unit in the first module region, and obtaining a second module region from the first module region; and updating the chip netlist file so as to carry out chip layout. The congestion degree of the logic units in the first module area is increased before layout, chip area resources are saved, the conditions of insufficient routing resources and crosstalk are avoided, and therefore the time sequence convergence requirement is met.

The application aims to provide a method for reducing the timing influence of metal dummy based on metal dummy blockage, which comprises the following steps: obtaining chip parameters and metal density requirements; performing metal filling according to the chip parameters and the metal density requirements; and verifying whether the filled chip meets the specifications. The application avoids the influence of metal dummy on the paths by using dummy blockage to avoid adding metal dummy at these places, without changing the timing of the paths, so as to reduce the iteration number of timing convergence and make the timing convergence more controllable.

The present application belongs to the technical field of low power consumption of integrated circuit design, and discloses a multi-threshold voltage unit distribution method, comprising the following steps: step 1: data preparation: obtaining a simplified path set according to a full high threshold circuit, and obtaining unit delay, timing increase / decrease factor and static power consumption value of the full high / low threshold circuit; step 2: distributing threshold according to the path set: distributing threshold point by point in the full high threshold circuit according to path weight and unit weight until the paths in the path set all meet timing requirements; and step 3: updating the path set: applying the threshold distribution result and performing static timing analysis, if the static timing analysis result does not meet timing, updating the path set and performing the threshold distribution operation according to the path set again until the static timing analysis result meets timing. The present application effectively reduces the method running time through the simplified path set, and ensures threshold distribution accuracy and timing convergence through updating the path set.

The present invention discloses a physical construction method suitable for meeting triple modular redundancy. In the layout stage, a customized design is adopted for the clock management unit. The three registers in the same group are effectively controlled through scripts during implementation. Since the existing triple modular registers increase the clock delay and have the characteristic of large delay differences under different process corners in advanced processes, the difficulty of timing convergence is reduced, and the design efficiency is effectively accelerated. Finally, the triple modular clock phase difference check is completed by using the clock length comparison method. The present invention can ensure that the single event effect is effectively improved while ensuring that the triple modular design quickly meets the design specifications. The present invention has the advantages of simple process, strong operability, and fast timing convergence speed, and can meet other tape-out sign-off conditions.

The invention discloses a system-on-chip (SOC) chip distributed debugging architecture and a method thereof. The debugging architecture comprises a debugging chain logic unit, and the debugging chain logic unit is integrated in each to-be-debugged module in an SOC chip; the debugging chain logic unit comprises a register beating module and a signal branching module; the register beating module is used for performing register beating processing on an input debugging signal; the signal branching module is used for dividing the debugging signal processed by the register beating module into a first-path debugging signal and a second-path debugging signal according to preset address information or mark information, the first-path debugging signal is used for internal debugging of the current to-be-debugged module, and the second-path debugging signal is used as debugging output; and enabling the debugging output of the current to-be-debugged module to be connected with the debugging access inlet of the next to-be-debugged module to form a continuous distributed debugging network. According to the method, the problems of resource occupation, difficulty in time sequence convergence, low debugging efficiency and the like in the chip debugging process are solved.

This application provides a timing control device, system, and method for frequency-scanning radar based on frequency synthesizer and digital logic modules. The frequency synthesizer module serves as the synchronization source and timing reference source for the operating modes of the frequency-scanning radar system. In terms of system hardware architecture, it achieves coherent synchronization between the RF sub-module and the digital logic module. At the RF end, the SYNC signal is used to broaden the pulses of each sub-module, thereby forming the gate signals for each module's corresponding operating mode, which are distributed only by the digital logic module. At the digital end, edge and pulse width detection of the SYNC and MODE signals triggers the sampling and digital signal processing timing. The entire system uses the signal generated by the frequency synthesizer module as the reference, achieving high precision and low phase noise while reducing the external RF cables of the digital logic module. It also achieves strong coupling between the RF and digital ends, which is beneficial for FPGA on-chip resource optimization and timing convergence, reducing design verification costs and subsequent expansion costs.

The application discloses a kind of chip synchronous clock between circuit jump fault test method, in chip synchronous clock test circuit, pulse_ctrl module is connected behind PLL output clock, the pulse_ctrl module generates internal clock and reset;Including divider module, the divider module includes frequency division circuit, to generate frequency division clock;Still including syn_occ module, the syn_occ module controls the pulse output of frequency division clock;Pulse_ctrl module outputs clock_out as the reference clock of chip frequency division circuit;When fault test, the output signal div_rstn of pulse_ctrl module controls the reset end rstn of frequency division circuit, and participates in the test clock generation of sync_occ module.The application realizes the test of synchronous clock between circuit jump fault, and the clock path under test mode and the clock path under chip function mode are completely identical, the circuit area and timing convergence overhead of test logic are reduced, and the test coverage of circuit fault is improved.

Systems and related methods for implementing fabric, i.e., correct timing convergence, may include a first semiconductor device providing a thin interface module on a base die, the thin interface module including: an address register mechanism for an address interconnect according to an address clock from an address clock interconnect; the data register mechanism is used for the data interconnects according to the data clocks from the data clock interconnects; and a plurality of bonding mechanisms for communicating with the second semiconductor device via the address interconnects and the data interconnects.

The application discloses a method and system for checking a timing path based on logical depth splitting, and the method comprises the following steps: acquiring a logical depth of a timing path; splitting the logical depth to obtain a buffer and inverter level and a register transfer level (RTL) level; and locating a timing problem source based on the logical depth, the buffer and inverter level and the RTL level. The timing path checking method and system provided by the application can locate the timing problem source accurately by splitting the logical depth into the buffer and inverter level and the RTL level, thereby improving timing convergence efficiency and reducing chip design complexity.

The invention discloses a generation method, device and system suitable for a hybrid-driven multi-bit trigger. The generation method comprises the following steps: acquiring all single triggers in a digital chip of which the initial layout design is completed; mapping each single trigger into a ternary trigger vector comprising a transistor size, a threshold voltage and a number, and generating a trigger matrix; splitting the trigger matrix into a plurality of independent sub-matrixes according to the clustering result of the single trigger, wherein each sub-matrix corresponds to one multi-bit trigger; repeating the following steps until the Pareto front is stable and meets a preset layout legalization verification condition to obtain a multi-bit trigger: by taking the normalized total negative margin and power consumption minimization as optimization objectives, optimizing each sub-matrix by adopting a proxy auxiliary differential evolution algorithm and a non-dominated sorting evolution algorithm to obtain a Pareto optimal solution set; and if the multi-bit trigger corresponding to the Pareto optimal solution set does not meet the layout legalization verification condition, re-dividing the trigger matrix. The clock network power consumption can be reduced, and the time sequence convergence rate is improved.

The present invention discloses a method, system, medium and product for automatically correcting hold time violations in chip design. The method includes calculating the ratio between the setup time margin and the absolute value of the hold time violation value for the endpoint pin of the timing path of the hold time violation in the chip design, and selecting different insertion points to insert a delay unit or a buffer unit based on whether the ratio is greater than a preset value K; then completing a hold time violation correction, and then detecting and reporting whether there are still timing paths with hold time violations. If there are, repeating the above process until all hold time violation paths in the design are repaired. The present invention aims to realize the automated correction of hold time violations in chip design, to make up for the deficiency of existing engineering renovation tools that can only automatically repair hold time violations with sufficient setup time margin at the endpoint of the timing path, and to automatically and efficiently repair various hold time violations with sufficient and insufficient setup time margins, so that the chip design can achieve the purpose of timing convergence as soon as possible.

The invention discloses an AI-assisted time sequence report analysis method, and belongs to the technical field of integrated circuit design automation. The method comprises the following steps: acquiring a static time sequence analysis report; analyzing the report through an analysis rule base, and extracting structured information of a time sequence path; performing hierarchical grouping on the plurality of analyzed time sequence paths according to time sequence grouping, clock domains and violation types to generate time sequence statistical characteristics; and identifying a key path according to the time sequence statistical characteristics, and outputting a structured analysis result and an optimization suggestion. Through automatic analysis and intelligent analysis, the time sequence debugging efficiency is remarkably improved, dependence on experience of engineers is reduced, and the method is suitable for time sequence convergence scenes of large-scale integrated circuit design.

The present invention proposes an out-of-order speculative execution emission queue and electronic device, comprising a write buffer, an overflow area, a main entry area, and a first selector. The write buffer, overflow area, and main entry area are all connected to the first selector, and the write buffer and overflow area are all connected to the main entry area, and the write buffer is also connected to the overflow area. After providing a first type of instruction to the first selector, or when the first direct transmission condition is not met, if the number of valid instructions remaining in the write buffer is greater than or equal to 1, the write buffer is used to send the valid instructions therein to the overflow area and / or the main entry area according to a preset priority rule. The emission queue is divided into three areas: the write buffer, the overflow area, and the main entry area. Each area only needs to find the corresponding instruction as output according to the instruction age, which greatly reduces the logical depth of the entire emission queue age matrix, thereby reducing the difficulty of timing convergence of the emission queue.