67 results about "Timing closure" patented technology

The invention discloses a time sequence convergence method and device based on a clock tree, and relates to the technical field of circuit design. The method comprises the following steps: performing automatic layout on devices; determining a time sequence path needing to be optimized in the one-to-many structure time sequence path; performing establishment time sequence margin optimization, and determining a setting pattern of useful clock skew adjustment based on the optimized establishment time sequence margin; determining the number of buffers based on the setting pattern of useful clock skew adjustment and the optimized setup time sequence margin, and generating a clock tree; on the basis of the generated clock tree, determining whether the time sequence violation of the retention time of the time sequence path needing to be optimized meets a preset requirement or not, and if the preset requirement is not met, adjusting the setting pattern of the useful clock skew adjustment, and returning to the step of generating the clock tree; and completing automatic wiring based on the clock tree meeting the predetermined requirement. According to the invention, the problem of power consumption increase caused by restoration of Hold time sequence violation can be solved.

The invention relates to the technical field of chips, and provides a time sequence optimization method and device for a clock control path, a medium and a program product, and the method comprises the steps: inserting a multi-stage register on the clock control path of a target circuit module according to the physical size and target frequency of the target circuit module, and constructing to obtain an assembly line chain; fixing a last-stage register of the assembly line chain at a target position; constructing a clock network on the premise of keeping the position of the last-stage register fixed, and in the process of constructing the clock network, shielding a time sequence constraint from the last-stage register to a clock gating unit controlled by the last-stage register; and after the clock network is constructed, physical connection between the clock gating unit and the last-stage register is established, and time sequence optimization is performed on a clock control path between the last-stage register and the clock gating unit. According to the method, power consumption surge, wiring congestion and violation risks caused by an overlong path are avoided, and the time sequence convergence rate and the resource utilization rate of the high-performance chip in the sign-off stage are remarkably improved.

A unified timing closure system for the simultaneous synthesis of multi-mode clock trees in a system-on-chip architecture, comprising: a timing convergence processor configured to perform simultaneous analysis and optimization of clock distribution paths across a variety of operating modes and process voltage-temperature operating conditions, wherein the timing convergence processor maintains a unified timing graph that correlates all clock sinks with multiple mode vectors representing setup and hold relationships under different conditions; a multitude of distributed computer scaling units distributed across physically distinct sub-areas of the system-on-chip architecture, each distributed computer scaling unit being configured to determine local delay scaling factors corresponding to process variations, voltage fluctuations, and temperature gradients in its respective sub-area, and dynamically adjust the delay buffer characteristics, link impedance, and driver strength in response to the local scaling factors; a clock offset synchronization unit coupled with the timing convergence processor and the numerous distributed clock scaling units, wherein the clock offset synchronization unit is configured to monitor and minimize insertion delay differences between multiple clock sinks by dynamically adjusting capacitive loads and buffer driver strengths throughout the clock network to maintain uniform propagation characteristics across all modes; a multi-mode synchronization processor that is operationally linked to the timing convergence processor and is configured to harmonize clock arrival times across the operating modes of function, test, and power saving by mapping all mode-specific constraints into a unified timing domain, and to correct inter-mode skew divergence by iteratively adjusting clock path latencies; a distributed timing communication interface that establishes a hierarchical interconnection network between the timing convergence processor and the multiple distributed corner scaling units, wherein the distributed timing communication interface is configured to exchange real-time timing information, delay deviation metrics, and control instructions via a synchronized token-based communication protocol; and A physical time-matching circuit consisting of tunable delay lines, programmable capacitive elements and temperature-compensated bias transistors, physically embedded in the clock distribution network, wherein the physical time-matching circuit receives adaptive control signals from the time convergence processor and adjusts local propagation characteristics to achieve time completion simultaneously across all operating modes and process boundaries.

The invention discloses a method and a system for checking a time sequence path based on logic depth splitting. The method comprises the following steps: acquiring the logic depth of the time sequence path; splitting the logic depth to obtain a buffer and inverter level and a register transfer level (RTL) level; based on the logic depth, a buffer and inverter level, and a register transfer level (RTL) level, a timing problem source is located. According to the time sequence path inspection method and system provided by the invention, the logic depth is divided into the buffer and inverter level and the RTL level, and the source of the time sequence problem is accurately positioned, so that the time sequence convergence efficiency is improved, and the chip design complexity is reduced.

The invention provides a logic synthesis optimization method and device, electronic equipment and a computer storage medium, and belongs to the technical field of EDA, and the logic synthesis optimization method comprises the steps: determining a target module included in an optimization strategy based on a time sequence report generated in a logic synthesis process; in the optimization strategy, a register retiming function and a register optimization function of the target module are enabled, so that the electronic design automation tool allows the registers between the modules to be moved when optimizing the target module; and based on the optimization strategy, executing logic synthesis on the to-be-synthesized design. A key bottleneck module influencing time sequence convergence can be optimized in a targeted manner in a logic synthesis process.

Apparatus and methods for constructing Network on Chips (NoCs) by algorithmically elaborating one or more of Network on Chips (NoCs) through a hierarchical topology composed of instantiations of sub-NoCs and leaf components, and one or more connectivity definitions. Designing NoCs using one or more instantiations of sub-NoCs reduces overheads during chip backend processes, such as for timing closure.

The present invention relates to a configurable logic system (101) programmed to model a logic design for data pipeline between master and slave; and the method of implementation, wherein said system (101) comprises of at least one first register (112) configured to store and transfer at least one data from said master to said slave; wherein said system (101) is configured to operate on one clock and one reset. The system (101) further comprises of at least one first control logic (118) that controls said first register (112) and fourth register (109) to provide hold to the ready signal from the slave to ease timing closure at high speed.

The application relates to the field of semiconductor counting statistics, and discloses a DDR memory counting statistics method, equipment and a storage medium. The method comprises the following steps: when a counting request is received; performing polling allocation combination processing on a counting statistics ID and a counting request value to generate an allocation array; querying a memory statistics value corresponding to the counting statistics ID from a preset DDR memory; accumulating the memory statistics value and the counting request value to generate a new memory statistics value, and writing the new memory statistics value into the DDR memory; when a reading statistics request is received; querying all statistics values corresponding to the reading statistics ID from the DDR memory according to a reading statistics ID to generate a statistics value set, wherein the reading statistics ID is used to poll a Block counter value in a Block counter value set; and calculating a statistics output value corresponding to the reading statistics request based on the statistics value set. In the embodiment of the application, the characteristics of the DDR address are used for addition and subtraction of statistics values, a complex Cache mechanism is not needed, and the logical complexity and timing convergence difficulty are reduced.

The application relates to a message verification method and device, a chip, a storage medium and a program product. The method comprises the following steps: acquiring input data and an input data amount of a current clock beat corresponding to a target verification message; selecting N groups of mask numbers corresponding to a target storage value according to the input data amount of the current clock beat, the target storage value being a cyclic redundancy check value stored in a previous clock beat; performing operation on the N groups of mask numbers and the corresponding target storage value respectively to generate a first logic calculation value of the current clock beat; performing cyclic redundancy iteration operation on the input data of the current clock beat according to the first logic calculation value of the current clock beat to obtain a cyclic redundancy check value corresponding to the current clock beat; and obtaining a final cyclic redundancy check value according to the cyclic redundancy check value corresponding to the current clock beat. The method can reduce the timing convergence and chip wiring difficulty.

The invention discloses a time sequence driven macro module layout method, which comprises the following steps of: clustering standard units and macro modules in a circuit netlist to generate a clustering hierarchical tree; abstracting a leaf node cluster of the clustering hierarchical tree into a pseudo macro with a specific area and shape, and generating a global initial layout position of the pseudo macro; aiming at the interior of each cluster, constructing a virtual connection weight model, and solving a relative position relationship of macro modules in the cluster; the intra-cluster macro modules with the relative positions determined are regarded as macro groups, macro group position optimization is carried out, global macro layout is completed, key macro modules are screened out according to a time sequence analysis report, the key macro modules are classified and recognized as array macro or free macro, and position updating is carried out respectively; and then direction optimization is carried out, and a final macro-module layout result is output. According to the method, the layout problem of a large-scale mixed-size circuit can be effectively solved, the layout regularity is kept, meanwhile, the worst negative relaxation and the total negative relaxation are remarkably improved, and the timing convergence of physical design is improved.

The application provides a data transmission circuit and method based on signal conversion, a chip and an electronic device, and belongs to the field of circuits.The data transmission circuit based on signal conversion comprises a first conversion module and a second conversion module.The first conversion module is used for receiving a parallel signal from a first clock domain and converting the parallel signal into a serial signal of a second clock domain, wherein the frequency of the first clock domain is less than the frequency of the second clock domain.The second conversion module is used for receiving the serial signal and converting the serial signal into the parallel signal.The scheme realizes the transmission of the parallel signal from the first conversion module to the second conversion module within a first clock cycle.By applying the data transmission circuit based on signal conversion to transmit signals between FPGAs, a large number of signals can be transmitted from one FPGA to another FPGA within a clock cycle, thereby reducing the difficulty of circuit design and timing convergence.

The application aims to provide a method for reducing the timing influence of metal dummy based on metal dummy blockage, which comprises the following steps: obtaining chip parameters and metal density requirements; performing metal filling according to the chip parameters and the metal density requirements; and verifying whether the filled chip meets the specifications. The application avoids the influence of metal dummy on the paths by using dummy blockage to avoid adding metal dummy at these places, without changing the timing of the paths, so as to reduce the iteration number of timing convergence and make the timing convergence more controllable.

The present application belongs to the technical field of low power consumption of integrated circuit design, and discloses a multi-threshold voltage unit distribution method, comprising the following steps: step 1: data preparation: obtaining a simplified path set according to a full high threshold circuit, and obtaining unit delay, timing increase / decrease factor and static power consumption value of the full high / low threshold circuit; step 2: distributing threshold according to the path set: distributing threshold point by point in the full high threshold circuit according to path weight and unit weight until the paths in the path set all meet timing requirements; and step 3: updating the path set: applying the threshold distribution result and performing static timing analysis, if the static timing analysis result does not meet timing, updating the path set and performing the threshold distribution operation according to the path set again until the static timing analysis result meets timing. The present application effectively reduces the method running time through the simplified path set, and ensures threshold distribution accuracy and timing convergence through updating the path set.

The invention discloses a system-on-chip (SOC) chip distributed debugging architecture and a method thereof. The debugging architecture comprises a debugging chain logic unit, and the debugging chain logic unit is integrated in each to-be-debugged module in an SOC chip; the debugging chain logic unit comprises a register beating module and a signal branching module; the register beating module is used for performing register beating processing on an input debugging signal; the signal branching module is used for dividing the debugging signal processed by the register beating module into a first-path debugging signal and a second-path debugging signal according to preset address information or mark information, the first-path debugging signal is used for internal debugging of the current to-be-debugged module, and the second-path debugging signal is used as debugging output; and enabling the debugging output of the current to-be-debugged module to be connected with the debugging access inlet of the next to-be-debugged module to form a continuous distributed debugging network. According to the method, the problems of resource occupation, difficulty in time sequence convergence, low debugging efficiency and the like in the chip debugging process are solved.

This application provides a timing control device, system, and method for frequency-scanning radar based on frequency synthesizer and digital logic modules. The frequency synthesizer module serves as the synchronization source and timing reference source for the operating modes of the frequency-scanning radar system. In terms of system hardware architecture, it achieves coherent synchronization between the RF sub-module and the digital logic module. At the RF end, the SYNC signal is used to broaden the pulses of each sub-module, thereby forming the gate signals for each module's corresponding operating mode, which are distributed only by the digital logic module. At the digital end, edge and pulse width detection of the SYNC and MODE signals triggers the sampling and digital signal processing timing. The entire system uses the signal generated by the frequency synthesizer module as the reference, achieving high precision and low phase noise while reducing the external RF cables of the digital logic module. It also achieves strong coupling between the RF and digital ends, which is beneficial for FPGA on-chip resource optimization and timing convergence, reducing design verification costs and subsequent expansion costs.

The application discloses a kind of chip synchronous clock between circuit jump fault test method, in chip synchronous clock test circuit, pulse_ctrl module is connected behind PLL output clock, the pulse_ctrl module generates internal clock and reset;Including divider module, the divider module includes frequency division circuit, to generate frequency division clock;Still including syn_occ module, the syn_occ module controls the pulse output of frequency division clock;Pulse_ctrl module outputs clock_out as the reference clock of chip frequency division circuit;When fault test, the output signal div_rstn of pulse_ctrl module controls the reset end rstn of frequency division circuit, and participates in the test clock generation of sync_occ module.The application realizes the test of synchronous clock between circuit jump fault, and the clock path under test mode and the clock path under chip function mode are completely identical, the circuit area and timing convergence overhead of test logic are reduced, and the test coverage of circuit fault is improved.

Systems and related methods for implementing fabric, i.e., correct timing convergence, may include a first semiconductor device providing a thin interface module on a base die, the thin interface module including: an address register mechanism for an address interconnect according to an address clock from an address clock interconnect; the data register mechanism is used for the data interconnects according to the data clocks from the data clock interconnects; and a plurality of bonding mechanisms for communicating with the second semiconductor device via the address interconnects and the data interconnects.

The application discloses a method and system for checking a timing path based on logical depth splitting, and the method comprises the following steps: acquiring a logical depth of a timing path; splitting the logical depth to obtain a buffer and inverter level and a register transfer level (RTL) level; and locating a timing problem source based on the logical depth, the buffer and inverter level and the RTL level. The timing path checking method and system provided by the application can locate the timing problem source accurately by splitting the logical depth into the buffer and inverter level and the RTL level, thereby improving timing convergence efficiency and reducing chip design complexity.

The invention discloses a generation method, device and system suitable for a hybrid-driven multi-bit trigger. The generation method comprises the following steps: acquiring all single triggers in a digital chip of which the initial layout design is completed; mapping each single trigger into a ternary trigger vector comprising a transistor size, a threshold voltage and a number, and generating a trigger matrix; splitting the trigger matrix into a plurality of independent sub-matrixes according to the clustering result of the single trigger, wherein each sub-matrix corresponds to one multi-bit trigger; repeating the following steps until the Pareto front is stable and meets a preset layout legalization verification condition to obtain a multi-bit trigger: by taking the normalized total negative margin and power consumption minimization as optimization objectives, optimizing each sub-matrix by adopting a proxy auxiliary differential evolution algorithm and a non-dominated sorting evolution algorithm to obtain a Pareto optimal solution set; and if the multi-bit trigger corresponding to the Pareto optimal solution set does not meet the layout legalization verification condition, re-dividing the trigger matrix. The clock network power consumption can be reduced, and the time sequence convergence rate is improved.

The invention discloses an AI-assisted time sequence report analysis method, and belongs to the technical field of integrated circuit design automation. The method comprises the following steps: acquiring a static time sequence analysis report; analyzing the report through an analysis rule base, and extracting structured information of a time sequence path; performing hierarchical grouping on the plurality of analyzed time sequence paths according to time sequence grouping, clock domains and violation types to generate time sequence statistical characteristics; and identifying a key path according to the time sequence statistical characteristics, and outputting a structured analysis result and an optimization suggestion. Through automatic analysis and intelligent analysis, the time sequence debugging efficiency is remarkably improved, dependence on experience of engineers is reduced, and the method is suitable for time sequence convergence scenes of large-scale integrated circuit design.

The application provides a memory compiler IP timing convergence and power consumption collaborative optimization method and system, relates to the technical field of compilers, and comprises the following steps: obtaining circuit netlist information, extracting a timing path, performing wiring topology analysis, dividing a power consumption control domain by adopting a fine-grained power consumption control strategy, constructing a deep neural network model to predict a delay, training a decision tree model to obtain an optimization strategy, calculating a path priority to perform function partitioning, and finally generating a layout and wiring scheme that meets timing convergence requirements and is optimized in terms of power consumption. The application realizes the collaborative optimization of timing convergence and power consumption of the memory compiler IP, and improves the performance of integrated circuits.

A method for implementing timing closure of an ultra-large-scale SOC based on module division includes the following steps: S1, acquiring timing data of a full chipset, and dividing an SOC into three modules; S2, reading lib, lef, netlist and def in each module, determining each specific module requiring timing recovery and each prototype module not requiring timing recovery, reading lib and lef in each specific module, and reading netlist and def in each prototype module; S3, creating multiple process corners and acquiring timing data of each process corner, and back-annotating and reading netlist and def out of the multiple process corners corresponding to each specific module to determine an attribute-maintained part and a to-be-recovered part; and setting the attribute-maintained part and each prototype module to be in a not-to-be-recovered state; and S4, sending out a timing recovery command, and performing timing violation fixing on the to-be-recovered part.

The invention discloses a time sequence driving clock tree synthesis method and product based on key node pairs, and the time sequence driving clock tree synthesis method comprises the steps: constructing an initial clock tree, extracting a plurality of register transmission paths meeting the allowance requirement based on the initial clock tree, constructing a key node pair file according to the plurality of register transmission paths, generating a starting node mapping table and an ending node mapping table for the file according to the key nodes; dividing the plurality of node clusters in the initial clock tree into non-key node clusters and key node clusters based on the initial node mapping table and the termination node mapping table; and respectively processing the non-key node cluster and the key node cluster in the initial clock tree to obtain a final optimized clock tree. The time sequence driven clock tree synthesis method aims to construct a time sequence driven balance clock tree while ensuring time sequence convergence.

The present disclosure relates to the technical field of digital integrated circuit design, in particular to a binary content addressable memory building method, device, memory and system. The method comprises: constructing a bottom basic unit based on a register; splicing a plurality of bottom basic units through columns to form a column splicing unit, and controlling the column selection routing of each bottom basic unit in the column splicing unit through column control logic; splicing a plurality of column splicing units through rows to form a binary content addressable memory of a target specification, and controlling the row selection routing of each column splicing unit through row control logic. The present disclosure isolates the input and output of the bottom basic unit as independent integrated units by making the input and output of the bottom basic unit registers, thereby blocking the complex timing path between units, solving the timing convergence difficulty and layout congestion problem faced by large-scale pure register array in the synthesis stage.

The invention discloses a method, a tool and a program product for optimizing time sequence consistency, and relates to the field of chip design. Reading time sequence data from the time sequence database of each stage; creating a violation path group corresponding to each stage based on the time sequence data; analyzing and calculating to obtain corresponding path adjustment parameters of each violation path group in different stages and time sequence difference conditions of the violation path groups in different stages; according to the time sequence difference condition, indicating to adjust the target stage or indicating to enter the next process; if the next process is indicated to be entered, sign-off verification is entered, and if the target stage is indicated to be adjusted, path adjustment parameters are set to run before implementation of the target stage. According to the method, the time sequence consistency and the critical path accuracy of each physical design stage are improved, judgment according to experience of designers is not needed, and the situation that constraints are too strict or too loose does not occur. The iteration speed and the time sequence convergence speed of physical design are well increased, and the automation capacity of the physical design process is improved.

The invention relates to the technical field of electronic engineering, and discloses a control circuit hexadecimal signal generation method, an annunciator and a multifunctional regulator, and the method comprises the steps: collecting control circuit configuration, analyzing a constraint identifier and a level conversion condition, and extracting a circuit association node; analyzing node cross-domain characteristics, generating a jump propagation trajectory, extracting a critical section and calculating a time sequence margin coefficient, dividing a signal conversion block based on the coefficient, identifying a coding and decoding check chain, analyzing phase alignment logic to construct a signal check sequence, querying a block delay path, extracting an optimization point and calculating time sequence convergence confidence, and finally, generating an eye pattern verification matrix, analyzing noise margin characteristics and anti-interference codes, and finally generating an anti-attenuation hexadecimal signal sequence of the target control circuit. Therefore, signal generation of the control circuit is improved.

The invention discloses an on-chip clock controller for testability design and an optimization method thereof, based on the thought that asynchronous logics have no time sequence relation and do not need time sequence check, selectors in OCC circuits fixedly select high-speed clock output paths, and a front-end selector is additionally arranged at the front end of each OCC circuit, so that the time sequence check is not needed. A path selection signal of a front-end selector is used for selectively inputting a high-speed function clock signal or a low-speed test clock signal, so that the low-speed test clock signal enters an OCC circuit and then is output through a high-speed clock output path of an internal selector, and therefore, an asynchronous clock domain relationship is kept between clocks output by different OCCs; therefore, the cross-domain time sequence check between different clock domains is not triggered, the time consumption of time sequence convergence iteration performed by the rear end due to the cross-domain time sequence check is saved, and the overall development period of the chip is shortened.

The present invention relates to a configurable logic system (101) programmed to model a logic design for data pipeline between master and slave; and the method of implementation, wherein said system (101) comprises of at least one first register (112) configured to store and transfer at least one data from said master to said slave; wherein said system (101) is configured to operate on one clock and one reset. The system (101) further comprises of at least one first control logic (118) that controls said first register (112) and fourth register (109) to provide hold to the ready signal from the slave to ease timing closure at high speed.

A system and related method for achieving correct-by-construction timing convergence may comprise a first semiconductor device providing a thin interface module on a base die, the thin interface module including an address register mechanism for an address interconnect that follows an address clock from an address clock interconnect, a data register mechanism for a data interconnect that follows a data clock from a data clock interconnect, and a plurality of junction mechanisms that communicate with a second semiconductor device via the address interconnect and the data interconnect.

The invention discloses a method for introducing effective clock skew in a chip layout stage, which comprises the following steps of: utilizing an optimized time sequence of the effective clock skew to enable clock signals to arrive at a time sequence unit in a staggered manner, and offering surplus time sequence resources on a non-critical path to an adjacent critical path. According to the method, the effective clock skew is improved into an active optimization strategy in the early stage, and the degree of freedom and effectiveness of optimization are improved; a clear and quantitative optimization target is provided for the clock tree synthesis tool, so that the balance operation has clear time sequence guidance quality, and resource waste on a non-critical path is avoided; the problem of time sequence violation is solved by utilizing time sequence information earlier and more effectively, and higher working frequency is achieved; or the time sequence convergence is realized with lower power consumption, and the chip performance is improved; through effective clock skew, effective linkage of a layout wiring stage, a clock tree synthesis stage, a clock path and a data path is realized, a new normal form of a physical design stage is formed, and seamless connection of different design stages is realized.