48 results about "Virtual clock" patented technology

The invention relates to the technical field of virtual power plant intelligent control, and discloses a virtual power plant intelligent decision-making system and method based on hierarchical cooperative control, and the method comprises the steps: constructing a three-dimensional unified model; an elastic virtual clock system is constructed, and cooperative operation of different time scale systems is realized; developing a time sequence sensing topology reconstruction engine, and optimizing and controlling a topology structure by analyzing time characteristics of nodes; a fault time sequence two-dimensional recovery mechanism is realized, and node faults and time deviation are cooperatively processed; a space-time elasticity evaluation system is constructed, and real-time monitoring of the system state and comprehensive evaluation of the space-time elasticity capability are achieved; according to the invention, by adopting a hierarchical cooperative control technology, time and space dimensions are unified in an elastic control framework, and dynamic self-adaption of each hierarchical control system of the virtual power plant on time characteristics and topological structures is realized.

The invention discloses a dynamic master clock selection method based on Kalman filtering and Bayesian estimation, which is applied to the technical field of master clock selection, and comprises the following steps: constructing a virtual clock by calculating observation equations of a plurality of atomic clocks; performing state estimation on the atomic clocks by using a Kalman filtering method to obtain state estimation values of the atomic clocks; the state estimation value of each atomic clock comprises the phase and frequency estimation value of the atomic clock; the phase of each atomic clock is the phase deviation of the atomic clock relative to the virtual clock, and the frequency estimation value is the frequency estimation value of the atomic clock relative to the virtual clock; calculating the short-term frequency stability and the long-term frequency drift rate of the atomic clock based on the state estimation value of each atomic clock, and defining the comprehensive performance index of the atomic clock based on the short-term frequency stability and the long-term frequency drift rate; and calculating the posterior probability of each atomic clock based on the comprehensive performance index of each atomic clock and the current observation data by using a Bayesian estimation method so as to perform high-flexibility and high-reliability main clock selection.

Examples described herein provide a computer-implemented method that includes receiving a plurality of profiles corresponding to at least one of a plurality of virtual machines. Each of the plurality of profiles defines a validity period and an allowable variation of time. The method further includes determining, based at least in part on the validity period, a subset of the plurality of profiles that are active. The method further includes calculating a uniform distribution for virtual clocks of each of the subset of the plurality of virtual machines and determining a desired offset. The method further includes adjusting a virtual clock frequency of a virtual clock based at least in part on the desired offset and the allowable variation of time. The adjusting causes a difference between a real time-of-day clock and a virtual time-of-day clock of the at least one of the virtual clocks to increase.

The invention provides a joint action simulation method adopting a deterministic condition Monte Carlo simulation scheme and a solver system, and the method comprises the steps: Monte Carlo simulation: carrying out the traversal calculation of a key element combination for an action target to be simulated through employing the idea of deterministic condition Monte Carlo simulation, inputting the combination of all the key parameters into a simulation entity for calculation by utilizing the high-speed calculation capability of a computer system, finally automatically obtaining n results, and then screening m optimal results from the n results; a virtual clock metronome step: designing and coordinating a virtual clock metronome of each simulation module, wherein the virtual clock metronome is used for simulating tasks required to be completed in the real world by each module within the same time interval; and a perception interaction step: carrying out simulation entity perception layer interaction by adopting an artificial intelligence mode. The method has the advantages that the deterministic condition Monte Carlo simulation scheme is used for tactical-level action simulation, and wide application prospects and value are achieved.

The present application belongs to the chip verification technical field, and particularly relates to a controllable clock reset signal generation module and method based on SV and UVM. The function module is used for providing the required clock reset signal as an excitation signal in a test platform. The module architecture comprises an rcc interface, an rcc configuration class, an rcc environment top layer, a sequence library, and an rcc transaction class. The rcc interface contains N virtual clock group interfaces. The rcc configuration class defines a clock reset group agent number variable and N clock group configurations. The rcc environment top layer declares an rcc virtual interface handle, an rcc configuration handle, and N clock reset group agents. The sequence library contains four function sequences for controlling the clock signal and the reset release signal in the excitation signal. The rcc transaction class creates N clk transaction classes and encapsulates the attribute configuration of the corresponding clock reset. The present application overcomes the problems of the traditional verification platform, such as the clock reset signal being unable to be flexibly edited, low verification efficiency, high error rate and the like.

The present invention relates to the field of computer application technologies, and specifically discloses a dual-clock multi-core embedded concurrent timing simulation method and apparatus. The method includes: determining the core rate of each core in a multi-core embedded system and simulation events to be simulated; determining the global virtual clock rate of a global virtual clock according to the core rates of all cores; dividing the global virtual clock rate by the core rate to obtain the core clock rate ratio of each core's local virtual clock relative to the global virtual clock; and sequentially determining whether each core needs to execute simulation in each global virtual clock cycle according to the ratio between the current cycle number of the global virtual clock and the core clock rate ratios of each core, so as to simulate the simulation events through the cores that need to execute simulation in each global virtual clock cycle. The present invention solves the problem of core speed mismatch and simulation error caused by different core processor frequencies.

A system including an asynchronous finite state machine that transitions from a first state to a second state in response to receiving a virtual-clock event signal. The system further includes a trigger circuit that asserts a trigger signal when a first-state asynchronous event signal is asserted while the asynchronous finite state machine is in the first state. The system further including a virtual clock-pulse circuit configured to generate the virtual-clock event signal after receiving the trigger signal.

The invention belongs to the technical field of high-speed data testing, and discloses a high-speed signal eye pattern testing method and system based on automatic testing equipment, and the method comprises the steps that a high-speed signal configuration vector is divided into a configuration section and an action section, the configuration section is used for rapidly configuring a testing environment, and the action section is used for controlling a testing action; in the action section, constructing a virtual clock as a reference Trigger signal, and synchronizing the virtual clock and a high-speed signal to be detected to the same sequence group; performing waveform capture on the synchronized high-speed signal to be detected, and generating a two-dimensional array formed by sampling time and level values; the two-dimensional array is processed by a difference peak-valley segmentation method, the eye height, the rising / falling time and the jitter are measured based on a processing result, automatic control, measurement and output of test data can be realized through testing of automatic test equipment, data analysis and processing are facilitated, the test efficiency is improved, and interference of human factors is avoided.

The invention discloses a clock tree synthesis method, which comprises the following steps of: 1, inputting a selected clock tree topological structure according to a design when clock tree synthesis begins; 2, creating a virtual clock tree according to the topological structure of the clock tree; and step 3, constructing an actual clock tree according to the OCV information of the clock tree. According to the method, a non-uniform time sequence margin is added to a clock tree network under the condition that OCV is considered in the CTS stage, the margin is related to the topological structure of a clock tree, a virtual clock tree is constructed in the clock tree comprehensive starting stage, and the time sequence information of the virtual clock tree is added according to the OCV of the virtual clock tree and the magnitude of the non-uniform time sequence margin. And finally obtaining the time sequence optimized clock tree network.

The application discloses a performance optimization method for reverse debugging deterministic replay, and comprises the following steps: when a target program is executed by debugging in a first target architecture, first records are generated according to the lock competition frequency of threads, the shared memory access density and the state transition frequency, and the first records are divided into three types of high competition zones, low interaction zones and transition zones; thread dependency chains are constructed by extracting three types of dependency relations of synchronization, data and indirectness among threads from the first records; a dependency graph containing thread nodes, event nodes and dependency edges is constructed based on the first records and the dependency chains, and replay partitions are divided according to the number, control and timing dependencies among threads; finally, a replay engine is started in a second target architecture, CPU cores are bound to the replay partitions to execute the replay in parallel, the execution progress is monitored through the progress counter and the virtual clock of threads, the replay execution speed is dynamically adjusted, the dependency timing consistency is guaranteed through the synchronization notification process, and the cross-architecture replay is completed.

The invention provides a method for providing a synchronization in a computer network for synchronized playback of audio and / or video by a plurality of separate devices. Each separate device generates a virtual clock in response to a timing of the audio codec of a received audio stream. Especially, segmented time is used as reference time. Either the virtual clock is generated directly in response to the tick counter of the audio codec, or by a periodic measurement of the timing of the audio codec extrapolated by a monotonic clock. A sample rate converter may be used to slightly adjust the frequency of the virtual clock.

A control method, an electrical device, and a storage medium (200). The control method comprises: on the basis of a plurality of actual zero-crossing signals of an alternating current of an electrical device, predicting an occurrence period of future zero-crossing signals of the alternating current, and establishing a virtual clock (01); during the operation of the electrical device, performing zero-crossing signal correction on the alternating current on the basis of the virtual clock, so as to obtain a corrected zero-crossing signal (04); and on the basis of the corrected zero-crossing signal, controlling the electrical device to operate (05).

A method for event-based simulation of a system, wherein the simulation is performed on a computer system including a first computing unit and a second computing unit, the first computing unit having a simulation time; the second computing unit having a system time; the second computing unit executing a simulator application on which simulation objects are executed; and the first computing unit managing an event waiting queue, listing events for each simulation step and configuring the event with a process to be executed and setting a simulation time for executing the process; the second computing unit having a virtual clock generator, for each simulation step: transmitting a start signal to the virtual clock generator via the first computing unit for executing a new simulation step in the second computing unit; and increasing the system time of the second computing unit based on the time difference between the simulation time of the previous simulation step and the simulation time of the new simulation step, and executing the process at the simulation time configured for the waiting process.

Techniques include a method, apparatus, system and computer-readable medium to enhance security for time-synchronized networking. A method includes decoding a reference message comprising time information to synchronize a hardware clock of a time sensitive network (TSN) node with a network time for a TSN, the reference message associated with a reference synchronization interval, selecting a virtual clock from a set of virtual clocks for the TSN node, the virtual clock associated with a first synchronization interval that is different from the reference synchronization interval, and adjusting a time for the virtual clock based on the time information from the reference message to synchronize the virtual clock with the network time for the TSN. Other embodiments are described and claimed.

The application provides a clock tree synthesis method, comprising: obtaining a plurality of synchronous unit groups of a same target clock source; each of the synchronous unit groups comprises at least one synchronous unit; for each of the plurality of synchronous unit groups, a virtual clock source is set at a side of each synchronous unit in the synchronous unit group away from the target clock source along a common path of the synchronous unit to the target clock source; and a layout and routing tool is used to make clock delays of each synchronous unit in the synchronous unit group to the virtual clock source equal. By setting a virtual clock source on the synchronous unit groups belonging to different functional targets under the same clock source, the synchronous unit groups belonging to different functional targets under the same clock source can be synthesized independently, instead of starting from the clock source, so that the quality of the clock tree on the chip is greatly improved.

A method for monitoring timestamps in data (100) acquired by a data acquisition device (101, 201a, ..., 201n, 302, 303), wherein the data acquisition device (101, 201a, ..., 201n, 302, 303) includes a real clock (203a, ..., 203n) and a virtual clock (202a, ..., 202n), timestamps (102) are assigned to the data according to the real clock, and the virtual clock advances in substantially constant steps, and the data (100) is indexed (103) according to the virtual clock, the method comprising: receiving index values ​​(103, 103a) and corresponding timestamps (102, 102a) from the data (100), predicting timestamps of subsequent index values ​​based on the index values ​​and corresponding timestamps, as well as previous index values ​​(103) and corresponding timestamps (102), to generate predicted timestamps of subsequent index values, receiving real clock timestamps of subsequent index values, - Based on the acceptance criteria associated with the real clock timestamp and the predicted timestamp, the real clock timestamp or the predicted timestamp of the subsequent index value is provided.

The invention discloses a dynamic master clock selection method based on Kalman filtering and Bayesian estimation, which is applied to the technical field of master clock selection. The method comprises the following steps: constructing a virtual clock by calculating observation equations of multiple atomic clocks; performing state estimation on multiple atomic clocks using the Kalman filtering method to obtain state estimation values ​​of multiple atomic clocks; the state estimation value of each atomic clock comprises a phase and frequency estimation value of the atomic clock; the phase of each atomic clock is a phase deviation of the atomic clock relative to the virtual clock, and the frequency estimation value is a frequency estimation value of the atomic clock relative to the virtual clock; calculating the short-term frequency stability and long-term frequency drift rate of each atomic clock based on the state estimation value of the atomic clock, and defining a comprehensive performance index of the atomic clock based on the short-term frequency stability and the long-term frequency drift rate; and calculating the posterior probability of each atomic clock based on the comprehensive performance index of each atomic clock and current observation data using the Bayesian estimation method to select a master clock with high flexibility and reliability.

A clock determining method includes: when both a second network device and a first network device are synchronous with a reference clock, simulating, by using delay information between the second network device and the first network device and clock frequency information of the second network device, a second virtual clock synchronized with a first virtual clock, where the first virtual clock is used to simulate a clock of the first network device. A clock of the second network device can thus be simulated to perform a subsequent operation by using the simulated clock. For example, the simulated clock may be used to estimate precision time protocol (PTP) message synchronization performance of the second network device. Therefore, the PTP message synchronization performance of the second network device may be pre-determined before a global navigation satellite system (GNSS) fails, to guide network operation and maintenance activities.

The application relates to the technical field of signal analysis, and particularly discloses a chip single-wire IIC signal analysis method based on function testing, which comprises the following steps: step S1: performing dynamic window median filtering on an input signal, effectively eliminating signal jitter and burrs through dynamic expansion of a sliding window and median replacement, and outputting a smooth digital signal; step S2: performing virtual clock generation, obtaining a time interval sequence based on jump edge detection, calculating interval variance by using a sliding window, screening effective intervals according to a variance threshold, and finally equally dividing to generate a virtual clock; and step S3: sampling at the center of a signal steady state interval by using the clock, and analyzing sampling data according to an IIC protocol state machine to complete data decoding; the whole process is realized by a pure software algorithm, the hardware limitation is broken through, and the analysis precision and equipment compatibility are significantly improved.

The present invention provides a parallel bus data transmission system, method and storage medium, belonging to the technical field of data transmission, the system comprises: a data receiving end and a data transmitting end; the data receiving end generates a first state code through a state coding module, and sends the first state code to the data transmitting end through a heartbeat link; the data transmitting end controls a digital code generator to generate a first training code pattern corresponding to the first state code through a control register according to the received first state code, and sends the first training code pattern, a reference clock signal and N-channel data signals to the data receiving end; the data receiving end generates N-channel virtual clock signals through a clock distribution module based on the reference clock signal, and performs clock alignment processing to align the center of the N-channel virtual clock signal with the center of the N-channel data signal, and through the parallel bus data transmission system, the problem of clock skew and data skew in the parallel bus data transmission process can be solved.

The invention discloses a time reference correction system, which comprises a clock initialization module and a virtual clock module, and is characterized in that the clock initialization module is connected with the virtual clock module; the clock initialization module comprises a GPS device, a 5G communication module, an RTC clock, a counter capture channel, a credibility calculation module, a priority selector and an oscillator. The invention further comprises a clock establishment method of the time reference correction system, the composition of the system is improved and optimized, based on an embedded system scheme, a new time reference correction system is formed in a software and hardware combination mode, a GPS and a 5G time service source are combined, the time service jitter behavior generated due to environment willing during independent GPS time service is eliminated, and the time service accuracy is improved. The method has the advantages that no accumulated error exists, no jitter error exists in a local vibrator, a periodic quasi-local oscillator is calibrated through a GPS time service source or a 5G network time service source, and local time and coordinated world time are kept synchronous.

The PLL uses a virtual clock signal during delay and / or startup to maintain the closed loop of the PLL and allows the phase / frequency of the PLL output to be adjusted through a feedback divider during the delay / startup period when the reference clock provided to the PLL is not available. The virtual clock signal is a series of digital values ​​separated by a time period, where the digital values ​​indicate a transition of the virtual clock signal, and the time period corresponds to a period of the virtual clock signal. The selector circuit selects the virtual clock signal in the delay or startup mode as the digital reference clock signal and another reference clock signal in normal operation.

To provide a data processing apparatus which can be restored early from a malfunction due to an abnormal serial clock waveform which is caused by noise or power supply fluctuation.SOLUTION: A data processing apparatus includes a master unit and a plurality of slave units, and communicates data between the master unit and the slave units based on I2C standard. The master unit includes: detection means which detects that a serial data line has been in an L level for a predetermined time; and output means which outputs, when the detection means detects that the serial data line has been in the L level for the predetermined time, dummy clocks to the serial clock line until the serial data line becomes an H level, or outputs dummy clocks to the serial clock line until the dummy clocks are output a predetermined number of times.SELECTED DRAWING: Figure 5

The present application relates to the technical field of digital twin simulation, and discloses a multi-time-scale asynchronous parallel heat supply digital twin simulation method, which comprises the following steps: constructing a digital twin model of a heat supply system; configuring an independent virtual clock and an event buffer queue for a sub-model in the digital twin model; the sub-models asynchronously advance the simulation process according to their respective optimal time steps, and real-time monitor key state variables output by the sub-models; when any sub-model detects a preset coupling trigger event, the event and a time stamp are written into a global event buffer queue; the event buffer queue of the sub-models is polled and time-aligned based on a global event coordinator; when it is detected that multiple sub-models generate events at the same coupling time, cross-sub-model state synchronization and data interaction are triggered; after the state synchronization is completed, the sub-models continue to asynchronously advance the simulation until the next coupling event is triggered or the simulation is completed. Efficient and high-precision collaborative simulation of multi-scale processes of the heat supply system is realized.

The invention discloses an integrated circuit detailed layout method based on clock tree driving, which comprises the following steps: S10, firstly reading a layout file after global layout, and obtaining physical and time sequence information of a register; s20, register layout is carried out, capacitance-balanced bisecting K-means clustering is firstly used, a virtual clock tree is constructed for each clustered partition, optimal position searching is carried out on the registers according to the constructed clock trees, and the registers are moved to comprehensive favorable positions of the clock trees; and S30, performing non-register layout, re-legalizing overlapped units in the search process, and finally optimizing the line length of a signal line by using nearest neighbor search based on a priority queue. Optimized balance of the line length of the signal line and the line length of the clock tree is guaranteed, the clock tree is optimized, power consumption is optimized, and circuit stability and reliability are improved.

The invention provides a method for providing a synchronization in a computer network for synchronized playback of audio an / or video by a plurality of separate devices. Each separate device generates a virtual clock in response to a timing of the audio codec of a received audio stream. Especially, segmented time is used as reference time. Either the virtual clock is generated directly in response to the tick counter of the audio codec, or by a periodic measurement of the timing of the audio codec extrapolated by a monotonic clock. A sample rate converter may be used to slightly adjust the frequency of the virtual clock.

This invention belongs to the field of high-speed data testing technology and discloses a method and system for testing high-speed signal eye diagrams based on automated testing equipment. The method includes: dividing the high-speed signal configuration vector into a configuration segment and an action segment. The configuration segment is used for quickly configuring the test environment, and the action segment is used for controlling test actions. In the action segment, a virtual clock is constructed as a reference trigger signal, and the virtual clock is synchronized with the high-speed signal under test to the same sequence group. The synchronized high-speed signal under test is waveform captured to generate a two-dimensional array composed of sampling time and level value. The two-dimensional array is processed using a differential peak-valley segmentation method, and eye height, rise / fall time, and jitter are measured based on the processing results. Automated testing equipment enables automated control, measurement, and output of test data, facilitating data analysis and processing, improving testing efficiency, and avoiding human interference.

The present invention provides a cloud platform clock timing method and system, wherein the method includes: calibrating the clock of the master virtual machine according to the precise clock of the clock source, obtaining the calibrated master virtual machine clock, and forming a virtual machine clock card to provide clock services; searching for the correspondence between the master virtual machine clock service port identifier, the service virtual machine clock service port identifier, and the clock timing protocol according to the clock service port identifier of the first service virtual machine to be timed, and obtaining the first clock timing protocol between the first service virtual machine and the master virtual machine; calibrating the clock of the first service virtual machine according to the calibrated master virtual machine clock through a dedicated clock network based on the first clock timing protocol between the first service virtual machine and the master virtual machine, and forming a virtual clock card to provide precise clock services. The above scheme can improve the flexibility of providing clock timing for virtualized services, improve the utilization efficiency of clock cards, and reduce the cost of precise timing services for cloud platforms.

The invention relates to the technical field of signal analysis, and particularly discloses a chip single-line IIC signal analysis method based on a function test, which comprises the following steps: S1, carrying out dynamic window median filtering on an input signal, effectively eliminating signal jitter and burrs through sliding window dynamic expansion and median replacement, and outputting a smooth digital signal; s2, virtual clock generation is carried out, a time interval sequence is obtained based on jump edge detection, an interval variance is calculated by adopting a sliding window, effective intervals are screened according to a variance threshold, and finally a virtual clock is generated through equal division; s3, sampling in the center of a signal steady-state interval by using the clock, and analyzing sampled data according to an IIC protocol state machine to complete data decoding; the whole process is realized through a pure software algorithm, hardware limitation is broken through, and analysis precision and equipment compatibility are remarkably improved.

To provide an information communication system and an information communication device, capable of performing synchronous control with a reduced error by absorbing variation in a propagation time of information communication without using a reference clock such as a GMC or a relay device such as a BC or TC.SOLUTION: An information communication system 100 includes: a communication control unit 73 for making a communication unit 10 perform transmission / reception of synchronization information within a predetermined time in which a time difference can be regarded as constant between information communication devices 1; a time acquisition unit 76 for acquiring transmission / reception time of synchronization information of an own device CLa (1) and transmission / reception time of the synchronization information of an other device CLb (1); a time difference calculation unit 77 for calculating time differences between a clock 20 of the own device CLa and clocks 20 of all other devices CLb, on the basis of the time acquired by the time acquisition unit 76; a virtual time difference calculation unit 78 for calculating a virtual time difference, which is a time difference between the clock 20 of the own device CLa and a virtual clock; and a synchronization control unit 79 for performing time synchronization of the clock 20 of the own device CLa with the virtual clock on the basis of the virtual time difference.SELECTED DRAWING: Figure 4