106 results about "Virtual clock" patented technology

A dynamic race detection system and method overcomes drawbacks of previous lockset approaches, which may produce many false positives, particularly in the context of thread fork/join and asynchronous calls. For each shared memory location, a set of locks that are protecting the location and a set of concurrent thread segments that are accessing the location are maintained. To maintain these sets, each thread maintains a set of locks it is currently holding and a set of thread segments ordered before its current thread segment. Each thread also maintains a virtual clock that is incremented when it forks a second thread. A thread segment is a pair comprising a thread identifier and a virtual clock value. A data race is reported when the lockset for a particular shared memory location is empty and the cardinality of the set of concurrent threads for that memory location is greater than one.

Implementations of the present disclosure involve an apparatus and/or method for providing one or more clock signals within a processing device. In particular, one or more counter devices may be integrated into a microprocessor design that operates on a system clock signal to provide ratioed synchronous clock signals for use by the microprocessor. Additionally, one or more synchronization pulse signals are also generated from the one or more counter devices to facilitate communication between domains of the microprocessor that may operate on separate clock frequencies. Such synchronization pulse signals may also provide for a virtual clock signal within a clock domain to create a low frequency logic cluster within a high frequency domain of the microprocessor. A synchronous, low frequency reset signal is also disclosed to synchronize the counting devices to the system clock without the need for an additional high frequency signal path in the microprocessor design.

Prediction of a clock skew for an incomplete integrated circuit design, includes (a) selecting a first metal layer having at least one clock design figure, (b) placing, for a minimum clock skew prediction, clock source locations on the clock design figure in accordance with a first predetermined minimum distance between adjacent clock source locations, (c) placing, for a maximum clock skew prediction, a clock source location on a largest clock design figure in the first layer, such that the clock source location has a largest distance from a via to a lower layer, and (d) placing, for an intermediate clock skew prediction, clock source locations on intersections between the clock design figure and a virtual clock grid created for the first metal layer, the virtual clock grid having a predetermined offset from a design boundary and a predetermined pitch between grid lines.

An alphanumeric keyboard that is easy to learn, easy to use, and mountable on a handset for one-hand operation, comprises a virtual clock face having the center for the rotation of virtual hands, first set of twelve hourly radial positions, from one o'clock to twelve o'clock, surrounding the center, second set of twelve hourly radial positions, from one o'clock to twelve o'clock, surrounding the center and nearer to the center than the first set of twelve hourly radial positions, twenty four key areas, each key area being uniquely associated with one hourly radial position of the first and second sets, wherein each key area is substantially of 30 degree annular sector shape and contiguous to the adjacent key areas associated with the adjacent hourly radial positions, wherein all twenty four key areas are substantially of equal area, at least thirteen alphabetic keys placed at predetermined hourly radial positions of the first and second sets, and wherein each key has an indicia surface that is within the associated key area for being pressed by a finger. The associated radial direction or time may be marked on the key surface for visual or tactile differentiation.

The invention discloses a regulating method of lip synchronization of multimedia video and audio stream, which relates to the regulating method of lip synchronization. In order to solve the problem that the existing method can not well realize the lip synchronization of the multimedia stream, the regulating method is invented. The regulating method builds a virtual clock model on the basis of a real-time clock of a decoding end of the multimedia video and audio stream; according to the calculation results of adaptive delay algorithm and synchronized control algorithm, the virtual clock is adjusted and the lip synchronization of multimedia video and audio stream is available, thus greatly improving lip synchronization performance applied to multimedia and internet.

A method and system for providing a virtual clock on a computer by multiplying the number of instructions executed by the average instruction execution time. It is however not reliable to use this generic computation for virtualization of application in a fault tolerant system because the virtual clock computed like this quickly deviates from the system clock. A virtual clock computation is provided which includes periodic readjustment of the virtual to the system clock. Also, the errors coming from rounding of the number of executing instruction are suppressed.

Taking the assumption that the user instruction counters are maintained synchronized in the operational and the replication computers, replacing the system clock access by a virtual clock when virtualizing applications thus turning the system clock acquisition into a deterministic event. Replicating the system clock access can be thus done by reexecuting the application code in the replication machine avoiding transfer of information at each system clock access of the virtualized application programs.

A process for synchronizing an MPEG decoder, characterized by the process of calculating an actual instant of presentation Tpres of the video of an image, this instant relating to a local clock LSTC, further calculating an offset STOC between Tpres, being the calculated instant of presentation and the PTS label corresponding to the instant of presentation desired by the coder for the video of this image, so as to define a virtual clock VSTC=STCO+LSTC, the presentation of the video corresponding to this image being made at the PTS dates relating to the virtual clock VSTC, wherein this process relates to satellite decoders, MPEG decoders, as well, as digital TV receivers, utilizing a hard disk for recording coded data.

Achieving clock timing closure in designing an integrated circuit involves virtually synthesizing a clock network for the integrated circuit design to generate virtual clock buffering in the clock network before a point in the design flow at which the clock network is actually synthesized and committed to a netlist. Timing violations are determined for clock gates generated by the virtual clock buffering. Clock gating transforms are evaluated for the clock gates having the timing violations, based on recalculated clock and data path delays, to incrementally virtually synthesize the clock network. The clock gating transforms that result in the best timing gains are committed to the netlist. The clock network is then actually synthesized for the integrated circuit design, and design changes, due to the actual clock network synthesis, are committed to the netlist.

The invention discloses a distributed multi-hop wireless network clock synchronization method based on a mean field, and aims to solve the technical problem that a clock reference is difficult to determine in an existing distributed clock synchronization method. According to the technical scheme, the method comprises the following steps: realizing bidirectional time stamp exchange in a broadcast way firstly; making a clock difference overall effect between nodes be equivalent to a mean field; establishing a clock synchronization model of a network based on a spatial Markov random field; introducing a neighbor system and a clique potential according to the equivalence between the Markov random field and a Gibbs random field to obtain a clock synchronization energy function based on a mean field Ising model; and giving a clock synchronization algorithm adopting energy minimization optimization, namely, a whole-network clock distributed synchronization algorithm based on a mean field model. Through adoption of a whole-network clock synchronization method based on the mean field model, a whole-network virtual clock reference is determined through a mean action between the nodes, so that the technical problem that the clock reference is difficult to determine in the distributed clock synchronization method in the prior art is solved.

The invention includes a method and apparatus for generating virtual clock signals for differing hierarchies in a communication system conveying data frames of differing hierarchies. Specifically, a method according to one embodiment of the invention includes receiving data frames of a first hierarchy, receiving at least one input clock signal, and generating a virtual clock signal using the at least one input clock signal and a clock enable signal. The clock enable signal is generated using at least one of a data rate ratio and a clock rate ratio. The virtual clock signal is adapted for converting at least a portion of the data frames of the first hierarchy to data frames of a second hierarchy. The frequency of the virtual clock signal is determined by applying the clock enable signal to a common clock signal.

The invention relates to an SoC verification platform with high efficiency and high coverage rate for virtual clock synchronization. The SoC verification platform comprises a dual clock module used for generating two clock signals required by a system, a module to be verified used for executing random instructions and feeding back an execution result, a reference model module used for providing acomparison result of the module to be verified for the system, an initialization module used for providing programs required for initialization, a monitoring module used for monitoring the operating state of the module to be verified, a result comparison module used for checking the execution result of the module to be verified and a control module used for controlling the operation flow of the entire system. An SoC random instruction synchronization test platform can provide a solution for the problem that the instructions in the module to be verified in the SoC verification platform are difficult to synchronize with the instructions in a reference model, so that a lot of verification time is saved, the work difficulty is reduced, and the coverage rate of verification is increased.

The invention discloses a method for realizing hard real time virtual timer response of an embedded virtual machine. The method is characterized by comprising the following steps that through building a timer interrupt distribution table in Hypervisor, a limited hardware timer is interrupted, and the direct distribution is carried out through the interrupt distribution table of the Hypervisor, so the delay caused by the original modes of virtual machine event channels, virtual clocks and the like can be reduced, and in addition, the sharing of the limited hardware timer interrupt in an embedded processor platform at a plurality of partitions can be realized. The method has the advantages that the delay caused by the original modes of the virtual machine event channels, virtual clocks and the like is reduced, and in addition, the sharing of the limited hardware timer interrupt in the embedded processor platform at a plurality of partitions can be realized, so the precision and the response speed of the virtual timer of the virtual machine partitions can be respectively improved and accelerated, and finally, the great problem encountered by the application of the embedded virtualization technology to the field of aerospace is solved.

The preset invention provides an optical data link that prevents the internal I2C bus system from being hung up. The data link provides a CPU able to receive a reset signal and an IC (PHY) to control the physical layer to communicate with the outside of the data link, and they are coupled via the internal I2C bus system. When the data link receives a reset signal, the PHY behaves as the slave device, while, the controller behaves as the master device to output dummy clocks on the clock line of the I2C bus so as to sweep left data on the data line of the I2C bus.

The embodiment of the invention discloses a packet scheduling algorithm and a device thereof, belonging to communication field. The packet scheduling algorithm includes the following steps: partitioning the service packets into real-time service packets and non-real-time service packets according to headers of the service packets; judging whether legal real-time service packets exist in the real-time service packets according to shaping virtual clock algorithm, if yes, sending out the legal real-time service packets, and if no, sending out the non-real-time service packets; if new legal real-time service packets appear during the process of sending out the non-real-time service packets, suspending the sending of the non-real-time service packets and sending out the new legal real-time service packets. The device comprises a sort module, a judge module, a real-time service sending module, a non-real-time sending module and a notification module. The packet scheduling algorithm and the device can ensure that the sending of the real-time service packets is free from the influence of the non-real-time service packets and can avoid the occasion that the non-real-time service packets wait for too long. Therefore, the packet scheduling algorithm and the device have strong practicability, reliability and effectiveness.

The embodiments of the present invention provide a method and a device for managing state of a virtual machine and an intelligent terminal, wherein, the method includes: receiving a suspend instruction of a virtual machine, the suspend instruction includes a target machine-sleep state of the virtual machine; and the virtual machine is put into dormancy according to the suspend instruction, and thevirtual machine is acquired in real time. The sleep stage register value of the machine; when the sleep stage register value matches the target sleep state, the operation of the virtual CPU of the virtual machine is suspended. Through the above technical solution, the embodiment of the present invention can achieve complete suspension of the virtual machine, avoid false wakeup of an interrupt signal generated by the virtual machine by the virtual clock, and improve the energy-saving effect of the system.

A device and method for time synchronization in a communication network, wherein a virtual clock is produced by a controller in each network node based on the PROFINET-Standard and/or the Precision Transparent Clock Protocol. In contrast to known methods for estimating the time, the time of the virtual clock does not undergo sudden changes. The virtual clock includes a controlled, continuous path. As a result, the virtual clock is particularly suitable for time-critical applications. Here, the estimation of the time of a reference clock is improved by 18-35%. Accordingly, a markedly greater number of network nodes may be synchronized with a predetermined level of accuracy for the time synchronization.

The embodiment of the invention discloses a data stream shaping method. The method is used for reducing queue jumping operation of data packets and realizing data stream shaping in a network. A data stream shaping device calculates first virtual time of receiving a first data packet according to a virtual clock method, and selects a target data queue for the first data packet from N data queues according to the first virtual time and a time period corresponding to each data queue in the N data queues, wherein the N is an integer greater than or equal to 2. After determining the target data queue, the data stream shaping device adds the first data packet to the tail of t he target data queue. The embodiment of the invention also provides a related data scheduling method and device and a computing device.

The invention provides a dithering-removal method and device in de-mapping, a clock obtain method and device, and a phase detector. The dithering-removing method in de-mapping includes: data required de-mapping is processed de-mapping and is cached according with data writer clock; data writer virtual clock and data reader precast clock is obtained according with data required de-mapping and corresponding clock; data writer virtual clock and data reader precast clock are compared, data reader clock is generated according with the comparison result; data after being de-mapping is read according with the data reader clock. The technical solution provided by the invention can obtain dithering condition generated in de-mapping course effectively, filter dithering generated in data de-mapping course effectively by adjusting clock in time, and obtain data output with high performance.