19 results about "Virtual clock" patented technology

The present application belongs to the chip verification technical field, and particularly relates to a controllable clock reset signal generation module and method based on SV and UVM. The function module is used for providing the required clock reset signal as an excitation signal in a test platform. The module architecture comprises an rcc interface, an rcc configuration class, an rcc environment top layer, a sequence library, and an rcc transaction class. The rcc interface contains N virtual clock group interfaces. The rcc configuration class defines a clock reset group agent number variable and N clock group configurations. The rcc environment top layer declares an rcc virtual interface handle, an rcc configuration handle, and N clock reset group agents. The sequence library contains four function sequences for controlling the clock signal and the reset release signal in the excitation signal. The rcc transaction class creates N clk transaction classes and encapsulates the attribute configuration of the corresponding clock reset. The present application overcomes the problems of the traditional verification platform, such as the clock reset signal being unable to be flexibly edited, low verification efficiency, high error rate and the like.

The application discloses a performance optimization method for reverse debugging deterministic replay, and comprises the following steps: when a target program is executed by debugging in a first target architecture, first records are generated according to the lock competition frequency of threads, the shared memory access density and the state transition frequency, and the first records are divided into three types of high competition zones, low interaction zones and transition zones; thread dependency chains are constructed by extracting three types of dependency relations of synchronization, data and indirectness among threads from the first records; a dependency graph containing thread nodes, event nodes and dependency edges is constructed based on the first records and the dependency chains, and replay partitions are divided according to the number, control and timing dependencies among threads; finally, a replay engine is started in a second target architecture, CPU cores are bound to the replay partitions to execute the replay in parallel, the execution progress is monitored through the progress counter and the virtual clock of threads, the replay execution speed is dynamically adjusted, the dependency timing consistency is guaranteed through the synchronization notification process, and the cross-architecture replay is completed.

A control method, an electrical device, and a storage medium (200). The control method comprises: on the basis of a plurality of actual zero-crossing signals of an alternating current of an electrical device, predicting an occurrence period of future zero-crossing signals of the alternating current, and establishing a virtual clock (01); during the operation of the electrical device, performing zero-crossing signal correction on the alternating current on the basis of the virtual clock, so as to obtain a corrected zero-crossing signal (04); and on the basis of the corrected zero-crossing signal, controlling the electrical device to operate (05).

A method for monitoring timestamps in data (100) acquired by a data acquisition device (101, 201a, ..., 201n, 302, 303), wherein the data acquisition device (101, 201a, ..., 201n, 302, 303) includes a real clock (203a, ..., 203n) and a virtual clock (202a, ..., 202n), timestamps (102) are assigned to the data according to the real clock, and the virtual clock advances in substantially constant steps, and the data (100) is indexed (103) according to the virtual clock, the method comprising: receiving index values ​​(103, 103a) and corresponding timestamps (102, 102a) from the data (100), predicting timestamps of subsequent index values ​​based on the index values ​​and corresponding timestamps, as well as previous index values ​​(103) and corresponding timestamps (102), to generate predicted timestamps of subsequent index values, receiving real clock timestamps of subsequent index values, - Based on the acceptance criteria associated with the real clock timestamp and the predicted timestamp, the real clock timestamp or the predicted timestamp of the subsequent index value is provided.

A clock determining method includes: when both a second network device and a first network device are synchronous with a reference clock, simulating, by using delay information between the second network device and the first network device and clock frequency information of the second network device, a second virtual clock synchronized with a first virtual clock, where the first virtual clock is used to simulate a clock of the first network device. A clock of the second network device can thus be simulated to perform a subsequent operation by using the simulated clock. For example, the simulated clock may be used to estimate precision time protocol (PTP) message synchronization performance of the second network device. Therefore, the PTP message synchronization performance of the second network device may be pre-determined before a global navigation satellite system (GNSS) fails, to guide network operation and maintenance activities.

The application relates to the technical field of signal analysis, and particularly discloses a chip single-wire IIC signal analysis method based on function testing, which comprises the following steps: step S1: performing dynamic window median filtering on an input signal, effectively eliminating signal jitter and burrs through dynamic expansion of a sliding window and median replacement, and outputting a smooth digital signal; step S2: performing virtual clock generation, obtaining a time interval sequence based on jump edge detection, calculating interval variance by using a sliding window, screening effective intervals according to a variance threshold, and finally equally dividing to generate a virtual clock; and step S3: sampling at the center of a signal steady state interval by using the clock, and analyzing sampling data according to an IIC protocol state machine to complete data decoding; the whole process is realized by a pure software algorithm, the hardware limitation is broken through, and the analysis precision and equipment compatibility are significantly improved.

The present application relates to the technical field of digital twin simulation, and discloses a multi-time-scale asynchronous parallel heat supply digital twin simulation method, which comprises the following steps: constructing a digital twin model of a heat supply system; configuring an independent virtual clock and an event buffer queue for a sub-model in the digital twin model; the sub-models asynchronously advance the simulation process according to their respective optimal time steps, and real-time monitor key state variables output by the sub-models; when any sub-model detects a preset coupling trigger event, the event and a time stamp are written into a global event buffer queue; the event buffer queue of the sub-models is polled and time-aligned based on a global event coordinator; when it is detected that multiple sub-models generate events at the same coupling time, cross-sub-model state synchronization and data interaction are triggered; after the state synchronization is completed, the sub-models continue to asynchronously advance the simulation until the next coupling event is triggered or the simulation is completed. Efficient and high-precision collaborative simulation of multi-scale processes of the heat supply system is realized.

This invention belongs to the field of high-speed data testing technology and discloses a method and system for testing high-speed signal eye diagrams based on automated testing equipment. The method includes: dividing the high-speed signal configuration vector into a configuration segment and an action segment. The configuration segment is used for quickly configuring the test environment, and the action segment is used for controlling test actions. In the action segment, a virtual clock is constructed as a reference trigger signal, and the virtual clock is synchronized with the high-speed signal under test to the same sequence group. The synchronized high-speed signal under test is waveform captured to generate a two-dimensional array composed of sampling time and level value. The two-dimensional array is processed using a differential peak-valley segmentation method, and eye height, rise / fall time, and jitter are measured based on the processing results. Automated testing equipment enables automated control, measurement, and output of test data, facilitating data analysis and processing, improving testing efficiency, and avoiding human interference.

The invention relates to the technical field of signal analysis, and particularly discloses a chip single-line IIC signal analysis method based on a function test, which comprises the following steps: S1, carrying out dynamic window median filtering on an input signal, effectively eliminating signal jitter and burrs through sliding window dynamic expansion and median replacement, and outputting a smooth digital signal; s2, virtual clock generation is carried out, a time interval sequence is obtained based on jump edge detection, an interval variance is calculated by adopting a sliding window, effective intervals are screened according to a variance threshold, and finally a virtual clock is generated through equal division; s3, sampling in the center of a signal steady-state interval by using the clock, and analyzing sampled data according to an IIC protocol state machine to complete data decoding; the whole process is realized through a pure software algorithm, hardware limitation is broken through, and analysis precision and equipment compatibility are remarkably improved.

A virtual clock device, a time synchronization method, a device, equipment and a storage medium are disclosed, and relate to the technical field of time management and time synchronization. The device comprises a processor. The processor determines a frequency adjustment signal corresponding to a virtual clock based on a target time error between a target hardware clock and the virtual clock within a time synchronization period of the virtual clock and the target hardware clock. The processor resets a first time parameter of the virtual clock in a previous time synchronization period based on the frequency adjustment signal, obtains a second time parameter of the virtual clock, and writes the second time parameter into a shared memory. The processor reads the second time parameter from the shared memory in response to a time reading request of the virtual clock by an application program, and determines a current virtual time of the virtual clock based on the second time parameter and a time value of a hardware monotonic clock at a current time. The device can establish a high-precision smooth synchronization mechanism between the two time axes of the virtual clock and the target hardware clock, and the reading overhead is very low.

This invention relates to the field of intelligent control technology for virtual power plants, and discloses an intelligent decision-making system and method for virtual power plants based on hierarchical collaborative control. The method includes: constructing a three-dimensional unified model; constructing an elastic virtual clock system to achieve collaborative operation of systems at different time scales; developing a time-aware topology reconstruction engine to optimize the control topology by analyzing the time characteristics of nodes; implementing a two-dimensional fault timing recovery mechanism to collaboratively handle node faults and time deviations; and constructing a spatiotemporal elasticity assessment system to achieve real-time monitoring of system status and comprehensive evaluation of spatiotemporal elasticity capabilities. This invention, by employing hierarchical collaborative control technology, unifies time and space dimensions within an elastic control framework, achieving dynamic adaptation of the virtual power plant's control systems at each level in terms of time characteristics and topology.

This application discloses a lossless self-healing method and system based on FTTR digital twins and distributed prediction. The method includes: maintaining digital twins on both the FTTR master gateway and FTTR sub-gateways, employing a synchronization mechanism combining periodic full-scale and event-triggered incremental synchronization; the FTTR sub-gateways using a lightweight fault prediction model to infer in real time, predicting software faults and reporting them; the master gateway coordinating the digital twins of the faulty gateway and its neighboring gateways to enter a virtual sandbox environment, where each twin instance runs diagnostic algorithms in parallel, reaching consensus on the root cause of the fault based on a majority voting mechanism, and using a virtual clock to accelerate the deduction of the optimal repair solution; the faulty gateway performing minimally invasive repair operations while maintaining uninterrupted data plane forwarding; and the cloud optimizing the model through federated learning and distributing it. This application achieves zero service interruption during the fault repair process, improving overall system performance and diagnostic accuracy.

The application discloses an open multifunctional low-delay high-stability interconnection method and belongs to the technical field of communication and network interconnection. The method comprises the following steps: establishing passive point-to-point physical connection based on an industry standard among a plurality of accelerator processor nodes; realizing nanosecond-level precision global virtual clock synchronization among the nodes through a Sideband management channel independent of a main data channel; based on the synchronized clock, adopting a time window-restricted forward credit flow control mechanism to complete the cooperative reservation and authorization of link time periods and receiving buffer resources before data transmission; the sender sends data through the main data channel within the authorized time window, and the receiver verifies the compliance of the data arrival time; all control signaling is transmitted through the Sideband channel and is physically isolated from the high-speed data channel. The application realizes open and compatible, low-power-consumption and high-bandwidth physical interconnection, provides nanosecond-level low-delay and high-deterministic data transmission capacity, and improves the communication efficiency and system stability of a large-scale computing cluster.

The present application relates to the technical field of industrial control, and discloses a concrete feeding management and control method based on information-physical fusion, comprising: collecting current sequences in a sampling time window of a driving unit, generating power consumption cumulative characteristic quantities representing impedance changes through discrete integral operation; constructing a virtual clock reference vector of discrete time stamp dimension, and implementing local density mapping according to the characteristic quantities, adjusting the sampling step when the characteristic quantities exceed a preset threshold, so that the control pulse avoids the physical high resistance area; loading a high-frequency disturbance signal before issuing an instruction to overcome static friction resistance, and then determining the action time in combination with the processed reference vector, the present application effectively solves the phase step-out problem caused by the nonlinear rheology of concrete by reconstructing the time sequence topology of the information space, eliminates the mechanical response lag, and enhances the stability of the management and control system.

This invention discloses a time reference correction system, including a clock initialization module and a virtual clock module, wherein the clock initialization module is connected to the virtual clock module. The clock initialization module includes a GPS device, a 5G communication module, an RTC clock, a counter acquisition channel, a trustworthiness calculation module, a priority selector, and an oscillator. It also includes a clock establishment method for the time reference correction system. This invention improves and optimizes the system composition, based on an embedded system solution, and constructs a new time reference correction system through a combination of hardware and software. By combining GPS and 5G time synchronization sources, it eliminates the timing jitter caused by environmental factors when using GPS alone, and has the advantages of no accumulated error and no jitter error from the local oscillator. By calibrating the periodic quasi-local oscillator through a GPS time synchronization source or a 5G network time synchronization source, the local time is kept synchronized with Coordinated Universal Time (UTC).

The invention discloses a virtual clock calibration method and device for a power distribution network, terminal equipment and a storage medium. The method comprises the following steps: acquiring a power signal of the power distribution network at each moment; decomposing the power signal into a plurality of frequency band signals with different frequencies through a multi-frequency band filter; generating a confidence coefficient based on an autocorrelation operation result; obtaining the importance degree of each frequency band signal according to the confidence degree, and carrying out the weighted fusion of each frequency band signal, and obtaining the fusion time delay of the electric power signal at the current moment; according to a time sequence, sorting the fusion time delays corresponding to the power signals at each moment to obtain a time delay sequence of the power distribution network; fitting the time delay sequence to obtain a future time delay trend of the power distribution network; judging an external time service signal; if the external time service signal is normal, taking the external time service signal as the reference of the virtual clock; and if the external time service signal is abnormal, taking the future time delay trend as the reference of the virtual clock.

The application provides a clock synchronization method and device of a distributed device network, a terminal and a medium, the method comprising the following steps: determining a coordination center node with the minimum time-varying clock drift change rate in the current distributed device network, constructing an initial cluster network comprising multiple clusters by using other nodes in the network except the coordination center node, modeling a virtual clock of each node, initializing and synchronizing all clusters with the coordination center node, determining the relative clock drift between all nodes and the coordination center node, applying a spatial clustering algorithm based on hierarchical density noise, and clustering all nodes in the initial cluster network according to the relative clock drift, and assigning different synchronization frequencies to each target cluster in the target cluster network obtained by clustering, so as to realize distributed clock synchronization of the cluster network. The application re-divides the network into clusters by applying the spatial clustering algorithm based on hierarchical density noise, constructs a robust synchronization topology structure, and ensures the stability of the synchronization frequency allocation.

The application provides a kind of electric vehicle V2X terminal clock synchronization method for defending satellite navigation PPS signal lockout, for the short-term lockout of GNSS, by judging the receiving state of PPS pulse and reference timestamp, the adaptive sampling step of reference timestamp is determined, and then combined with the established virtual clock model, high-precision reference time is obtained without switching clock source, effectively overcoming the lack of time synchronization accuracy caused by clock source switching in the prior art. Based on the adaptive timestamp acquisition means provided by the application, various virtual clock models and correction parameter estimation methods can be applied, and the application can also provide wider applicability compared to the prior art.

The invention discloses a reverse debugging deterministic replay performance optimization method, which comprises the following steps of: when a first target architecture debugs and executes a target program, generating a first record in a high competition area, a low interaction area and a transition area according to a lock competition frequency, a shared memory access density and a state conversion frequency of a thread; extracting synchronization, data and indirect dependency relationships among the threads from the first record to construct a thread dependency chain; constructing a dependency graph containing thread nodes, event nodes and dependency edges on the basis of the first record and the dependency chain, and dividing replay partitions according to data, control and time sequence dependency among threads; and finally, starting a replay engine in a second target architecture, binding a CPU core for a replay partition, executing replay in parallel, monitoring the execution progress through a progress counter and a virtual clock of the thread, dynamically adjusting the replay execution speed, and combining a synchronous notification process to guarantee the consistency of a dependent time sequence, thereby completing cross-architecture replay.