SoC verification platform with high efficiency and high coverage rate for virtual clock synchronization

Abstract

The invention relates to an SoC verification platform with high efficiency and high coverage rate for virtual clock synchronization. The SoC verification platform comprises a dual clock module used for generating two clock signals required by a system, a module to be verified used for executing random instructions and feeding back an execution result, a reference model module used for providing acomparison result of the module to be verified for the system, an initialization module used for providing programs required for initialization, a monitoring module used for monitoring the operating state of the module to be verified, a result comparison module used for checking the execution result of the module to be verified and a control module used for controlling the operation flow of the entire system. An SoC random instruction synchronization test platform can provide a solution for the problem that the instructions in the module to be verified in the SoC verification platform are difficult to synchronize with the instructions in a reference model, so that a lot of verification time is saved, the work difficulty is reduced, and the coverage rate of verification is increased.

Description

technical field [0001] The invention relates to a high-efficiency and high-coverage SoC verification platform with virtual clock synchronization, in particular to a UVM random instruction testing method for a microprocessor in the SoC, and belongs to the technical field of integrated circuit verification. Background technique [0002] UVM (Universal Verification Methodology) random instruction test plays an important role in the SoC (system-on-chip) verification process. Random instruction test can reduce the interference of artificial factors in verification test incentives, avoid the tendency of artificially writing test incentives, and fully Corner cases of SoC designs are verified. [0003] In the UVM random instruction test, it is necessary to use the results of the reference SoC model to compare the execution results of the SoC to be verified to determine the correctness of the design. The SoC to be verified is cycle-accurate and can give the exact design of the design...

AI Technical Summary

Problems solved by technology

[0005] The shortcomings of the above-mentioned existing methods are mainly manifested in the following aspects: the instruction synchronization scheme based on the same clock signal is more complicated to synchronize between the instruction-accurate reference model and the cycle-accurate design model, and different control models need to be used for different design models. Logic, the command synchronization scheme needs to be redesigned after the SoC design is changed or replaced

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