17 results about "Clock tree synthesis" patented technology

An embodiment method of forming a layout plan of an integrated circuit (IC) device includes obtaining a placement of a plurality of digital circuit cells in a region of a layout plan; obtaining an initial placement of one or more thermal sensing resistor cells in a subset of a plurality of metallization layers and a subset of a plurality of via layers of the layout plan; obtaining a routing plan based on a clock tree synthesis and the initial placement of the one or more thermal sensing resistor cells; performing a thermal analysis based on the placement of the plurality of digital circuit cells and the routing plan to identify one or more areas of interest in the region of the layout plan; and obtaining a refined placement of the one or more thermal sensing resistor cells respectively over the one or more areas of interest.

A method for clock tree synthesis and a computer-readable storage medium are disclosed. The method includes: acquiring a global clock tree of a target circuit, the global clock tree comprising multiple timing skew groups; determining sub-clock trees corresponding to each timing skew group based on each timing skew group, wherein each sub-clock tree includes a common path and several non-common paths branching from the common path, and the common and non-common paths each include several components; for each sub-clock tree: determining a drive object to be processed based on the common path of the sub-clock tree; calculating the load center location based on the several non-common paths; inserting a load center component at the load center location; when the components on the common path where the inserted load center component is located, and the components adjacent to the load center component in each of the non-common paths connected to the inserted load center component, do not meet preset design constraints, setting several signal conditioning units between the drive object to be processed and the inserted load center component.

This application relates to a clock tree synthesis method and system for reducing the vertical coupling capacitance of the clock tree, belonging to the field of clock tree synthesis technology. The core of the method lies in the fact that, during the clock tree synthesis process in the physical design phase, by using a preset vertical design of the clock tree and a coupling-aware clock tree synthesis optimization cost function, the parasitic coupling capacitance between clock lines and adjacent signal lines in the vertical metal layer is systematically reduced, thereby improving the noise immunity of the clock network and reducing delay uncertainty and dynamic power consumption.

The application discloses a bottom-up clock tree synthesis method and system, which comprises inserting a logic unit to be inserted between a driver and a load connected to the driver; judging whether a clock tree with the inserted logic unit meets a design rule constraint, if yes, the insertion of the logic unit between the driver and the load connected to the driver is completed, if not, taking the inserted logic unit as a new load and starting from the insertion of the logic unit to be inserted between the driver and the load connected to the driver. When the logic unit is inserted, the logic unit is inserted layer by layer from bottom to top, and leaf nodes which need to share clock paths as much as possible due to clock skew, common control critical path and other reasons can be divided under the same sub-tree as early as possible in the bottom layer, so that the power consumption and the chip area occupied are reduced, the problem that the common path of the leaf nodes of the critical path is too short is avoided, and the clock tree synthesis situation of a buffer, an inverter or a mixture of both can be applied.

A clock tree timing optimization method and a computer readable storage medium, relate to the technical field of clock tree synthesis and timing optimization. The method comprises: obtaining a to-be-processed timing path, starting from the to-be-processed timing path, performing timing optimization on the to-be-processed timing path, the timing optimization comprising: determining a register with the smallest timing margin as a to-be-processed register; determining a target fan-in end timing margin according to a plurality of fan-in end timing margins of the to-be-processed register; and / or determining a target fan-out end timing margin according to a plurality of fan-out end timing margins of the to-be-processed register; calculating a clock offset according to the target fan-in end timing margin and / or the target fan-out end timing margin; adjusting each fan-in end timing margin of the to-be-processed register and / or each fan-out end timing margin of the to-be-processed register according to the clock offset; updating the to-be-processed timing path until a set ending condition is reached.

A clock tree generated through clock tree synthesis (CTS) for an integrated circuit (IC) design is stored in memory. The IC design includes a post-CTS clock tree having a plurality of clock nets. An application programming interface (API) implements a set of commands to allow a user, through a user request, to provide inputs to restructure the post-CTS clock tree to include a user-specified clock instance. The request is received from a user through the API and includes inputs defining the user-specified clock instance, a physical location of the clock instance, and a logical equivalence of a clock signal to be provided by one of the plurality of clock nets. One of the clock nets in the post-CTS clock tree is selected based on the inputs of the request and the post-CTS clock tree is restructured to include the user-specified clock instance.

The invention discloses a GNN-guided hierarchical H-tree low-skew clock tree synthesis method, which comprises the following steps of: firstly, executing fan-out-radius-capacitance three-constraint clustering on a chip register to generate an optimized buffer leaf cluster; spatial distribution and electrical characteristics are extracted, and an optimal sub-tree division scheme is predicted by using a graph neural network GNN; a K-adaptive non-uniform branch H tree is constructed based on the prediction result, a binary chain structure is adopted for a light load area, and a quadtree structure is adopted for a heavy load area; and finally, integrating the global clock network through the sparse grid. According to the method, the capacitance balance constraint and the graph neural network technology are creatively fused, and compared with a traditional H-tree method, the clock skew is reduced by 11.5%, the clock delay is reduced by 13.9%, the number of buffers is reduced by 31.0%, and the comprehensive operation time is remarkably shortened.

The invention discloses a method for introducing effective clock skew in a chip layout stage, which comprises the following steps of: utilizing an optimized time sequence of the effective clock skew to enable clock signals to arrive at a time sequence unit in a staggered manner, and offering surplus time sequence resources on a non-critical path to an adjacent critical path. According to the method, the effective clock skew is improved into an active optimization strategy in the early stage, and the degree of freedom and effectiveness of optimization are improved; a clear and quantitative optimization target is provided for the clock tree synthesis tool, so that the balance operation has clear time sequence guidance quality, and resource waste on a non-critical path is avoided; the problem of time sequence violation is solved by utilizing time sequence information earlier and more effectively, and higher working frequency is achieved; or the time sequence convergence is realized with lower power consumption, and the chip performance is improved; through effective clock skew, effective linkage of a layout wiring stage, a clock tree synthesis stage, a clock path and a data path is realized, a new normal form of a physical design stage is formed, and seamless connection of different design stages is realized.

The invention provides a clock tree synthesis method related to a frequency dividing circuit. The clock tree synthesis method comprises the following steps: step 1, selectively adding / deleting buffers on a clock line; 2, dividing an independent clock region behind an output pin of a frequency dividing circuit trigger; 3, in the newly divided clock area, a clock is created again, and an independent clock network is created; step 4, adjusting clock delay by adopting an insertiondelay command, and guiding a tool to complete clock tree balance; and step 5, completing automatic wiring of the clock circuit. On the basis of the steps, the problems that time sequence violation of a frequency dividing circuit (DIV) cannot be repaired under an original clock tree synthesis method, and power consumption is increased are solved.

A clock tree synthesis optimization method, device and product based on machine learning, the clock tree synthesis optimization method comprising: obtaining a trained replacement cell prediction model, wherein the trained replacement cell prediction model is used to predict the optimal replacement cell corresponding to the to-be-optimized cell in the clock tree synthesis; integrating the trained replacement cell prediction model into an EDA tool, so as to call the trained replacement cell prediction model through the EDA tool integrated with the trained replacement cell prediction model to predict the optimal replacement cell corresponding to the to-be-optimized cell in the clock tree synthesis. The above clock tree synthesis optimization method aims to reduce the running time of replacing the selected cell with a weaker driving capability cell of the same type in the clock tree synthesis stage without significantly deteriorating the clock timing and meeting the design rule violation requirement.

This invention discloses a timing optimization method, device, and computer-readable storage medium for clock tree synthesis, belonging to the field of chip design. Considering that analyzing each receive register individually can avoid register omissions, and that timing optimization based on the violation severity evaluation value of the receive registers can avoid omitting violation paths with high violation severity, this invention can determine the sum of the time margins of all violation paths containing the receive register for any receive register in the target chip, which is used as the violation severity evaluation value of the receive register. Then, the receive registers with violation paths are sorted in descending order of the absolute value of the violation severity evaluation value, and the violation paths of the receive registers are time-optimized according to the sorting. By sorting according to the violation severity evaluation value and optimizing one by one from the most severe to the least severe, the comprehensiveness of the optimization can be improved, thereby improving the timing optimization efficiency.

The invention relates to the field of rear-end design of digital integrated circuits, in particular to an integrated circuit segmented clock tree synthesis method and system oriented to multiple working modes, and the method comprises the steps: employing a segmented optimization strategy, firstly dividing the working modes into a high-frequency function mode group and a low-frequency test mode group based on a clock frequency, the high-frequency group is preferentially subjected to clock tree synthesis and the network is fixed, and then the low-frequency group is optimized on the fixed basis. According to the method, global balance conflicts are reduced through priority isolation, high-frequency path time sequence quality is improved, and meanwhile low-frequency path power consumption overhead is controlled. And finally, time sequence convergence and power consumption are verified, and collaborative optimization of the time sequence and the power consumption in a multi-mode scene is realized.

The application relates to the field of integrated circuit design, and discloses a physical design method suitable for a high-performance atomic-level computing chip. The application firstly analyzes RTL code, carries out module division, and generates required memories; then carries out logic synthesis, sets up different path groups for the memory-to-register path, and gives different weights; in the layout and wiring stage, according to the algorithm function and data flow direction of each module, top layout planning, module layout planning, power supply and ground planning, layout, clock tree synthesis, wiring and design rule checking are realized; then physical verification, timing analysis, power consumption and voltage drop analysis are carried out, and through sufficient iteration optimization, it is ensured that the final design meets the timing, power consumption and voltage drop requirements. The application focuses on the physical design of the high-performance atomic-level computing chip, effectively deals with the challenges of high computing intensity, high design complexity, large chip scale and high power consumption, and improves the reliability of the chip on the basis of ensuring high performance.

The present application relates to the technical field of integrated circuits, and particularly relates to a clock tree synthesis method and system. The present application generates multiple optimization groups by dynamically grouping clock trees, and then iteratively optimizes each optimization group to balance clock skew. Specifically, in the iteration process, a skew compensation device is inserted into the optimization group with the minimum delay, and in each iteration, the skew of the optimization group after the skew compensation device is inserted is balanced, and then it is determined whether the skew is balanced. If so, the iteration is ended. If not, the next iteration is continued until all optimization groups reach the clock skew balance, and the iteration optimization is ended. By using the above scheme, the clock network convergence efficiency and layout adaptability are significantly improved while ensuring the optimization accuracy through the cooperative optimization of the grouping strategy and the clock skew balance mechanism.

The invention relates to a clock tree synthesis method and system for reducing vertical coupling capacitance of a clock tree, and belongs to the technical field of clock tree synthesis. The core of the method is that in the clock tree synthesis process of a physical design stage, parasitic coupling capacitance of a clock line and an adjacent signal line between vertical metal layers is systematically reduced through preset vertical direction design of a clock tree and a clock tree synthesis optimization cost function based on coupling sensing; therefore, the anti-noise capability of the clock network is improved, and the delay uncertainty and the dynamic power consumption are reduced.

A timing-driven clock tree synthesis method and product based on key node pairs, the timing-driven clock tree synthesis method comprising: constructing an initial clock tree; extracting multiple register transfer paths satisfying a margin requirement based on the initial clock tree; constructing a key node pair file according to the multiple register transfer paths; and generating a start node mapping table and a termination node mapping table according to the key node pair file; dividing multiple node clusters in the initial clock tree into non-key node clusters and key node clusters based on the start node mapping table and the termination node mapping table; and processing the non-key node clusters and the key node clusters in the initial clock tree respectively to obtain a final optimized clock tree. The timing-driven clock tree synthesis method aims to ensure timing convergence while constructing a timing-driven balanced clock tree.

A hybrid window scheme for defining timing windows during CTS. CTS is performed to generate an intermediate clock tree including a respective insertion delay for each of the one of more flip-flops. A set of clock timing constraints is generated for the plurality of slack values of each flip-flop such that every positive slack value of the plurality of slack values is prevented from becoming negative, a lowest negative slack value of the one or more negative slack values is prevented from becoming lower, and every negative slack value of the one or more negative slack values having a higher value than the lowest negative slack value is prevented from becoming lower than the lowest negative slack value but is allowed to become lower than its current value. A second iteration of CTS is performed, constrained by the clock timing constraints, resulting in an enhanced clock tree.