57 results about "Clock tree synthesis" patented technology

The invention discloses a clock tree synthesis method and related equipment, and the method comprises the steps: dividing a plurality of time sequence units which need to receive clock signals from a clock source into clustering clusters of different levels, and enabling the load capacitance of each clustering cluster of the same level to be balanced; according to a hierarchical sequence of clusters starting from the clock source, taking each cluster as a node of a clock tree, recursively constructing the clock tree, and inserting a target buffer at the position of each node for driving the corresponding node; analyzing the delay and offset of the constructed clock tree to obtain an analysis result; and if the analysis result indicates that the delay and offset of the clock tree do not meet the preset constraint condition, adjusting the clock tree until the adjusted delay and offset of the clock tree meet the preset constraint condition. According to the technical scheme, power consumption and offset can be effectively reduced, calculation efficiency and design reliability are improved, and the method is suitable for high-performance chip design under the advanced technology.

The invention discloses a clock tree synthesis method and system based on clustering, and the method comprises the steps: carrying out the preliminary grouping of registers through employing a K-means clustering method, generating the position of a first-stage buffer under the condition that the maximum fan-out number limitation constraint, the maximum RC constraint and the position overlapping constraint are satisfied, and generating a second-stage buffer based on the position, and then constructing a subsequent clock tree by adopting a DME algorithm. The problem of clock signal distribution in large-scale integrated circuit design is solved, clock delay, clock skew and the number of buffers can be reduced, and the comprehensive quality of the clock tree is improved.

A clock tree generated through clock tree synthesis (CTS) for an integrated circuit (IC) design is stored in memory. The IC design includes a post post-CTS clock tree that includes a plurality of clock nets. A request to add a user-specified clock instance to the post-CTS clock tree is received and all logically equivalent clock nets in the post-CTS clock tree detected to generate a set of candidate clock nets. A reduced set of candidate clock nets is generated from the set of candidate clock nets based on a distance between each candidate clock net and the clock instance. One candidate clock net in the reduced set is selected based on a length of conductive traces required to interconnect the corresponding candidate clock net and the clock instance. The post-CTS clock tree is restructured to connect the clock instance to the selected one of the candidate clock nets.

The invention discloses a time sequence optimization method and device for clock tree synthesis and a computer readable storage medium, belongs to the field of chip design, and aims to solve the problem that register omission can be avoided by analyzing receiving registers as objects one by one, and time sequence optimization is performed according to violation degree evaluation value sorting of the receiving registers. According to the method and the device, omission of violation paths with deep violation degrees can be avoided, so that the sum of the time margins of the violation paths containing the receiving register can be determined as the violation degree evaluation value of the receiving register for any receiving register in the target chip; according to the sequence of absolute values of violation degree evaluation values from large to small, all receiving registers with violation paths are sorted, time sequence optimization is conducted on the violation paths of the receiving registers according to the sequence, sorting can be conducted according to the violation degree evaluation values, optimization is conducted one by one from heavy to light, the optimization comprehensiveness can be improved, and the optimization efficiency is improved. Therefore, the time sequence optimization efficiency is improved.

The invention provides a hierarchical clock tree synthesis method and system based on a hybrid topological structure, and aims to collaboratively optimize clock skew and clock delay in a chip clock network. The method comprises the following steps: firstly, introducing a balanced greedy search clustering algorithm, clustering registers at the initial stage of clock network construction, and reducing local clock skew and delay; and generating a bottom layer clock tree in each cluster by adopting a bounded deviation construction method so as to ensure the clock synchronization quality in the cluster. In a top-layer clock tree construction stage, the invention provides a self-adaptive H-tree topology construction algorithm, and the H-tree structure is dynamically adjusted according to the position relationship among all layers of clusters, so that a global clock distribution path is optimized under multiple layers. Besides, in order to further improve the CTS quality, the invention further designs a clock network optimization strategy based on buffer post-processing, and local buffer insertion and position adjustment are carried out for the problems of fan-out unevenness and load overrun so as to eliminate potential illegal paths.

Methods and systems for performing post clock tree synthesis of a clock tree. The methods and systems access, from memory, a circuit design comprising a clock tree that interconnects a clock source to a plurality of clock sinks, each clock sink in the plurality of clock sinks having an associated target insertion delay adjustment, the clock tree comprising a restriction on a quantity of levels of components for respectively adding delay to the clock source. The methods and systems identify an individual target insertion delay adjustment associated with an individual clock sink of the plurality of clock sinks and compare the individual target insertion delay adjustment to a threshold value. The methods and systems selectively remove the restriction on the quantity of levels of components to provide the individual target insertion delay adjustment based on comparing the individual target insertion delay adjustment to the threshold value.

The invention belongs to the field of digital integrated chips, particularly relates to a clock tree generation and optimization method for quickly realizing time sequence convergence, and aims to solve the problems that an existing clock tree does not completely optimize a time sequence violation path and is difficult to realize quick time sequence convergence. The method comprises the following steps: carrying out logic synthesis on RTL codes to obtain a time sequence convergence netlist after logic synthesis; performing chip layout planning and hardware unit placement based on the time sequence convergence netlist; performing clock tree generation and clock tree comprehensive optimization on the chip with the hardware unit to obtain to-be-wired chip data with time sequence convergence; and based on the to-be-wired chip data, wiring of the to-be-wired chip is carried out according to preset parameters, and static time sequence analysis is carried out. According to the method, the frequency index of the chip is effectively optimized by combining an EDA tool, manually adjusting the clock tree structure and guiding the file, the number of iterations in the clock tree generation process and the time sequence optimization process after the clock tree generation process can be reduced, and the method is effective, reliable, convenient and practical.

A method for constructing a fishbone H-clock tree suitable for a high-speed interface module includes the following steps: S1, setting an instance of a clock tree by means of an EDA tool, and eliminating existing definitions; S2, setting a root node, a non-default routing rule and multiple TAP nodes; S3, creating an H-clock tree, and performing H-clock tree synthesis, wherein the H-clock tree synthesis includes: introducing multiple intermediate nodes between the root node and the TAP nodes, editing a clock network between the root node and the TAP nodes by means of an innovus script, and deleting each redundant intermediate node to obtain a structure of a fishbone H-clock tree; mounting multiple sinks on each TAP node, and defining the TAP nodes in a same source group by means of the EDA tool; and performing routing according to the non-default routing rule to complete construction.

Aspects of the present disclosure include system, methods, and software for buffer insertions. In one example, a method includes receiving a clock signal network layout, wherein the clock signal layout comprises a clock source electrically coupled to a plurality of clock sinks via a plurality of net segments, and creating a plurality of buffering solutions, wherein each buffering solution of the plurality of buffering solutions comprises a plurality of buffers inserted on one or more net segments of plurality of net segments. The method further includes assigning each buffering solution a timing delay value and an area value, and selecting a buffering solution of the plurality of buffering solutions based on the timing delay value and the area value. The method additionally includes committing the selected buffering solution into an integrated circuit design comprising the clock signal network.

A unified timing closure system for the simultaneous synthesis of multi-mode clock trees in a system-on-chip architecture, comprising: a timing convergence processor configured to perform simultaneous analysis and optimization of clock distribution paths across a variety of operating modes and process voltage-temperature operating conditions, wherein the timing convergence processor maintains a unified timing graph that correlates all clock sinks with multiple mode vectors representing setup and hold relationships under different conditions; a multitude of distributed computer scaling units distributed across physically distinct sub-areas of the system-on-chip architecture, each distributed computer scaling unit being configured to determine local delay scaling factors corresponding to process variations, voltage fluctuations, and temperature gradients in its respective sub-area, and dynamically adjust the delay buffer characteristics, link impedance, and driver strength in response to the local scaling factors; a clock offset synchronization unit coupled with the timing convergence processor and the numerous distributed clock scaling units, wherein the clock offset synchronization unit is configured to monitor and minimize insertion delay differences between multiple clock sinks by dynamically adjusting capacitive loads and buffer driver strengths throughout the clock network to maintain uniform propagation characteristics across all modes; a multi-mode synchronization processor that is operationally linked to the timing convergence processor and is configured to harmonize clock arrival times across the operating modes of function, test, and power saving by mapping all mode-specific constraints into a unified timing domain, and to correct inter-mode skew divergence by iteratively adjusting clock path latencies; a distributed timing communication interface that establishes a hierarchical interconnection network between the timing convergence processor and the multiple distributed corner scaling units, wherein the distributed timing communication interface is configured to exchange real-time timing information, delay deviation metrics, and control instructions via a synchronized token-based communication protocol; and A physical time-matching circuit consisting of tunable delay lines, programmable capacitive elements and temperature-compensated bias transistors, physically embedded in the clock distribution network, wherein the physical time-matching circuit receives adaptive control signals from the time convergence processor and adjusts local propagation characteristics to achieve time completion simultaneously across all operating modes and process boundaries.

The invention discloses a time sequence optimization method of a clock tree and a computer readable storage medium, and relates to the technical field of clock tree synthesis and time sequence optimization. The method comprises the steps that a to-be-processed time sequence path is obtained, time sequence optimization is conducted on the to-be-processed time sequence path from the to-be-processed time sequence path, and time sequence optimization comprises the steps that a register with the minimum time sequence margin is determined as a to-be-processed register; determining a target fan-in end timing margin according to the plurality of fan-in end timing margins of the to-be-processed register; and / or determining a target fan-out end timing margin according to the plurality of fan-out end timing margins of the register to be processed; calculating a clock offset according to the target fan-in end timing margin and / or the target fan-out end timing margin; adjusting the time sequence margin of each fan-in end of the register to be processed and / or the time sequence margin of each fan-out end of the register to be processed according to the clock offset; and updating the to-be-processed time sequence path until a set ending condition is met.

The application discloses a clock tree synthesis method and related equipment, including: dividing a plurality of timing units needing to receive a clock signal from a clock source into clustering clusters of different levels, wherein the load capacitances of each clustering cluster of the same level are balanced; according to the level order of the clustering cluster starting from the clock source, taking each clustering cluster as a node of a clock tree, recursively constructing the clock tree, and inserting a target buffer at the position of each node for driving the corresponding node; analyzing the delay and offset of the constructed clock tree to obtain an analysis result; if the analysis result indicates that the delay and offset of the clock tree do not satisfy a preset constraint condition, adjusting the clock tree until the delay and offset of the adjusted clock tree satisfy the preset constraint condition. The technical scheme of the embodiment of the application can effectively reduce power consumption and offset, improve computing efficiency and design reliability, and is suitable for high-performance chip design under advanced process.

An embodiment method of forming a layout plan of an integrated circuit (IC) device includes obtaining a placement of a plurality of digital circuit cells in a region of a layout plan; obtaining an initial placement of one or more thermal sensing resistor cells in a subset of a plurality of metallization layers and a subset of a plurality of via layers of the layout plan; obtaining a routing plan based on a clock tree synthesis and the initial placement of the one or more thermal sensing resistor cells; performing a thermal analysis based on the placement of the plurality of digital circuit cells and the routing plan to identify one or more areas of interest in the region of the layout plan; and obtaining a refined placement of the one or more thermal sensing resistor cells respectively over the one or more areas of interest.

A method for clock tree synthesis and a computer-readable storage medium are disclosed. The method includes: acquiring a global clock tree of a target circuit, the global clock tree comprising multiple timing skew groups; determining sub-clock trees corresponding to each timing skew group based on each timing skew group, wherein each sub-clock tree includes a common path and several non-common paths branching from the common path, and the common and non-common paths each include several components; for each sub-clock tree: determining a drive object to be processed based on the common path of the sub-clock tree; calculating the load center location based on the several non-common paths; inserting a load center component at the load center location; when the components on the common path where the inserted load center component is located, and the components adjacent to the load center component in each of the non-common paths connected to the inserted load center component, do not meet preset design constraints, setting several signal conditioning units between the drive object to be processed and the inserted load center component.

This application relates to a clock tree synthesis method and system for reducing the vertical coupling capacitance of the clock tree, belonging to the field of clock tree synthesis technology. The core of the method lies in the fact that, during the clock tree synthesis process in the physical design phase, by using a preset vertical design of the clock tree and a coupling-aware clock tree synthesis optimization cost function, the parasitic coupling capacitance between clock lines and adjacent signal lines in the vertical metal layer is systematically reduced, thereby improving the noise immunity of the clock network and reducing delay uncertainty and dynamic power consumption.

The present invention relates to a structured chip design architecture and method, which includes a segmentation component, an idle state signal adding component, a clock generation component and a clock tree synthesis component; the segmentation component is used to perform appropriate module segmentation and hierarchical segmentation on each submodule of each IP module of the chip; the idle state signal adding component is used to add a module idle state signal to each submodule; the clock generation component is used to call a clock gating unit before each submodule, generate a gated clock according to the corresponding module idle state signal and send it to the corresponding submodule; the clock tree synthesis component is used to, during clock tree synthesis, output a segmented long clock tree from the clock of the clock gating unit according to the idea of ​​segmenting a long clock tree.

The present invention discloses a clustering-based clock tree synthesis method and system. The method uses the K-means clustering method to initially group registers, generates the positions of the first-level buffers under the constraints of the maximum fan-out limit, the maximum RC constraint, and the position overlap constraint, generates the second-level buffers based on this, and then uses the DME algorithm to construct the subsequent clock tree. The present invention solves the clock signal distribution problem in large-scale integrated circuit design, can reduce clock delay, clock skew, and the number of buffers, and improves the quality of clock tree synthesis.

The invention relates to the technical field of integrated circuits, in particular to a clock tree synthesis method and system. According to the scheme, the clock tree is dynamically grouped to generate a plurality of to-be-optimized groups, and then each to-be-optimized group is iteratively optimized, so that all to-be-optimized groups achieve clock skew balance. Specifically, in the iteration process, a deviation compensation device is inserted into a to-be-optimized group with the minimum delay, in each round of iteration, clock skew balance is carried out on the to-be-optimized group after the deviation compensation device is inserted in the current round, then whether skew balance is achieved or not is judged, if yes, the process is finished, and if not, the process is finished. And if not, continuing to carry out the next round of iterative optimization until all the to-be-optimized groups reach clock skew balance, thereby ending the iterative optimization. By adopting the scheme, through collaborative optimization of the grouping strategy and the clock skew balance mechanism, the convergence efficiency and layout adaptability of the clock network are remarkably improved while the optimization precision is guaranteed.

The invention specifically discloses a clock tree synthesis method based on clustering and reinforcement learning collaborative optimization, and relates to the technical field of integrated circuit design and electronic design automation. The method comprises the following steps: firstly reading a trigger coordinate, a clock source position and a design constraint parameter in a circuit; secondly, performing clustering grouping on triggers in the circuit through a clustering method, generating an initial hierarchical clock tree topology and determining candidate insertion positions of buffers; constructing a reinforcement learning environment, and defining a state space, an action space and a multi-target reward function; then, respectively learning a trigger relocation strategy and a buffer insertion and removal strategy by maintaining an independent movement Q table and action Q table within the displacement constraint; and finally, evaluating clock skew, delay and other performances, generating a comprehensive performance evaluation result, and performing iterative optimization judgment through a closed-loop feedback mechanism. According to the method, the clock skew and delay are effectively controlled, the local optimum problem of a traditional method is avoided, and the comprehensive quality and the automation efficiency of the clock tree are improved.

The invention provides a clock tree error positioning method and device. The clock tree error positioning method comprises the following steps: performing first clock tree synthesis on a target chip, and obtaining clock delay jumps corresponding to a plurality of clock trees in the first clock tree synthesis process; determining the clock tree of which the clock delay jump meets a first preset condition in the plurality of clock trees as a to-be-optimized clock tree; and performing error positioning on the to-be-optimized clock tree according to the clock delay reports corresponding to the to-be-optimized clock tree at the plurality of integrated nodes. Through the clock tree error positioning method, the problem that the research and development period of the chip is prolonged due to the fact that abnormal nodes in the chip are difficult to position is solved.

The invention discloses a process control method and device for rear-end design of a digital chip and EDA tool software, and the method comprises the steps: firstly, carrying out RC automatic calibration on a pre-wiring database according to a design database, a reference database, a reference parasitic parameter information file and / or a preset time sequence calibration target, and then obtaining a parameter configuration file, the parameter configuration file comprises calibration configuration parameters for parasitic parameter extraction and / or time sequence values; and then loading the parameter configuration file in a logic synthesis stage, a layout stage, a clock tree synthesis stage, a wiring stage and / or an ECO stage of physical perception in a digital chip back-end design for RC extraction. According to the calibration configuration parameters, RC extraction or a time sequence value of a certain stage is used as a reference value to guide an RC engine of another stage, and then an optimized RC estimation model is used for iterative design again, so that a calibrated RC estimation or extraction model can be applied in different stages, the RC estimation and extraction precision is improved, and the design process efficiency is further improved.

The application relates to a clock tree synthesis method, computer equipment, a readable storage medium and a program product in the field of chip design. The steps of the clock tree synthesis method include clustering, delay reduction, power consumption reduction and flattening. The method adopts a new detailed layout mode in the clock tree synthesis process, adjusts the detailed layout between the power consumption reduction stage and the flattening stage, makes the timing device move caused by the legalization of the placement position in the detailed layout more scientific, reduces the movement of the timing device caused by the legalization of the placement position in the detailed layout, and makes the clock tree synthesis result closer to the theoretical expectation. The search range during the calculation of the candidate position is limited by the boundary frame, the controllability of the device movement range in the detailed layout is realized through the position keeping parameter, the position change of the timing device is smaller, the result quality of the clock tree synthesis is more stable, and especially under the constraint of the lower maximum placement density, the method can reduce the deterioration of the result quality of the clock tree synthesis caused by the detailed layout.

The application discloses a bottom-up clock tree synthesis method and system, which comprises inserting a logic unit to be inserted between a driver and a load connected to the driver; judging whether a clock tree with the inserted logic unit meets a design rule constraint, if yes, the insertion of the logic unit between the driver and the load connected to the driver is completed, if not, taking the inserted logic unit as a new load and starting from the insertion of the logic unit to be inserted between the driver and the load connected to the driver. When the logic unit is inserted, the logic unit is inserted layer by layer from bottom to top, and leaf nodes which need to share clock paths as much as possible due to clock skew, common control critical path and other reasons can be divided under the same sub-tree as early as possible in the bottom layer, so that the power consumption and the chip area occupied are reduced, the problem that the common path of the leaf nodes of the critical path is too short is avoided, and the clock tree synthesis situation of a buffer, an inverter or a mixture of both can be applied.

The application provides a clock tree synthesis method, comprising: obtaining a plurality of synchronous unit groups of a same target clock source; each of the synchronous unit groups comprises at least one synchronous unit; for each of the plurality of synchronous unit groups, a virtual clock source is set at a side of each synchronous unit in the synchronous unit group away from the target clock source along a common path of the synchronous unit to the target clock source; and a layout and routing tool is used to make clock delays of each synchronous unit in the synchronous unit group to the virtual clock source equal. By setting a virtual clock source on the synchronous unit groups belonging to different functional targets under the same clock source, the synchronous unit groups belonging to different functional targets under the same clock source can be synthesized independently, instead of starting from the clock source, so that the quality of the clock tree on the chip is greatly improved.

The application discloses a new clock tree adaptive optimization method based on RISC-V architecture and utilizing useful skew, after S1, layout; S2, layout; S3, clock tree synthesis, S10, register-to-register timing path optimization is carried out; after S4, wiring, S20, register-to-memory timing path optimization is carried out. Through adaptive iteration, the application does not need complicated algorithms, solves the shortage of auto useful skew of the EDA tool itself, maximally repairs the timing problem, and simultaneously adopts the method of combining delay units, so that the win-win effect of high performance and low power consumption of chip design is realized.

The application provides a scan chain construction method, device and equipment and a storage medium. The method comprises the following steps: selecting any register as a starting register of a scan chain; determining a next-level register of the starting register based on a matching degree of each candidate register and the starting register, wherein the matching degree is determined based on physical position information of the register and path delay information based on clock tree synthesis (CTS); taking the next-level register as a new starting register, and performing the operation of determining the next-level register of the starting register based on the matching degree of each candidate register and the starting register until the next-level register is the last register in the chip; and constructing the scan chain of all registers according to the relationship between the starting register and the next-level register.

A clock tree timing optimization method and a computer readable storage medium, relate to the technical field of clock tree synthesis and timing optimization. The method comprises: obtaining a to-be-processed timing path, starting from the to-be-processed timing path, performing timing optimization on the to-be-processed timing path, the timing optimization comprising: determining a register with the smallest timing margin as a to-be-processed register; determining a target fan-in end timing margin according to a plurality of fan-in end timing margins of the to-be-processed register; and / or determining a target fan-out end timing margin according to a plurality of fan-out end timing margins of the to-be-processed register; calculating a clock offset according to the target fan-in end timing margin and / or the target fan-out end timing margin; adjusting each fan-in end timing margin of the to-be-processed register and / or each fan-out end timing margin of the to-be-processed register according to the clock offset; updating the to-be-processed timing path until a set ending condition is reached.

A clock tree synthesis method comprises obtaining information of a source node and information of N leaf nodes, N being a positive integer greater than 1, performing a Steiner tree algorithm according to the information of the source node and the information of the N leaf nodes to determine information of a set of branch nodes, and creating a clock feedthrough according to the information of the source node, the information of the N leaf nodes, and the information of the set of branch nodes.

The invention discloses a bottom-to-top clock tree synthesis method and system. The method comprises the following steps: inserting a logic unit to be inserted between a driver and a load connected with the driver; and judging whether the clock tree in which the logic unit is inserted meets design rule constraints or not, if so, completing insertion of the logic unit between the driver and the load connected with the driver, and if not, taking the inserted logic unit as a new load, and starting execution from insertion of the logic unit to be inserted between the driver and the load connected with the driver. When the logic units are inserted, the logic units are inserted layer by layer from bottom to top, leaf nodes which need to share clock paths as far as possible due to clock skew, common control of key paths and other reasons can be divided into the same sub-trees as soon as possible at the bottom layer, power consumption and occupied chip area are reduced, and the cost is reduced. The problem that a common path of leaf nodes of a critical path is too short is avoided, and the method can be suitable for the situation of clock tree synthesis of a buffer, a phase inverter or a mixture of the buffer and the phase inverter.

A clock tree comprehensive optimization method, device and product based on machine learning, the clock tree comprehensive optimization method comprising: obtaining a trained replacement unit prediction model, the trained replacement unit prediction model being used for predicting an optimal replacement unit corresponding to a to-be-optimized unit in a clock tree synthesis; and integrating the trained replacement unit prediction model into an EDA tool so as to call the trained replacement unit prediction model through the EDA tool integrated with the trained replacement unit prediction model to predict an optimal replacement unit corresponding to the to-be-optimized unit in the clock tree synthesis. The clock tree comprehensive optimization method aims to reduce the operation time for replacing the selected unit with the same type of unit with weaker driving capability in the clock tree comprehensive stage on the premise that the clock time sequence is not obviously deteriorated and the design rule violation requirement is met.