72 results about "Clock tree synthesis" patented technology

A method of cell placement and clock tree synthesis includes steps of: (a) identifying critical paths in an integrated circuit design; (b) partitioning the integrated circuit design into a timing group for each of the critical paths; (c) assigning each flip-flop in a critical path to a timing group corresponding to the critical path; (d) performing a cell placement to minimize a function of propagation delay and maximum distance between flip-flops within each timing group; and (e) constructing a clock sub-net for each timing group.

The invention discloses a processor performance optimization method based on the clock planning deviation algorithm, which comprises the following steps: the layout planning phase, the layout phase and the follow-up phase, wherein in the layout planning phase, grouping SRAM (static random access memory) according to the path relation between an SRM (shared resource module) preceding-stage or backward-stage register and multiple SRM; clock deviation planning is performed in the layout phase, and the layout phase is divided into two phases, namely before clock tree synthesis and after clock tree synthesis; before clock tree synthesis, SRAM clock delay is adjusted according to the average surplus capacity between SRAM and multiple paths of the preceding-stage or backward-stage register, and planning the clock jitter of the register by adopting the partial surplus capacity borrowing algorithm; after clock tree synthesis, handling a large number and few time sequence violations respectively by adopting the clock tree algorithm correction and the engineering change; in the follow-up phase, to handle the storage time violation after wiring, the restoring scheme based on distributed multi-scenario time sequence analysis, and combining an ECO (engineering change order) and a script is adopted.

A clock tree synthesis (CTS) tool determines how to position a hierarchy of buffers for fanning out a clock signal to clocked devices (“sinks”) within an integrated circuit (IC). The tool first clusterizes the sinks and places a lowest level fan-out buffer near each cluster. The tool then iteratively places progressively higher level buffers by clusterizing a last-placed buffer level and then placing a next higher level buffer near the centroid of each lower level buffer cluster, until the tool has placed buffers at a mid-level for which variation in path distances between that level and a next higher buffer level exceeds a predetermined limit. The CTS tool then places a top level buffer at the centroid of the mid-level buffers, divides the layout into partitions, each containing a similar number of mid-level buffers, and then places a second-highest level buffer in each partition. The CTS iteratively places each next lower buffer level by dividing each partition into progressively smaller partitions and placing progressively lower level buffers in each smaller partition until it places buffers at a level having sufficient number of buffers to drive the mid-level buffers.

A method for low power clock tree synthesis using buffer insertion, removal and resizing for high-speed VLSI design is proposed. The developed tool can be embedded in the existing clock tree synthesis design flow to ensure satisfying both the specifying database constrains and the clock skew constrains. For a given clock tree netlist, the location information of buffers, the parameters of wires and the buffers' timing and power library are all included. The buffer delay and wire delay of the clock tree are calculated first. Then the feasible solution is solved if the input netlist is not feasible for the given constrains. Finally, a modified low power clock tree netlist, which satisfies the timing specifications, is obtained using our proposed method.

An analysis part analyzes a description of a logic design; an extraction part extracts a part of the description of the logic design having a fan-out number beyond a predetermined value, based on the analysis; an insertion part inserts a buffer for clock tree synthesis for performing an adjustment on the part extracted by said extracting part, the adjustment being performed at a time of subsequent layout process; and a logic synthesis part performs logic synthesis on the description of the logic design obtained after the insertion performed by said inserting part.

A macro-cell is incorporated into an integrated circuit (IC) design to describe a fixed arrangement of cells to be included in the IC. The IC includes a clock tree for delivering a clock signal from its root to all clocked devices (sinks) within the IC external to the macro-cell, and to a root of a clock tree subtree included within the macro-cell for delivering the clock signal from its root to sinks residing within the macro-cell. A model of the subtree depicts the maximum and minimum delays of the clock signal's rising and falling edges between the subtree root and the sinks within the macro-cell as functions of the clock signal's rising and falling edge transition times as they arrives at the subtree root and also as functions of the relative amount of delay the rising and falling edges experience as they pass from the clock tree root to the subtree root. A clock tree synthesis tool uses the subtree model to determine the maximum and minimum rising and falling edge path delays though the subtree when estimating the maximum and minimum amounts by which the clock tree delays the clock signal's rising and falling edges as they pass from the clock tree root to any sink of the IC.

A clock design apparatus includes a delay time adjusting section, a prohibition specifying section and a clock tree synthesis section. The delay time adjusting section is configured to adjust signal delay time of signal propagation paths on a semiconductor integrated circuit to be designed. The prohibition specifying section is configured to specify a part of the signal propagation paths as a circuit prevented from being changed. The clock tree synthesis section is configured to synthesize a clock tree of the semiconductor integrated circuit in accordance with the specification made by the prohibition specifying section.

The invention discloses a clock tree synthesis method and a computer-readable storage medium. The method comprises a step of obtaining clock latency of registers which have timing check with a top-level module in sub-modules after the clock tree balance of the sub-modules in a full chip is completed, and calculating several statistical values of the grabbed clock latency, and a step of selectinga statistical value of the clock latency and carrying out back-annotation of the statistical value to the full chip, and guiding the full clock to carry out global clock tree balance. According to the method and the computer-readable storage medium, by obtaining clock latency values of the registers at the interfaces of the sub-modules and the top-level module in the sub-modules and carrying outback-annotation of the values to the full chip to carry out global clock tree balance, the clock latency of a large number of unrelated registers that have no logical interaction with the top-level module in the sub-modules is omitted, the accuracy of a back annotation value is improved, thus a large number of timing violations do not occur at the interfaces of the sub-modules and the top-level module, the speed of the timing convergence of the full chip is increased, and a design cycle is shortened.

Regions G1 to G8 each including a predetermined number of flip-flops (FF) are divided into two groups. This dividing is performed so that the number of data connection channels intersected by a boundary is minimized. In the case of intersection of two data connection channels (A1, A2), the number of data connection channels intersected by the boundary is two, the minimum number. After grouping of all the regions (G1 to G4, G5 to G8), clock tree synthesis (CTS) is performed. If clock forming is performed in this way, the increase in clock skew on an actual device can be limited and on-chip variation resistance can be increased.

Gating clocks has been a widely adopted technique for reducing dynamic power. The clock gating strategy employed has a huge bearing on the clock tree synthesis quality along with the impact to leakage and dynamic power. This invention is a technique for clock gate optimization to aid the clock tree synthesis. The technique enables cloning and redistribution of the fanout among the existing equivalent clock gates. The technique is placement aware and hence reduces overall clock wire length and area. The technique involves employing the k-means clustering algorithm to geographically partition the design's registers. This invention improves the clock tree synthesis quality on a complex design.

A method of designing the layout for an IC is provided, which eliminates the signal line re-routing process and which optimizes the relative skew of the clock signal. This method comprises the steps of: (a) determining prohibited areas in each of stacked wiring layers; the prohibited areas causing an obstacle to determine layout of signal lines in each of the wiring layers if clock lines are defined to intersect the prohibited areas; (b) defining layout of clock lines in each of wiring layers through a Clock Tree Synthesis process in such a way that none of the clock lines intersects the prohibited areas; and (c) defining layout of signal lines in each of the wiring layers after the step (b). Preferably, prohibited area information about a primitive cell including at least one of the prohibited areas is provided, where the prohibited area information is used in the CTS process in the step (b).

A method and apparatus for rapidly selecting types of buffers which are inserted in the clock tree for high-speed VLSI design is disclosed. The developed tool can be embedded in the existing clock tree synthesis design flow to ensure minimizing the clock delay and satisfying the clock skew constrains. Given the clock tree netlist, inserted buffers locations information, wires electrical parameters and buffers timing library, the components delay (buffer delay and wire delay) of the clock tree can be calculated first. Then, for each I/O pin, the path delay, clock delay and clock skew can be obtained. Finally using the proposed method, a modified clock tree netlist which satisfying the timing specifications can be constructed.

The invention discloses an integrated circuit back end design system. The system comprises an environment building module, a design task module, a layout planning design module, an automatic unit placement optimization module, a clock tree synthesis optimization module, a global routing optimization module, a functional equivalence checking module, a timing sign-off design module, a voltage attenuation design module and a physical verification module. According to the integrated circuit back end design system, design sequence standardization is carried out on the main design links of the backend design, so that the design has good universality, thus the design threshold of the back end design is greatly reduced, the labor cost is reduced, the design efficiency is improved, and the designquality is ensured.