Processor performance optimization method based on clock planning deviation algorithm

Abstract

The invention discloses a processor performance optimization method based on the clock planning deviation algorithm, which comprises the following steps: the layout planning phase, the layout phase and the follow-up phase, wherein in the layout planning phase, grouping SRAM (static random access memory) according to the path relation between an SRM (shared resource module) preceding-stage or backward-stage register and multiple SRM; clock deviation planning is performed in the layout phase, and the layout phase is divided into two phases, namely before clock tree synthesis and after clock tree synthesis; before clock tree synthesis, SRAM clock delay is adjusted according to the average surplus capacity between SRAM and multiple paths of the preceding-stage or backward-stage register, and planning the clock jitter of the register by adopting the partial surplus capacity borrowing algorithm; after clock tree synthesis, handling a large number and few time sequence violations respectively by adopting the clock tree algorithm correction and the engineering change; in the follow-up phase, to handle the storage time violation after wiring, the restoring scheme based on distributed multi-scenario time sequence analysis, and combining an ECO (engineering change order) and a script is adopted.

Description

technical field [0001] The invention relates to the field of processor performance optimization, in particular to a processor performance optimization method based on a clock planning deviation algorithm. Background technique [0002] The rapid development of semiconductor manufacturing technology has entered the nanometer era, and the integration level of SoC is increasing exponentially according to Moore's law. As the processor at the core of the SoC, its design scale is also increasing, its complexity is increasing, and its performance requirements are constantly improving. Clock skew planning has long been proposed as an effective physical design strategy to optimize processor performance. Reasonable clock skew planning can improve performance, reduce power consumption, and increase reliability. [0003] Timing convergence in integrated circuit design refers to the consistency of front-end and back-end design timing, that is, how high a frequency can the netlist given b...

AI Technical Summary

Problems solved by technology

These algorithms are still not implemented in commercial tools, and designers still tend to adopt zero clock skew design strategy

Second, clock skew planning takes a long time, especially timing analysis takes a long time

Third, in practical applications, the optimization strategies of commercial synthesis tools often limit the optimization space of clock skew planning

But so far, EDA manufacturers have not yet proposed a mature improvement plan

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