The invention relates to the field of digital
wireless communication chips, in particular to an optimized digital
wireless communication
chip system, which comprises a
radio frequency controller, and an
EEPROM, a
data cache FIFO, an SPI interface, an IO controller, an RSSI
detector, an IQ demodulator, an LNA, a mixer, a PA, a PLL, a VCO and a QFN16
package connected with the
radio frequency controller. The SPI interface is a logic main SPI interface, and is connected to the
radio frequency controller through four lines, namely a CSB, an FCSB, an SCLK and an SDIO; the IO controller comprises a logic input circuit and a logic output circuit which are connected with
chip packaging pins GPIO1, GPIO2 and GPIO3; the RSSI
detector is connected with the radio frequency controller, the IQ demodulator is connected with the radio frequency controller through an IPC channel, the LNA is directly connected to an antenna input end, the mixer is connected with the LNA and the VCO through a
chip internal shielding circuit, and the PA is connected with an antenna output end and the VCO. The board arrangement and wiring rule of chip application is greatly simplified.