The present invention relates to the field of digital
wireless communication chips, and in particular to an optimized digital
wireless communication
chip system. The
system comprises a
radio frequency controller and an
EEPROM, a
data cache FIFO, an SPI interface, an IO controller, an RSSI
detector, an IQ demodulator, an LNA, a mixer, a PA, a PLL, a VCO and a QFN16
package connected thereto. The SPI interface is a logic master SPI interface, which is connected to the
radio frequency controller via four lines of CSB, FCSB, SCLK and SDIO; the IO controller comprises a logic input and output circuit, which is connected to the
chip package pins GPIO1, GPIO2 and GPIO3; the RSSI
detector is connected to the
radio frequency controller, the IQ demodulator is connected to the radio frequency controller via an IPC channel, the LNA is directly connected to the antenna input end, the mixer is connected to the LNA and the VCO via a
chip internal shielded line, and the PA is connected to the antenna output end and the VCO. The present invention greatly simplifies the
layout and wiring rules of chip applications.