89 results about "Physical verification" patented technology

An automated design for manufacturability platform for integrated physical verification and manufacturing enhancement operations. Given original layouts and one or more associated resolution-enhanced layouts, intermediate resolution-enhancement state layouts are reconstructed, and selective localized resolution-enhancement reconfigurations, modifications, and/or perturbations are introduced on any existing enhancements in order to improve manufacturability and yield.

An automated manufacturing control system is proposed to greatly reduce the human interaction relative to the data transfer, physical verification and process control associated with the movement of components, tooling and operators in a manufacturing system. This is achieved by the use of data carriers which are attached to the object(s) to be traced. These data carriers (12) can store all the relevant identification, material and production data to required by the various elements, e.g. stations, of the manufacturing system. Various readers, integrated with controllers and application software, are located at strategic points of the production area, including production machines and storage areas, to enable automatic data transfer and physical verification that the right material is at the right place at the right time, using the right tooling.

An automated design for manufacturability platform which provides integrated physical verification and manufacturing enhancement operations. The platform uses an efficient data structure capable of handling and manipulating both layout circuit and geometry characteristics, which permits a wide range of operations such as timing analysis, design-rule checking and optical proximity corrections on a single platform. This feature eliminates the need to translate layout representations between various tools without the requirement of using a common database. Moreover, the platform's common user interface enables encapsulated information exchange between the design and the manufacturing teams, permiting early consideration of manufacturing distortion or enhancement impact on circuit performance.

A sub-circuit based extraction method which extracts a multi-finger MOS transistor directly as a sub-circuit is described. By adding three marking layers, the method provides the layout extracted netlist with a complete list of device geometric parameters corresponding to the device properties as presented in the sub-circuit model based schematic netlist. By performing a layout-versus-schematic comparison based on all geometric parameters extracted, the layout checking is performed in a complete and accurate way where each device parameter is checked against the corresponding design schematic. This complete and accurate geometric parameter comparison enhances the confidence level of the layout physical verification.

The present invention relates generally to systems and methods that facilitate the prevention of fraud occurring in connection with credit cards, debit cards, smart cards and other payment cards that are used in transactions involving goods sold by a seller, delivered by a shipper, and purchased by a buyer. Specifically, the present invention provides systems and methods that allow for physical verification of a payment card (e.g., credit card) upon delivery of goods that are purchased in the context of a remote transaction between a buyer and a seller, including, for example, goods that are ordered via phone, mail order, fax or the Internet.

Some embodiments provide a system for managing violations during physical verification. The system may identify a design-rule-check (DRC) violation by applying a set of DRC rules to a layout. The system can then receive an error classification from the user which specifies how the DRC violation is to be handled. Next, the system can store the DRC violation, the user-selected error classification, and a user identifier associated with the user in a database. If the user is not authorized to approve the error classification, the database can indicate that the error classification has not been approved. Later, a user who is authorized to approve the error classification can approve the error classification. The system can determine if a cell is known, and if so, the system can use the violations and error classifications stored in the database to speed up the verification process.

The invention discloses a consistency physical verification device of a multicore processor Cache, to provide a consistency physical verification device with low cost and high efficiency for the multicore processor Cache. Based on a field programmable gate-array (FPGA) verification platform of a single core processor, the device is embedded with a virtual processor core (103) to verify the consistency of the multicore processor Cache. The virtual processor core (103) can imitate the multicore processor to automatically generate shared memory access request and automatically store the correctness of results. The device can verify the correctness of the consistency of the multicore processor Cache on the FPGA verification platform of a single core processor, which reduces FPGA physical verification cost of the multicore processor and improves the consistency verification efficiency of the multicore processor Cache; synchronously, using such verification method in a simulation verification can reduce the complexity of the simulation verification and increase the speed of the simulation verification.

Techniques for performing physical verification processes for stacked integrated circuit devices. An interface between a first two-dimensional integrated circuit device and a second two-dimensional integrated circuit device is identified. The design data for the identified layers in the first and second two-dimensional integrated circuit devices are then combined and physically verified as a single set of interface design data. The design data for the first two-dimensional integrated circuit device and the second two-dimensional integrated circuit device are then separately physically verified. Once the interface design data, the first two-dimensional integrated circuit device design data and the second two-dimensional integrated circuit device design data have been physically verified, the verified design can be recombined to form verified design data corresponding to a stacked integrated circuit device.

The invention provides a failure point positioning method for semiconductor power device failure analysis. The failure point positioning method comprises the following steps of: performing chemical corrosion on a metal aluminum layer covering the surface of a power device by utilizing a chemical corrosion stripping technology, completely removing the aluminum layer, and completely keeping a barrier layer below the metal aluminum layer; positioning the front side of the power device by utilizing a micro light microscope and a light beam induced resistance variation technology, simulating electric conditions under the failure conditions, electrifying by using a point needle method, simulating the electric conditions, and finding possible failure points; and performing physical verification of electronic package assembly failure analysis by utilizing the positioning result of an electronic package assembly failure analysis tool on the previous steps, and finding the final physical failure point. The failure point positioning method has the advantages that the metal aluminum layer is effectively stripped, and the integrity of the barrier layer is kept; and moreover, the positioning speed and efficiency of the semiconductor power device failure point are greatly improved, and an extremely high precision is kept.

A collaborative environment for performing physical verification processes on integrated circuit designs. Multiple physical verification results may be stored in a “unified” results database/directory (e.g., unified at least from a user's perspective), where results from various verification processes, such as Design-Rule-Check (DRC) processes, Layout-Versus-Schematic comparison (LVS) processes, Design-For-Manufacturing (DFM) processes Optical Proximity Correction (OPC) processes, and Optical Rule Check (ORC) processes are accessible from the same style of user interface, which may be a graphical user interface. The basic abilities for design team-based interactions can be equally available to each process involved in the physical verification of an integrated circuit design.

The invention discloses a debugging method of a nuclear power plant half-speed turbine monitoring system. The debugging method includes the following steps that S1, after a drawing is checked, and correct wiring of a control cabinet is guaranteed, the control cabinet is powered up, and verification of sensor characteristics is conducted by using a semi-physical verification platform; and after the control cabinet is powered up and the verification of the sensor characteristics is finished, verification of a channel below the semi-physical verification platform is conducted; S2, a sensor is installed; S3, after a measuring channel from the sensor to a display terminal is built, a monitoring instrument is adjusted by comparing a measuring value and a display value; and S4, jiggering, impulse starting and grid combining of a turbine unit are finished, and comparison of mechanical measurement and instrument control measuring value is conducted during on-load so as to verify whether unit operation requirements are met. The debugging method can solve the problem that static characteristic inspection can not be conducted before installing of the sensor, and cost is saved.

A semiconductor device verification system capable of verifying operation with great accuracy. A pattern matching verification system outputs interference pattern information. A physical verification system compiles the interference pattern information and a design rule and extracts a design rule applied to the interference pattern information. The physical verification system then refers to the design rule to verify a compared cell list and the interference pattern information. As a result, the physical verification system can perform physical verification of layout data without skipping data regarding the compared cell list.

A level shifter physical verification system identifies missing level shifters in a multi-voltage domain integrated circuit design. The system analyzes a physical layout design data file for design to identify domains and signals that cross domains, and connected nets of devices within the IC design having one or more missing level shifters.

The invention discloses a clock tree layout flow method in an integrated circuit, in particular comprising the following steps: step 1, a top layer layout; 2, physical realization of a hard module; 3,extracting the clock tree information in the hard module; 4, acquire that clock tree deviation between the hard modules; 5, insert a clock tree deviation compensating device into that top-level module T; 6, generate a top-level clock tree in that top-level module T; 7, wire generation is carried out on that signal interconnection between each hard module in the top-layer module T; 8, extracting the interface timing model of the hard module when the static timing analysis of the whole chip is carried out; 9, static timing analysis of the whole chip; Step 10: physical authentication. The invention can reduce the level of the clock tree and the difficulty of balancing the clock tree. At the same time, a clock tree deviation compensation device is proposed for this flow method, which can effectively reduce the difficulty of timing convergence between hard modules.

The invention discloses a test method for the external pressure resistance of a steel pipe for a submarine pipeline. The test method mainly includes selection of test equipment, design of a steel pipespecimen, test of the sealing performance of the steel pipe specimen, test of the external pressure resistance of the steel pipe specimen and evaluation of the external pressure resistance of the steel pipe specimen. The test method is mainly applicable to the test of the external pressure resistance of the steel pipe for the submarine pipeline under the external pressure load of surrounding environmental water, especially for the test of the external pressure resistance of a high-strength thick-walled steel pipe for a deep-sea pipeline within the water depth of 3500 meters or less. Through adoption of the method, physical verification and test analysis of the external pressure resistance of the steel pipe for the deep-sea pipeline can be realized; comprehensive performance evaluation ofindexes such as mechanical properties and appearance geometric dimensions of the steel pipe for the submarine pipeline can be realized; and the test result play an important guidance role in the design and control of indexes such as materials, wall thicknesses, mechanical properties and appearance dimensions of steel pipes for submarine pipeline projects.

The invention relates to a Virtools based multivariate data fusion virtual test display system, which comprises a data interface and processing module, a hybrid modeling and integrated module, a visual fusion display module, and a model correction module. A finite element method calculation (virtual test) and physical test methods carry out the calculation or test verification on all sub-structures, and a finite element model (virtual test model) is corrected according to physical test result data; meanwhile, a test trend indicated by the virtual test is utilized to guide the physical test to perfect the physical verification test scheme; finally, the overlapping display of comprehensive test environment of a complicated system is carried out according to a hybrid model established by a virtual test model and physical test data, and an LOD management technology is adopted in an overlapping display model, so that the overlapping display efficiency of physical field data in Virtools is improved.

The present invention relates to a time-division multiplexing technology-based networked ground-based radar semi-physical system. The system includes an X-band command and control radar semi-physical verification system, a Cobra Dane radar semi-physical verification system and an early warning radar semi-physical verification system; the three verification systems work jointly so as to simulate required battlefield environments more completely, and therefore, fidelity is high, implementation possibility is higher; and a time-division technology, semi-physical model and functional auxiliary verification module-combined method is adopted, and therefore, the costs of actually-created semi-physical equipment are decreased, a test method is simplified, and test difficulty is reduced.