Clock-tree layout flow method and clock-tree deviation compensation device in integrate circuit

Abstract

The invention discloses a clock tree layout flow method in an integrated circuit, in particular comprising the following steps: step 1, a top layer layout; 2, physical realization of a hard module; 3,extracting the clock tree information in the hard module; 4, acquire that clock tree deviation between the hard modules; 5, insert a clock tree deviation compensating device into that top-level module T; 6, generate a top-level clock tree in that top-level module T; 7, wire generation is carried out on that signal interconnection between each hard module in the top-layer module T; 8, extracting the interface timing model of the hard module when the static timing analysis of the whole chip is carried out; 9, static timing analysis of the whole chip; Step 10: physical authentication. The invention can reduce the level of the clock tree and the difficulty of balancing the clock tree. At the same time, a clock tree deviation compensation device is proposed for this flow method, which can effectively reduce the difficulty of timing convergence between hard modules.

Description

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AI Technical Summary

Benefits of technology

This technology helps improve the performance of computer systems by reducing their complexity while still being able to operate correctly with each other's components properly. It also makes it easier for software developers to develop applications that work together more efficiently without any issues or errors caused when they use different parts from one another.

Problems solved by technology

Technological Problem addressed in this patents relates to improving the efficiency and performance of electronic devices with smaller components while still maintaining their functionality even if they become larger due to advancements made over recent years. Specifically, current methods involve dividing the circuitry into smaller parts based upon logical rules rather than combining them together. Additionally, existing techniques used during synchronization may result in delays caused by signal processing times. To address these challenges, new solutions involving virtual circuits instead of real ones were proposed but previously discussed only focusing on achieving equal loads across various elements of the device's architecture.

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