Failure point positioning method for semiconductor power device failure analysis

A power device, failure analysis technology, applied in the direction of instruments, measuring devices, measuring electricity, etc., can solve the problems of incomplete detection and analysis, unable to locate all failure points, low positioning accuracy, etc., to simplify the physical verification work, high precision, The effect of speed and efficiency

Inactive Publication Date: 2013-01-02
SHANGHAI FALAB TEST
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] In order to solve the problem that the current failure point analysis and positioning method has low positioning accuracy or incomplete detection and analysis, which leads to the inability to locate all failure points, the present invention proposes the following technical solutions:

Method used

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Embodiment Construction

[0021] The preferred embodiments of the present invention are described in detail below, so that the advantages and features of the present invention can be more easily understood by those skilled in the art, so as to define the protection scope of the present invention more clearly.

[0022] The chip in this specific embodiment is a 75V semiconductor switch controller. During detection, it was found that the gate and source of a field effect transistor on the switch controller were short-circuited abnormally, so it was determined that there was a problem with the field effect transistor.

[0023] First, prepare an appropriate amount of hot phosphoric acid at 250°C, and immerse the field effect tube in hot phosphoric acid. The metal aluminum layer on the surface of the field effect tube reacts violently with hot phosphoric acid to generate a large number of bubbles. Wait for 20 to 30 seconds, and the bubbles disappear. At the end of the reaction, the field effect tube was immed...

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Abstract

The invention provides a failure point positioning method for semiconductor power device failure analysis. The failure point positioning method comprises the following steps of: performing chemical corrosion on a metal aluminum layer covering the surface of a power device by utilizing a chemical corrosion stripping technology, completely removing the aluminum layer, and completely keeping a barrier layer below the metal aluminum layer; positioning the front side of the power device by utilizing a micro light microscope and a light beam induced resistance variation technology, simulating electric conditions under the failure conditions, electrifying by using a point needle method, simulating the electric conditions, and finding possible failure points; and performing physical verification of electronic package assembly failure analysis by utilizing the positioning result of an electronic package assembly failure analysis tool on the previous steps, and finding the final physical failure point. The failure point positioning method has the advantages that the metal aluminum layer is effectively stripped, and the integrity of the barrier layer is kept; and moreover, the positioning speed and efficiency of the semiconductor power device failure point are greatly improved, and an extremely high precision is kept.

Description

technical field [0001] The invention relates to a failure point location technology for failure analysis of semiconductor power devices, in particular to a failure point location method combined with chemical corrosion technology. Background technique [0002] Due to the special vertical transistor structure design of semiconductor power devices, the surface of the chip is covered with a metal layer (generally an aluminum layer) of 4um or greater, while the back side is used as the back electrode, and the outermost layer is also covered with a metal layer of more than 1-3um. The metal layer (usually titanium / nickel / silver stack), and this structure makes it very difficult to accurately locate the failure point once the semiconductor power tube fails. Because whether it is the low-light microscope technology for capturing the composite luminescence of the electron-hole pair at the leakage point, or the beam-induced resistance change technology for capturing the abnormal resis...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/02
Inventor 张涛
Owner SHANGHAI FALAB TEST
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