Consistency physical verification device of multicore processor Cache

A multi-core processor, consistent technology, applied in the direction of electrical digital data processing, special data processing applications, instruments, etc., can solve the problems of increasing the development cycle of multi-core processors and the difficulty of inheriting the verification results of single-core processors

Active Publication Date: 2009-06-03
上海高性能集成电路设计中心
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Problems solved by technology

However, due to the essential difference in system architecture between multi-core processors and single-core processors, this also determines that the software simulation environment, test incentives, and physical hardware simulation platforms of single-core processors cannot be directly applied to multi-co

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  • Consistency physical verification device of multicore processor Cache
  • Consistency physical verification device of multicore processor Cache
  • Consistency physical verification device of multicore processor Cache

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Embodiment Construction

[0014] Such as figure 1 Shown, the present invention is used for the device of multi-core processor Cache consistency physical verification and comprises processor FPGA realization (101), external system (105) two components, the processor FPGA realization (101) and external system (105) are connected by high-density slots. Wherein, system control logic and storage access control logic are implemented on the external system (105); a virtual multi-core processor is implemented on the processor FPGA implementation (101), including the following components: real processor core (102), virtual processor Core (103), secondary cache, inter-core coherence control unit and system interface control unit (104); real processor core (102) and virtual processor core are all connected with secondary cache and inter-core coherence control unit (104) are connected, wherein the virtual processor core (103) is a highly abstract behavioral model of the real processor core (102), and the function...

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Abstract

The invention discloses a consistency physical verification device of a multicore processor Cache, to provide a consistency physical verification device with low cost and high efficiency for the multicore processor Cache. Based on a field programmable gate-array (FPGA) verification platform of a single core processor, the device is embedded with a virtual processor core (103) to verify the consistency of the multicore processor Cache. The virtual processor core (103) can imitate the multicore processor to automatically generate shared memory access request and automatically store the correctness of results. The device can verify the correctness of the consistency of the multicore processor Cache on the FPGA verification platform of a single core processor, which reduces FPGA physical verification cost of the multicore processor and improves the consistency verification efficiency of the multicore processor Cache; synchronously, using such verification method in a simulation verification can reduce the complexity of the simulation verification and increase the speed of the simulation verification.

Description

technical field [0001] The invention relates to a device for physical verification of multi-core processors, in particular to the correctness verification of Cache consistency of multi-core processors. technical background [0002] With the development of microprocessors, traditional processor design and manufacturing methods have been difficult to achieve performance breakthroughs, single-core microprocessors are increasingly difficult to meet application requirements, and microprocessors have entered the multi-core era. From single-core to multi-core, it is not just a simple increase in the number of processor cores, the development of multi-core processors poses a huge challenge to the processor architecture, the overall computer architecture, operating systems and application software. With the increase of multi-core processor structure complexity, how to ensure the correctness of multi-core processor design, especially the correctness of multi-core processor Cache coher...

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Application Information

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IPC IPC(8): G06F17/50
Inventor 李强吴志勇
Owner 上海高性能集成电路设计中心
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