A device for physical verification of multi-core processor cache consistency

A multi-core processor, consistent technology, applied in electrical digital data processing, special data processing applications, instruments, etc., can solve the problems of increasing the development cycle of multi-core processors and the difficulty of inheriting the verification results of single-core processors.

Active Publication Date: 2011-12-14
上海高性能集成电路设计中心
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AI Technical Summary

Problems solved by technology

However, due to the essential difference in system architecture between multi-core processors and single-core processors, this also determines that the software simulation environment, test incentives, and physical hardware simulation platforms of single-core processors cannot be directly applied to multi-core processing. The functional verification of the processor requires a lot of modification, and some environments even need to be rebuilt. In this way, it is difficult to inherit the verification results of the single-core processor, which greatly increases the development cycle of the multi-core processor.

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  • A device for physical verification of multi-core processor cache consistency
  • A device for physical verification of multi-core processor cache consistency
  • A device for physical verification of multi-core processor cache consistency

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Embodiment Construction

[0016] Such as figure 1 Shown, the present invention is used for the device of multi-core processor Cache consistency object verification and comprises single-core processor FPGA realization (101), two components of external system (105), and single-core processor FPGA realizes (101) and external system (105) are connected through high-density slots. Wherein, system control logic and storage access control logic are implemented on the external system (105); a virtual multi-core processor is implemented on the single-core processor FPGA implementation (101), including the following components: real processor core (102), virtual Processor core (103), L2 cache, inter-core coherence control unit and system interface control unit (104); real processor core (102) and virtual processor core are all connected to L2 cache and inter-core coherence The control components (104) are connected, wherein the virtual processor core (103) is a highly abstract behavioral model of the real proc...

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Abstract

The invention discloses a device for physical verification of multi-core processor Cache consistency. Its purpose is to provide a physical verification device with low overhead and high efficiency for multi-core processor Cache consistency. This device is based on the field programmable gate array (Field Programmable Gate-Array, FPGA for short) verification platform of the single-core processor, and a virtual processor core (103) is embedded to realize the purpose of verifying the consistency of the multi-core processor Cache . The virtual processor core (103) can imitate a multi-core processor to automatically generate a shared memory access request and automatically ensure the correctness of the result. Using this device can verify the correctness of multi-core processor Cache consistency on the single-core processor FPGA verification platform, which reduces the cost of FPGA physical verification of multi-core processors, thereby improving the verification efficiency of multi-core processor Cache consistency, and at the same time , using this verification method in simulation verification can also reduce the complexity of simulation verification and increase the speed of simulation verification.

Description

technical field [0001] The invention relates to a device for physical verification of multi-core processors, in particular to the correctness verification of Cache consistency of multi-core processors. technical background [0002] With the development of microprocessors, traditional processor design and manufacturing methods have been difficult to achieve performance breakthroughs, single-core microprocessors are increasingly difficult to meet application requirements, and microprocessors have entered the multi-core era. From single-core to multi-core, it is not just a simple increase in the number of processor cores, the development of multi-core processors poses a huge challenge to the processor architecture, the overall computer architecture, operating systems and application software. With the increase of multi-core processor structure complexity, how to ensure the correctness of multi-core processor design, especially the correctness of multi-core processor Cache cohe...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
Inventor 李强吴志勇
Owner 上海高性能集成电路设计中心
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