Clock tree synthesis method and computer-readable storage medium

Abstract

The invention discloses a clock tree synthesis method and a computer-readable storage medium. The method comprises a step of obtaining clock latency of registers which have timing check with a top-level module in sub-modules after the clock tree balance of the sub-modules in a full chip is completed, and calculating several statistical values of the grabbed clock latency, and a step of selectinga statistical value of the clock latency and carrying out back-annotation of the statistical value to the full chip, and guiding the full clock to carry out global clock tree balance. According to the method and the computer-readable storage medium, by obtaining clock latency values of the registers at the interfaces of the sub-modules and the top-level module in the sub-modules and carrying outback-annotation of the values to the full chip to carry out global clock tree balance, the clock latency of a large number of unrelated registers that have no logical interaction with the top-level module in the sub-modules is omitted, the accuracy of a back annotation value is improved, thus a large number of timing violations do not occur at the interfaces of the sub-modules and the top-level module, the speed of the timing convergence of the full chip is increased, and a design cycle is shortened.

Description

technical field [0001] The invention relates to the technical field of chip design, in particular to a clock tree synthesis method and a computer-readable storage medium. Background technique [0002] In digital integrated circuits, the clock signal, as the timing reference of the entire chip, plays a vital role in the performance and stability of the chip. Timing closure is one of the most important tasks in digital integrated circuit design. As integrated circuit design enters the deep sub-micron era, the scale of the chip continues to increase, the design becomes more and more complex, and the difficulty of timing convergence becomes more and more difficult. [0003] Hierarchical design is the most commonly used design method for integrated circuit chips. In this design method, the chip to be designed is divided into many sub-modules. Each sub-module is designed separately and then called by the top-level module. This design The method divides the huge and complex desig...

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Problems solved by technology

[0003] Hierarchical design is the most commonly used design method for integrated circuit chips. In this design method, the chip to be designed is divided into many sub-modules. Each sub-module is designed separately and then called by the top-level module. This design The method divides the huge and complex design into several partitions (Partition) in the physical design stage, and performs clock tree balancing on each sub-module separately. The whole chip only needs to pay attention to the clock delay of the register at the interface of the sub-module, which can Significantly improve design cycle times and localiz...

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