A clock tree synthesis method and computer-readable storage medium

Abstract

The invention discloses a clock tree synthesis method and a computer-readable storage medium, comprising: after the sub-modules in the full chip complete the clock tree balance, obtain and check the clock delay of the register in the sub-module with the timing check of the top-level module, and calculate Capture several statistical values ​​of clock delay; select a statistical value of clock delay to reverse mark to the whole chip, and guide the whole chip to perform global clock tree balance. The present invention obtains the clock delay value of the register at the interface between the sub-module and the top-level module in the sub-module, reverses the whole chip for global clock tree balance, and ignores the clock delay of a large number of irrelevant registers in the sub-module that have no logical interaction with the top-level module , which improves the accuracy of back-labeled values, so that there will not be a large number of timing violations at the interface between sub-modules and top-level modules, speeding up the speed of full-chip timing convergence, and shortening the design cycle.

Description

technical field [0001] The invention relates to the technical field of chip design, in particular to a clock tree synthesis method and a computer-readable storage medium. Background technique [0002] In digital integrated circuits, the clock signal, as the timing reference of the entire chip, plays a vital role in the performance and stability of the chip. Timing closure is one of the most important tasks in digital integrated circuit design. As integrated circuit design enters the deep sub-micron era, the scale of the chip continues to increase, the design becomes more and more complex, and the difficulty of timing convergence becomes more and more difficult. [0003] Hierarchical design is the most commonly used design method for integrated circuit chips. In this design method, the chip to be designed is divided into many sub-modules. Each sub-module is designed separately and then called by the top-level module. This design The method divides the huge and complex desig...

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Problems solved by technology

[0003] Hierarchical design is the most commonly used design method for integrated circuit chips. In this design method, the chip to be designed is divided into many sub-modules. Each sub-module is designed separately and then called by the top-level module. This design The method divides the huge and complex design into several partitions (Partition) in the physical design stage, and performs clock tree balancing on each sub-module separately. The whole chip only needs to pay attention to the clock delay of the register at the interface of the sub-module, which can Significantly improve design cycle times and localize timing issues

[0004] However, the existing digital design implementation (Encounter Digital Implementation, EDI) tool reports the clock delay of all registers in the sub-module, and provides the maximum value and minimum value of the clock delay, and the statistical data is different from the real clock delay of the register. A certain deviation, resulting in the distorted value of the clock delay to the top layer, resulting in the clock delay of the global clock tree balance of the whole chip being different in length between the full-chip register and the sub-module register, and a large number of timing violations occur

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