Multi-die fpga designed based on signal delay balance technology

Abstract

This application discloses a multi-die FPGA designed based on signal delay balance technology, which relates to the field of FPGA technology. Several FPGA dies on the chip, the silicon stack connection point built in the die is connected to the lead-out end of the connection point through the top-layer metal wire with a predetermined winding structure in the RDL layer, and the lead-out end of the connection point is then passed through two directions in the silicon connection layer. The cross-die connection can be connected to other dies to realize the two-dimensional interconnection and communication between the dies. This cascading structure supports the cascading of multiple small-scale and small-area dies to realize large-scale and large-area FPGAs. Products, reduce processing difficulty, improve chip production yield; by adjusting the winding distance of the top metal wire, it can efficiently achieve cross-die signal delay balance, accelerate design timing convergence, and help improve resource layout flexibility in applications.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a multi-die FPGA designed based on signal delay balance technology. Background technique [0002] FPGA (Field Programmable Gate Array, Field Programmable Logic Gate Array) is a hardware programmable logic device. In addition to being used in mobile communications, data centers and other fields, it is also widely used in prototype verification in integrated circuit design, which can effectively verify The correctness of the circuit function, while speeding up the circuit design speed. Prototype verification requires the use of programmable logic resources inside the FPGA to implement circuit design. With the continuous increase in the scale of integrated circuits and the realization of complex functions, the demand for the number of programmable logic resources in FPGAs continues to increase. Subsequent technology development and demand As the number of FPGA programmable r...

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Problems solved by technology

However, the above two patents are limited by the defects of the chip itself and the structural design. Both of them can only interconnect two adjacent IC dies arranged side by side, and can only realize signal interconnection in a single direction. The limitations are very large, and due to the limitations of the structure, the signal delay of the device is difficult to design and adjust, and it is actually difficult to meet the complex circuit requirements of large-scale integrated circuits

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