Multi-die FPGAs with balanced latency using active silicon connection layers

Abstract

This application discloses a multi-die FPGA that utilizes an active silicon connection layer to balance the delay, and relates to the field of FPGA technology. For several FPGA dies on the connection layer, the built-in silicon stack connection point of the FPGA die is connected to the lead-out end of the connection point, and the lead-out end of the connection point can be connected across the die in two directions in the active silicon connection layer. Connect to other dies to achieve two-dimensional interconnection and communication between dies; while the active devices arranged inside the silicon connection layer can flexibly adjust the cross-chip signal delay to achieve multi-die FPGA cross-chip signal delay balance and speed up Timing convergence of the design, this cascading structure supports cascading of multiple small-scale and small-area bare chips to realize large-scale and large-area FPGA products, reducing processing difficulty and improving chip production yield.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a multi-die FPGA which utilizes an active silicon connection layer to balance delay. Background technique [0002] FPGA (Field Programmable Gate Array, Field Programmable Logic Gate Array) is a hardware programmable logic device. In addition to being used in mobile communications, data centers and other fields, it is also widely used in prototype verification in integrated circuit design, which can effectively verify The correctness of the circuit function, while speeding up the circuit design speed. Prototype verification requires the use of programmable logic resources inside the FPGA to implement circuit design. With the continuous increase in the scale of integrated circuits and the realization of complex functions, the demand for the number of programmable logic resources in FPGAs continues to increase. Subsequent technology development and demand As the number of FP...

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Problems solved by technology

However, the above two patents are limited by the defects of the chip itself and the structural design. Both of them can only interconnect two adjacent IC dies arranged side by side, and can only realize signal interconnection in a single direction. The limitations are very large, and due to the limitations of the structure, the signal delay of the device is difficult to design and adjust, and it is actually difficult to meet the complex circuit requirements of large-scale integrated circuits

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