A Timing Budget Method Considering Distance and Clock

A timing and clock technology, applied in the field of hierarchical physical design, can solve problems affecting the design cycle and hindering the progress of physical design of sub-modules, etc.

Active Publication Date: 2017-12-15
NAT UNIV OF DEFENSE TECH
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  • Description
  • Claims
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Problems solved by technology

A reasonable timing budget is conducive to the convergence of the design, on the contrary, an unreasonable timing budget will hinder the progress of the physical design of the sub-module, thereby affecting the entire design cycle

Method used

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  • A Timing Budget Method Considering Distance and Clock
  • A Timing Budget Method Considering Distance and Clock
  • A Timing Budget Method Considering Distance and Clock

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Embodiment Construction

[0097]The present invention will be further described in detail below in conjunction with specific embodiments and accompanying drawings.

[0098] refer to Figure 7 , is the flow chart of the timing budget method considering distance and clock for the present invention, the present invention comprises the following steps:

[0099] The first step is to determine the process node and the metal layers used. For a given process and metal layer, the repeater insertion method can make the interconnection delay linear with the length of the interconnection line. The interconnection delay α per unit length can be obtained by the following calculation method.

[0100] 1.1 Obtain the process node and the total number of metal layers M that can be used max .

[0101] 1.2 Select the first with the first The layer metal acts as the horizontal and vertical trace metal layers. in for right the rounding of for right rounding of .

[0102] 1.3 Get the first with the first ...

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Abstract

Aiming at the roughness and limitations of the timing budget method with the shortest boundary and the timing budget method based on logic depth in hierarchical physical design, the present invention provides a timing budget method considering distance and clock. This method fully considers the physical distance between two modules and the impact of clock skew on the timing of cross-module paths. By carefully analyzing the physical locations of module ports and related boundary registers and the logical depth of cross-module paths, and according to the interconnection Line delay calculation, logic depth ratio calculation, and clock skew estimation are used to obtain more accurate and reasonable timing budget values ​​for each module port, thereby reducing the number of iterations of cross-module path timing optimization and accelerating chip design. Timing closure in .

Description

technical field [0001] The invention relates to a timing budget method in integrated circuit back-end physical design, especially for hierarchical physical design. Background technique [0002] Timing closure is the key to today's chip design, and it is also the biggest challenge. In hierarchical design, since the physical design of the top layer and each sub-module is carried out in parallel, a key issue is to ensure the consistency of the timing convergence of the sub-modules and the timing convergence of the top layer. A better timing budget is hierarchical An important prerequisite for fast closure and consistency of physical design timing. A reasonable timing budget is conducive to the convergence of the design, on the contrary, an unreasonable timing budget will hinder the progress of the physical design of the sub-module, and then affect the entire design cycle. How to give a reasonable timing budget according to the actual situation becomes the key to hierarchical ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
Inventor 刘祥远郭阳刘必慰李振涛陈书明詹武胡春媚梁斌池雅庆陈建军
Owner NAT UNIV OF DEFENSE TECH
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