60 results about "FPGA prototype" patented technology

The present application relates to the technical field of chip verification, and relates to a software and hardware collaborative simulation verification platform for accelerating verification and positioning of a smart network interface card chip. The platform comprises: a host side QEMU virtual machine, which simulates a hardware device, sends an IO request, responds to the IO request, and calls a device driving program to implement driving execution of a host side hardware device; a host side thread adapter, which converts a multi-thread processing program of the host side QEMU virtual machine into a single-thread processing program; an UVM verification platform, which performs simulation reproduction of FPGA prototype verification of the smart network interface card chip to generate a simulation waveform and a simulation log; a network side data stream adapter, which performs data type conversion on an Ethernet message; and a network side data packet transceiver, which performs message legitimacy check on the Ethernet message returned by the network side data stream adapter. The platform of the present application can improve the problem positioning speed and the chip verification efficiency, shorten the overall chip development period, and improve the chip quality.

The invention relates to a software and hardware SOC (System On Chip) verification system and method based on EDA (Electronic Design Automation) and an FPGA (Field Programmable Gate Array), and belongs to the field of SOC chip verification. The software part comprises an SOC UVM TESTBENCH SOC verification platform, a disk network disk and a T CP protocol client side; and the hardware part mainly comprises a TCP (Transmission Control Protocol) SERVER protocol server side and a SOCTOP (System On Chip Over Programmable). The method is characterized in that advantages of EDA verification and FPGA prototype verification are combined, cross-platform accelerated verification of the SOC chip is realized, the verification period of the chip is shortened, and the verification quality of the chip is improved.

The invention relates to the technical field of chip design simulation verification, in particular to a memory type dynamic determination method for prototype verification and hardware simulation, and the method comprises the steps: carrying out sub-design division according to the module level of each module in a user netlist in combination with a first resource threshold sequence corresponding to an FPGA (Field Programmable Gate Array), and fitting the design logic clustering characteristics; according to the method, the hardware segmentation requirements of cross-sub-design interconnection and adaptation to multi-FPGA prototype verification are reduced, the layout and wiring difficulty is reduced, the performance and frequency of the FPGA are effectively improved, storage type allocation is realized according to the first target conversion rate and the second target conversion rate of the object and the target memory type, and the storage efficiency is improved. Relative balance and independence of various kinds of memory resources are achieved in the sub-design as much as possible, the number of FPGA chips needed for achieving the sub-design is reduced, and equivalently, the performance of the FPGA is improved.

The present invention relates to the field of chip verification technology, and in particular to a debugging method, electronic device, and medium for chip FPGA prototype verification. The method comprises: step S1, obtaining simulation verification code for a chip to be verified; step S2, generating an FPGA prototype verification system; step S3, configuring the initial state of the FPGA prototype verification system, sending stimulus data to an input port of the FPGA prototype verification system, performing chip FPGA prototype verification, and transferring the stimulus data, clock data, and status data received by the input port to a storage module; step S4, when the FPGA prototype verification system runs to a target trigger point, obtaining target debug data from the storage module; and step S5, injecting the target debug data back into the RTL simulation model according to timing for debugging. The present invention improves the efficiency and accuracy of debugging for chip FPGA prototype verification.

A multi-stage FPGA routing method for optimizing time division multiplexing comprises the following steps: S1: collecting an FPGA set, an FPGA connection pair set, a net set and a net group set; S2: acquiring a routing topology of each net according to the FPGA set, the FPGA connection pair set, the net set and the net group set under the condition where TRs are not assigned; S3: assigning a corresponding TR to each edge of each net according to different delay of each net group; and S4: performing TR reduction and edge validation cyclically, iteratively optimizing net groups with TR being greater than a preset value until iteration end conditions are met, so as to obtain an optimal routing result. The multi-stage FPGA routing method may optimize the delay of inter-chip signals of a multi-FPGA prototype system and guarantee the routability of the multi-FPGA prototype system.

The present invention provides a method, system, device, and storage medium for rapid debugging of FPGA prototype verification. The method includes: adding debugging function codes that can be turned on or off through macro definitions during module design; developing general debugging modules for FPGA design software including breathing light control, AXI4 bus master behavior model control, AHB bus master behavior model control, AXI4 bus and AHB bus control channel and monitoring channel enabling control, and monitoring IP; transplanting the debugging function codes to the FPGA prototype verification platform, integrating the general debugging modules into the debugging function codes, and modifying the macro definitions to implement monitoring of the AXI4 bus or the AHB bus; and using the FPGA design software to synthesize the transplanted debugging function codes to generate verification files, and downloading the verification files to the FPGA prototype verification platform for verification. The present invention improves the debugging efficiency and reduces the time cost of re-synthesizing for the signals to be captured.

The application relates to an FPGA prototype verification method and system of a smart meter chip, and belongs to the field of integrated circuit testing and electric power metering. The method aims to solve the problems of ASIC design transplantation to an FPGA platform, large difference between a verification environment and a real power grid, and lack of a real-time closed-loop verification mechanism. A technical scheme efficiently transplants the design to the FPGA by optimizing ASIC front-end synthesis constraints and adopting a netlist-level IP replacement strategy; a hardware-in-the-loop system is constructed, which comprises a real power grid signal source, a separation device simulation front end, an FPGA verification board, a high-precision standard electric energy meter and a host computer. The system can generate a real power grid excitation and realize synchronous collection of prototype output and the standard meter, real-time error analysis and dynamic adjustment of parameters, thereby forming a closed-loop verification. The application significantly improves code transplantation efficiency, provides a highly consistent real power grid verification environment, and greatly improves verification iteration and defect positioning speed.

The invention discloses a version management method, a fault detection method and a prototype version compiling system, and relates to the technical field of chip verifier.The version management method comprises the steps that after compiling is started, whether FPGA prototype version information matched with current version information of a local warehouse is contained in a version storage directory or not is searched; updating FPGA prototype version information according to a search result, wherein the FPGA prototype version information comprises current version information and a suffix version number; and generating version feature information according to the updated FPGA prototype version information, and sending the version feature information to a hardware top layer module to perform fault detection on the FPGA prototype version based on the version feature information, so that the problem that the version information cannot be known in the compiling process of the FPGA prototype verification platform can be solved, the version information can be obtained through an interface when a fault occurs, and the reliability of the FPGA prototype verification platform is improved. And whether the fault is caused by the version is judged, so that the technical effects of reducing the fault tracking and positioning difficulty and improving the verification working efficiency are achieved.

The invention discloses a clock simulation method and device, equipment and a medium, relates to the technical field of integrated circuits, is applied to a prototype verification platform, and comprises the following steps: analyzing an original design file corresponding to a register transfer level circuit to obtain file topology information of an instantiated clock module; determining a to-be-adjusted clock module selected by the user side from the instantiated clock modules, and acquiring clock configuration information input by the user side, so as to generate a clock constraint file according to the clock configuration information; replacing a to-be-adjusted clock module in the original design file with a target clock module corresponding to the clock configuration information based on the file topology information to obtain an updated design file; and inputting the clock constraint file and the updated design file into a preset prototype development tool, and outputting a time sequence report after finishing time sequence analysis by utilizing the prototype development tool. Clock simulation under different scenes can be realized in an FPGA prototype verification platform, and the robustness of cross-clock domain transmission is verified.

Disclosed is a design process for high-performance specialized machine learning ASICs, optimized for given models and training or inference hardware end use. Modern Large Language Models (LLMs) and deep learning models can require trillions of parameters to be calculated, and the hardware currently used is not tailored for specific models or input datasets. A key tuneable parameter in custom hardware design is the encoding size of numbers. FPGA prototypes are used to test custom number encoding sizes, which informs the final fabricated design which is created with optimized RTL for the encoding size with attention to number register locations, and component sizes. By first analyzing specific machine learning models on prototype FPGA hardware with variable encoding sizes, the optimal number(s) for encoding size for both training and inference can be identified. By experimentally establishing an optimized encoding sizes for the specific computing use case wasted overhead in terms of physical registers is minimized. The approach herein minimizes research and development costs while optimizing encoding sizes for machine learning ASICS.

The invention provides an SATA (Serial Advanced Technology Attachment) speed bridge system, a data error injection method and an FPGA (Field Programmable Gate Array) prototype verification platform. According to the implementation scheme, the first end of the SATA speed bridge system is used for being connected with an SATA memory, the second end of the SATA speed bridge system is used for being connected with an SATA controller, and the SATA speed bridge system comprises a first data analysis module, a data error injection module and a first data packaging module; the first data analysis module analyzes the first data from the SATA memory and provides the first data to the data error injection module; the data error injection module injects error information into the analyzed first data to obtain second data and sends the second data to the first data packaging module; the first data packaging module receives the second data, packages the second data and sends the packaged second data to the SATA controller, and the second data is used for reporting error information when the SATA controller receives the second data. Therefore, the SATA controller can report error information.

The application provides a FPGA prototype verification platform transplantation method, device and equipment and readable medium, the method comprises the following steps: importing the engineering file of ASIC design into the engineering of FPGA prototype environment; identifying each phase-locked loop library module in the ASIC design, and analyzing the related parameters of the phase-locked loop, and generating the phase-locked loop IP module of the FPGA prototype verification platform based on the analyzed parameters; identifying each memory library module in the ASIC design, and analyzing the related parameters of the memory module, and generating the memory IP module of the FPGA prototype verification platform based on the analyzed parameters; generating the bidirectional IO port control logic module in the FPGA prototype verification platform based on the IO PAD library module in the ASIC design, and synchronizing the information of the pin in the ASIC design to the FPGA prototype verification platform. Through the use of the scheme of the application, the work efficiency of the ASIC design to the FPGA prototype transplantation can be improved, and the rework and repeated work caused by mistakes can be reduced.

The invention relates to the technical field of electronic equipment, and discloses a dual-port RAM prototype verification method and device and a prototype verification system.The dual-port RAM prototype verification device comprises a dual-port RAM module, a first port control unit, a second port control unit and a read data output control unit. An operation sequence of old data reading, operation and new data writing is completed in an external clock period, and an out-bit enabling function is simulated by using a common dual-port RAM; and meanwhile, the read data output control unit aligns, registers and outputs high-frequency operation results to ensure that the time sequence is correct. According to the scheme, the problem that the bit-enabled dual-port RAM cannot be directly supported in FPGA prototype verification is solved, and functional equivalent simulation can be efficiently and accurately realized without special hardware.

This invention relates to the field of integrated circuit technology, and in particular to an FPGA prototype verification system for a 16-channel clock-interleaved ADC, comprising a host computer and a verification board connected thereto; the verification board has an FPGA core board in the center and 16 ADC acquisition modules arranged compactly around it, the ADC acquisition modules being connected to the FPGA core board via a JTAG interface; the ADC acquisition module includes an ADC module and a clock generation module and a power supply module connected thereto; this invention innovatively introduces a hardware-level correction mechanism based on programmable phase-locked loop phase modulation, effectively reducing the complexity and logic resource overhead of subsequent digital domain signal processing.

The application discloses a kind of hardware logic design hierarchy information extraction method and system based on linked list tree, and the hardware logic design hierarchy information extraction method based on linked list tree of the present application includes using synthesis tool to synthesize the RTL code of hardware design into a group of netlist files, extract the information in netlist file, obtain hardware design synthesis report file, process hardware design synthesis report file to generate hardware logic design hierarchy information based on linked list tree, the design level structure information is extracted from a group of hardware module netlist files in the present application, and is organized and stored in the mode of linked list tree, to provide input for logic partition algorithm, the present application has the advantages that hierarchy information extraction is convenient, and storage space resource occupation is less, and visual display can be carried out to facilitate FPGA prototype verification system developer to intuitively understand hardware logic design hierarchy.

The FPGA prototype verification platform of the verifiable EMMC user interface of the application, by introducing the testcase module to output the user test instruction data corresponding to the same test operation of the EMMC chip connected with the user design interface to the EMMC chip, so as to determine whether the user design interface is correctly connected to the hardware link in the external EMMC chip through the FPGA prototype verification platform, and the problem positioning process is simplified.

The invention discloses a hardware resource scheduling method and device for a verification platform, a medium and a product, and the method comprises the steps: screening out a plurality of target servers meeting the requirements from a server resource pool according to the coarse-grained calculation resource demands of a target verification task, and carrying out the sorting based on the project priority and other factors, and generating a target server list; the servers in the list are traversed in sequence, and healthy alternative FPGA board cards on all the servers are screened out through real-time state monitoring; analyzing the task netlist file to obtain fine-grained resource requirements, and verifying whether the alternative board card meets the requirements or not; if verification succeeds, the matched board card group is used as a hardware equipment group to allocate tasks, and verification is executed; if verification fails, the traversal step is returned to continue to search other servers until matching succeeds or the preset number of iterations is reached, the resource utilization rate of the FPGA prototype verification platform is improved, and the average task queuing waiting time is shortened.

This invention discloses a hardware-software collaborative monitoring method and apparatus for on-chip network protocols. The method includes providing function bodies for shared use in the software portion through a shared function body declaration component in the synthesizable hardware portion; firstly, the non-synthesizable software portion instantiates the function bodies provided by the shared function body declaration component to capture CHI messages from various channels of the on-chip network protocol in the SoC under test; then, the CHI messages are output directly without verification, or the monitoring results are output after decoding, encoding, and specified protocol analysis of the CHI messages. This invention is applicable to FPGA prototyping platforms, has low hardware resource consumption, low system cost, and is quick and simple to implement. It enables efficient monitoring and analysis of CHI protocol messages on the prototyping platform, effectively accelerating the localization and performance analysis of SoC problems and improving SoC design efficiency.

The invention provides an FPGA prototype verification coverage rate monitoring system based on multi-dimensional monitoring and dynamic optimization, and belongs to the technical field of integrated circuit verifier.The FPGA prototype verification coverage rate monitoring system comprises the steps that firstly, a three-level coverage monitoring unit of a base layer, a state layer and a function layer is constructed, and multi-dimensional coverage rate monitoring is achieved; secondly, a self-adaptive data storage and transmission scheme is constructed, data coding storage is performed by fully utilizing coverage rate data features, the transmission efficiency is improved while the storage space is saved, and meanwhile, a multiple configurable transmission scheme is constructed to realize flexible data transmission; finally, according to the scheme, a time sequence sensing type instrumentation technology is constructed, cross-clock-domain data acquisition and instrumentation time sequence offset processing are fully solved, and the method has extremely high application value.

The embodiment of the invention discloses a prototype verification system, which is characterized by comprising at least two cascaded FPGA (Field Programmable Gate Array) prototype verification plates, the former-stage FPGA prototype verification board and the latter-stage FPGA prototype verification board are connected through a source synchronization data interface, and functional modules contained in the former-stage FPGA prototype verification board and the latter-stage FPGA prototype verification board are obtained through functional logic segmentation; wherein the source synchronization data interface comprises a multi-bit data interface and a channel associated clock interface. In the embodiment of the invention, the logic function modules connected through the source synchronization data interface are programmed to different cascaded FPGA boards, so that logic segmentation during FPGA prototype verification is realized, and the prototype verification cost can be reduced.

Provided in the present application are an FPGA prototype verification system, a chip verification method and an upper computer. The FPGA prototype verification system comprises: N chipsets, each chipset comprising M Chiplet units, each Chiplet unit being used for configuring a functional module to be verified, and N and M both being positive integers; a first communication bus unit, said functional modules configured in all of the Chiplet units being connected to the first communication bus unit, and the first communication bus unit being configured with a first communication protocol for enabling the communication between said functional modules; and a memory connected to the first communication bus unit, said functional modules configured in the Chiplet units accessing the memory by means of the first communication bus unit. The FPGA prototype verification system can improve the efficiency of verifying Chiplets.

The present invention relates to a software and hardware co - simulation verification platform for accelerating the verification and positioning of intelligent network card chips, belonging to the field of chip verification technology. The platform includes: a host - side QEMU virtual machine that simulates hardware devices, issues IO requests, responds to IO requests, and calls device drivers to implement the driving execution of host - side hardware devices; a host - side thread adapter that converts the multi - thread processing program of the host - side QEMU virtual machine into a single - thread processing program; a UVM verification platform that performs simulation reproduction of the FPGA prototype verification of the intelligent network card chip, generating simulation waveforms and simulation logs; a network - side data stream adapter that performs data type conversion on Ethernet packets; and a network - side packet transceiver that checks the legality of the Ethernet packets returned by the network - side data stream adapter. The platform of the present invention can improve the problem - positioning speed and chip verification efficiency, shorten the overall chip development cycle, and improve the chip quality.

The invention relates to the field of heterogeneous protocol conversion function verification, and provides an FPGA prototype verification device and method oriented to a heterogeneous protocol conversion function. The device comprises a flow generator and a comparison and statistics module, according to the device, the protocol conversion function of the heterogeneous protocol conversion equipment is verified through the flow generator and the comparison and statistics module; wherein the flow generator is used for generating a data stream by constructing a data packet to be converted, and inputting the data stream into the heterogeneous protocol conversion equipment; and the comparison and statistics module is used for verifying the heterogeneous protocol conversion function of the heterogeneous protocol conversion equipment by verifying the payload of the data packets converted by the heterogeneous protocol conversion equipment and counting the number of the data packets passing through the heterogeneous protocol conversion equipment. According to the device and the method provided by the invention, efficient judgment on the heterogeneous protocol conversion result can be realized.

The present application relates to the technical field of hardware verification, and discloses an FPGA prototype energy efficiency verification and iteration method for power patrol, which comprises the following cyclic execution: image data of a scene subsequence is input to an FPGA prototype verification board for target detection, and board-level power consumption data is obtained at the same time; based on the target detection result and the board-level power consumption data, a current efficiency index of the scene subsequence to be verified is calculated; the current efficiency index is evaluated: if the current efficiency index is not up to standard, the current bottleneck type is determined according to the size relationship between the current efficiency index and a current efficiency target value, and the hardware configuration scheme is updated according to the current bottleneck type. The method of the present application divides an image sequence into multiple groups of scene subsequences with different feature complexities, and each group of scene subsequences enters an independent cyclic verification, so that the final hardware configuration scheme can cope with diversity and complexity; through the cyclic verification process, the verification efficiency is improved, and the verification period is shortened.

The invention discloses a BMC (baseboard management controller) integrated test method based on an FPGA (field programmable gate array), which comprises the following steps of: based on an FPGA prototype verification board on hardware, performing BMC software function test and partial performance research test on each technical index of a BMC chip by utilizing the transportability and the maintainability of a cross compiling software platform in a mode of burning in batches according to modules; the problems that in the prior art, due to the fact that the capacity of an FPGA is insufficient, a binary stream file designed by a whole chip cannot be programmed to the FPGA at a time, and the performance of a test case which can only be operated in a whole environment or several kinds of hardware resources is poor are solved.

The present invention discloses a method for updating prototype system firmware on an FPGA platform, comprising: S1, converting the binary firmware content to be updated into a format readable by a firmware storage module through a Linux command and embedding the format into the firmware storage module to generate a bitstream file; S2, loading the bitstream file into the FPGA platform; after resetting, first sending an instruction to read the chip device ID to the Flash chip, and receiving the device ID information output by the Flash chip; S3, sending an instruction to enable write enable to the Flash chip, followed by an instruction to erase the entire chip; and S4, reading data from the firmware storage module and burning it into the Flash chip. This method simplifies the steps for replacing the firmware content in the Flash chip of the FPGA prototype platform, eliminates the need for hardware equipment such as a professional Flash burner, eliminates the need to power off the FPGA platform, and eliminates the need to remove the Flash chip from the FPGA platform. This reduces the use loss of the FPGA prototype platform, significantly improves replacement efficiency, and meets the needs of batch firmware replacement for multiple FPGA prototype verification platforms.

The invention discloses a low-power-consumption test method and device for a solid state disk based on FPGA prototype verification, and the method comprises the steps: a PC host transmits a signal for entering low power consumption and transmits the signal to an FPGA mainboard, and the FPGA mainboard starts to start a low-power-consumption process after receiving the signal; the FPGA main board controls the daughter board to back up the data of the power-down area in the Flash medium; the FPGA main board is used for keeping and processing special signals in the FPGA main board; the FPGA mainboard carries out reset operation on a power-down area in the test system; the FPGA mainboard executes isolation operation of the power-down area; and the FPGA mainboard carries out power-down operation on the power-down area. According to the method, the low-power-consumption process is verified based on the FPGA prototype verification platform, the risk can be effectively released before the Tapeout of the chip, and meanwhile the low-power-consumption debugging process after the chip returns can be accelerated.

The application provides an FPGA prototype verification method and system based on incremental compilation, which comprises the following steps: obtaining a current chip design and dividing the current chip design into multiple partitions; comparing the current chip design with a previous chip design to obtain partitions that have changed and partitions that have not changed in the current chip design; synthesizing the partitions that have changed to obtain a current netlist of the partitions that have changed, merging the current netlist of the partitions that have changed with a previous netlist of the partitions that have not changed to obtain a netlist of the current chip design; mapping the netlist of the current chip design to an FPGA chip to obtain a current placement and routing design; and verifying the current placement and routing design, if the current placement and routing design does not meet the requirements, modifying the chip design and repeating the above process, and if the current placement and routing design meets the requirements, performing board debugging according to the current placement and routing design. The application improves the efficiency of FPGA prototype verification and the development speed of chips.

The invention relates to the technical field of high-speed interface verification and system-level prototype verification, in particular to an FPGA prototype verification platform based on an MIPI loop, which comprises an upper computer PC, an FPGA main control chip, a PCIe interface module, a Decoder module, an MIPI sending module, an MIPI physical interface module, an MIPI receiving module and a verification module. The MIPI sending module and the MIPI receiving module are in direct loop connection through a dual-channel FPC flat cable. The verification module is a configurable verification area and is used for deploying a to-be-tested MIPI protocol module on the FPGA to realize function and performance verification of the to-be-tested MIPI protocol module in a closed-loop environment; the verification module can load different circuit modules, and performs on-line verification on data sending, receiving and time sequence logic of the different circuit modules; verification data is sent through the upper computer, enters the FPGA through the high-speed PCIe interface, and enters the MIPI sending module through the decoding module. According to the platform, functional verification and performance evaluation of any module based on the MIPI protocol can be completed under the condition of not depending on external real equipment, and the test complexity and cost are greatly reduced.

The application relates to an FPGA wiring method considering maximum time delay optimization, which comprises the following steps: step S1: adopting a layout optimization algorithm driven by wiring, circuit design is divided into subareas with smaller system time delay; step S2: adopting a TDM ratio initial allocation method based on a Lagrange relaxation method, optimal TDM ratio allocation results are obtained; step S3: a TDM ratio legalization algorithm based on actual constraint conditions is used to perform legalization operation on the TDM ratio allocation results; and step S4: a maximum time delay optimization algorithm based on negotiation exchange is used to further reduce the TDM ratio and reduce the system time delay. The application can effectively improve the availability of a multi-FPGA prototype system and improve wiring efficiency.