26 results about "FPGA prototype" patented technology

The invention relates to the technical field of chip design simulation verification, in particular to a memory type dynamic determination method for prototype verification and hardware simulation, and the method comprises the steps: carrying out sub-design division according to the module level of each module in a user netlist in combination with a first resource threshold sequence corresponding to an FPGA (Field Programmable Gate Array), and fitting the design logic clustering characteristics; according to the method, the hardware segmentation requirements of cross-sub-design interconnection and adaptation to multi-FPGA prototype verification are reduced, the layout and wiring difficulty is reduced, the performance and frequency of the FPGA are effectively improved, storage type allocation is realized according to the first target conversion rate and the second target conversion rate of the object and the target memory type, and the storage efficiency is improved. Relative balance and independence of various kinds of memory resources are achieved in the sub-design as much as possible, the number of FPGA chips needed for achieving the sub-design is reduced, and equivalently, the performance of the FPGA is improved.

The application relates to an FPGA prototype verification method and system of a smart meter chip, and belongs to the field of integrated circuit testing and electric power metering. The method aims to solve the problems of ASIC design transplantation to an FPGA platform, large difference between a verification environment and a real power grid, and lack of a real-time closed-loop verification mechanism. A technical scheme efficiently transplants the design to the FPGA by optimizing ASIC front-end synthesis constraints and adopting a netlist-level IP replacement strategy; a hardware-in-the-loop system is constructed, which comprises a real power grid signal source, a separation device simulation front end, an FPGA verification board, a high-precision standard electric energy meter and a host computer. The system can generate a real power grid excitation and realize synchronous collection of prototype output and the standard meter, real-time error analysis and dynamic adjustment of parameters, thereby forming a closed-loop verification. The application significantly improves code transplantation efficiency, provides a highly consistent real power grid verification environment, and greatly improves verification iteration and defect positioning speed.

The invention discloses a version management method, a fault detection method and a prototype version compiling system, and relates to the technical field of chip verifier.The version management method comprises the steps that after compiling is started, whether FPGA prototype version information matched with current version information of a local warehouse is contained in a version storage directory or not is searched; updating FPGA prototype version information according to a search result, wherein the FPGA prototype version information comprises current version information and a suffix version number; and generating version feature information according to the updated FPGA prototype version information, and sending the version feature information to a hardware top layer module to perform fault detection on the FPGA prototype version based on the version feature information, so that the problem that the version information cannot be known in the compiling process of the FPGA prototype verification platform can be solved, the version information can be obtained through an interface when a fault occurs, and the reliability of the FPGA prototype verification platform is improved. And whether the fault is caused by the version is judged, so that the technical effects of reducing the fault tracking and positioning difficulty and improving the verification working efficiency are achieved.

The application provides a FPGA prototype verification platform transplantation method, device and equipment and readable medium, the method comprises the following steps: importing the engineering file of ASIC design into the engineering of FPGA prototype environment; identifying each phase-locked loop library module in the ASIC design, and analyzing the related parameters of the phase-locked loop, and generating the phase-locked loop IP module of the FPGA prototype verification platform based on the analyzed parameters; identifying each memory library module in the ASIC design, and analyzing the related parameters of the memory module, and generating the memory IP module of the FPGA prototype verification platform based on the analyzed parameters; generating the bidirectional IO port control logic module in the FPGA prototype verification platform based on the IO PAD library module in the ASIC design, and synchronizing the information of the pin in the ASIC design to the FPGA prototype verification platform. Through the use of the scheme of the application, the work efficiency of the ASIC design to the FPGA prototype transplantation can be improved, and the rework and repeated work caused by mistakes can be reduced.

The invention relates to the technical field of electronic equipment, and discloses a dual-port RAM prototype verification method and device and a prototype verification system.The dual-port RAM prototype verification device comprises a dual-port RAM module, a first port control unit, a second port control unit and a read data output control unit. An operation sequence of old data reading, operation and new data writing is completed in an external clock period, and an out-bit enabling function is simulated by using a common dual-port RAM; and meanwhile, the read data output control unit aligns, registers and outputs high-frequency operation results to ensure that the time sequence is correct. According to the scheme, the problem that the bit-enabled dual-port RAM cannot be directly supported in FPGA prototype verification is solved, and functional equivalent simulation can be efficiently and accurately realized without special hardware.

This invention relates to the field of integrated circuit technology, and in particular to an FPGA prototype verification system for a 16-channel clock-interleaved ADC, comprising a host computer and a verification board connected thereto; the verification board has an FPGA core board in the center and 16 ADC acquisition modules arranged compactly around it, the ADC acquisition modules being connected to the FPGA core board via a JTAG interface; the ADC acquisition module includes an ADC module and a clock generation module and a power supply module connected thereto; this invention innovatively introduces a hardware-level correction mechanism based on programmable phase-locked loop phase modulation, effectively reducing the complexity and logic resource overhead of subsequent digital domain signal processing.

The application discloses a kind of hardware logic design hierarchy information extraction method and system based on linked list tree, and the hardware logic design hierarchy information extraction method based on linked list tree of the present application includes using synthesis tool to synthesize the RTL code of hardware design into a group of netlist files, extract the information in netlist file, obtain hardware design synthesis report file, process hardware design synthesis report file to generate hardware logic design hierarchy information based on linked list tree, the design level structure information is extracted from a group of hardware module netlist files in the present application, and is organized and stored in the mode of linked list tree, to provide input for logic partition algorithm, the present application has the advantages that hierarchy information extraction is convenient, and storage space resource occupation is less, and visual display can be carried out to facilitate FPGA prototype verification system developer to intuitively understand hardware logic design hierarchy.

The FPGA prototype verification platform of the verifiable EMMC user interface of the application, by introducing the testcase module to output the user test instruction data corresponding to the same test operation of the EMMC chip connected with the user design interface to the EMMC chip, so as to determine whether the user design interface is correctly connected to the hardware link in the external EMMC chip through the FPGA prototype verification platform, and the problem positioning process is simplified.

The invention discloses a hardware resource scheduling method and device for a verification platform, a medium and a product, and the method comprises the steps: screening out a plurality of target servers meeting the requirements from a server resource pool according to the coarse-grained calculation resource demands of a target verification task, and carrying out the sorting based on the project priority and other factors, and generating a target server list; the servers in the list are traversed in sequence, and healthy alternative FPGA board cards on all the servers are screened out through real-time state monitoring; analyzing the task netlist file to obtain fine-grained resource requirements, and verifying whether the alternative board card meets the requirements or not; if verification succeeds, the matched board card group is used as a hardware equipment group to allocate tasks, and verification is executed; if verification fails, the traversal step is returned to continue to search other servers until matching succeeds or the preset number of iterations is reached, the resource utilization rate of the FPGA prototype verification platform is improved, and the average task queuing waiting time is shortened.

The embodiment of the invention discloses a prototype verification system, which is characterized by comprising at least two cascaded FPGA (Field Programmable Gate Array) prototype verification plates, the former-stage FPGA prototype verification board and the latter-stage FPGA prototype verification board are connected through a source synchronization data interface, and functional modules contained in the former-stage FPGA prototype verification board and the latter-stage FPGA prototype verification board are obtained through functional logic segmentation; wherein the source synchronization data interface comprises a multi-bit data interface and a channel associated clock interface. In the embodiment of the invention, the logic function modules connected through the source synchronization data interface are programmed to different cascaded FPGA boards, so that logic segmentation during FPGA prototype verification is realized, and the prototype verification cost can be reduced.

Provided in the present application are an FPGA prototype verification system, a chip verification method and an upper computer. The FPGA prototype verification system comprises: N chipsets, each chipset comprising M Chiplet units, each Chiplet unit being used for configuring a functional module to be verified, and N and M both being positive integers; a first communication bus unit, said functional modules configured in all of the Chiplet units being connected to the first communication bus unit, and the first communication bus unit being configured with a first communication protocol for enabling the communication between said functional modules; and a memory connected to the first communication bus unit, said functional modules configured in the Chiplet units accessing the memory by means of the first communication bus unit. The FPGA prototype verification system can improve the efficiency of verifying Chiplets.

The present application relates to the technical field of hardware verification, and discloses an FPGA prototype energy efficiency verification and iteration method for power patrol, which comprises the following cyclic execution: image data of a scene subsequence is input to an FPGA prototype verification board for target detection, and board-level power consumption data is obtained at the same time; based on the target detection result and the board-level power consumption data, a current efficiency index of the scene subsequence to be verified is calculated; the current efficiency index is evaluated: if the current efficiency index is not up to standard, the current bottleneck type is determined according to the size relationship between the current efficiency index and a current efficiency target value, and the hardware configuration scheme is updated according to the current bottleneck type. The method of the present application divides an image sequence into multiple groups of scene subsequences with different feature complexities, and each group of scene subsequences enters an independent cyclic verification, so that the final hardware configuration scheme can cope with diversity and complexity; through the cyclic verification process, the verification efficiency is improved, and the verification period is shortened.

The invention discloses a BMC (baseboard management controller) integrated test method based on an FPGA (field programmable gate array), which comprises the following steps of: based on an FPGA prototype verification board on hardware, performing BMC software function test and partial performance research test on each technical index of a BMC chip by utilizing the transportability and the maintainability of a cross compiling software platform in a mode of burning in batches according to modules; the problems that in the prior art, due to the fact that the capacity of an FPGA is insufficient, a binary stream file designed by a whole chip cannot be programmed to the FPGA at a time, and the performance of a test case which can only be operated in a whole environment or several kinds of hardware resources is poor are solved.

The application provides an FPGA prototype verification method and system based on incremental compilation, which comprises the following steps: obtaining a current chip design and dividing the current chip design into multiple partitions; comparing the current chip design with a previous chip design to obtain partitions that have changed and partitions that have not changed in the current chip design; synthesizing the partitions that have changed to obtain a current netlist of the partitions that have changed, merging the current netlist of the partitions that have changed with a previous netlist of the partitions that have not changed to obtain a netlist of the current chip design; mapping the netlist of the current chip design to an FPGA chip to obtain a current placement and routing design; and verifying the current placement and routing design, if the current placement and routing design does not meet the requirements, modifying the chip design and repeating the above process, and if the current placement and routing design meets the requirements, performing board debugging according to the current placement and routing design. The application improves the efficiency of FPGA prototype verification and the development speed of chips.

The invention relates to the technical field of high-speed interface verification and system-level prototype verification, in particular to an FPGA prototype verification platform based on an MIPI loop, which comprises an upper computer PC, an FPGA main control chip, a PCIe interface module, a Decoder module, an MIPI sending module, an MIPI physical interface module, an MIPI receiving module and a verification module. The MIPI sending module and the MIPI receiving module are in direct loop connection through a dual-channel FPC flat cable. The verification module is a configurable verification area and is used for deploying a to-be-tested MIPI protocol module on the FPGA to realize function and performance verification of the to-be-tested MIPI protocol module in a closed-loop environment; the verification module can load different circuit modules, and performs on-line verification on data sending, receiving and time sequence logic of the different circuit modules; verification data is sent through the upper computer, enters the FPGA through the high-speed PCIe interface, and enters the MIPI sending module through the decoding module. According to the platform, functional verification and performance evaluation of any module based on the MIPI protocol can be completed under the condition of not depending on external real equipment, and the test complexity and cost are greatly reduced.

The application relates to an FPGA wiring method considering maximum time delay optimization, which comprises the following steps: step S1: adopting a layout optimization algorithm driven by wiring, circuit design is divided into subareas with smaller system time delay; step S2: adopting a TDM ratio initial allocation method based on a Lagrange relaxation method, optimal TDM ratio allocation results are obtained; step S3: a TDM ratio legalization algorithm based on actual constraint conditions is used to perform legalization operation on the TDM ratio allocation results; and step S4: a maximum time delay optimization algorithm based on negotiation exchange is used to further reduce the TDM ratio and reduce the system time delay. The application can effectively improve the availability of a multi-FPGA prototype system and improve wiring efficiency.

The application provides a data verification platform and a data verification method and a computer readable storage medium thereof, the data verification platform comprises at least two groups of extension modules and a master control module connected with the extension modules; the extension module is used for receiving the data of the project to be verified and verifying the data of the project to be verified; the master control module is used for compiling a basic data file related to the data of the project to be verified and detecting the running state of the extension module; when it is detected that the extension module which has verified the data of the project to be verified is in an occupied state and another group of extension modules in an idle state exist, the environment configuration variable in the basic data file is modified; the basic data file is mapped to another group of extension modules according to the modified environment configuration variable. Through the application, the FPGA resource can be used efficiently, and the user can be provided with the ability and flexibility of sharing the entire FPGA prototype / simulation system without waiting for the specific hardware to be released before the work is performed.

The application discloses an automatic FPGA prototype verification method and relates to the field of chip FPGA prototype verification; the method comprises the following steps: S1, a verification platform is divided into an FPGA prototype test module and an auxiliary test module; S2, according to the module function of FPGA prototype verification, a test flow is divided into three types: an internal self-test flow, an external excitation and feedback test flow and a test flow related to reset; S3, according to the module function, a test instruction is issued to FPGA test code, and meanwhile, an auxiliary test chip judges corresponding output or test results fed back by the FPGA; the auxiliary test chip sequentially sends test instructions and records test results; S4, the auxiliary test module sequentially tests all function CASEs, and according to test results, error test items are preferentially tested during regression testing. The application provides a stable verification method, reduces the verification difficulty and the threshold of verification personnel, reduces the labor cost and improves the efficiency.

The invention discloses an interface test method and device, electronic equipment and a medium, and relates to the technical field of computers, the method is applied to a field-programmable gate array prototype corresponding to equipment to be tested, the field-programmable gate array prototype comprises a plurality of pre-constructed test units, each test unit is used for generating a corresponding excitation signal, and the excitation signal is used for generating an excitation signal. Comprising the steps of obtaining an interface test instruction of to-be-tested equipment; based on the interface test instruction, a target test unit is screened from the multiple test units according to a preset screening rule, and the target test unit is used for generating an excitation signal corresponding to the interface test instruction; and testing the interface of the to-be-tested equipment through the target test unit. According to the invention, the prototype verification efficiency is improved, and the method is suitable for various complex verification scenes.

The invention provides an FPGA prototype partitioning method based on result driving, and relates to the technical field of FPGA chip prototypes, and the method comprises the steps: marking a VR module in a to-be-processed module based on an initial partitioning algorithm; calculating the partitioning cost of the graph model, and obtaining a partitioning result when the partitioning cost is lowest; performing layout and wiring based on a partitioning result, and performing adaptive optimization on the partitioned FPGA until a time sequence requirement of layout and wiring is met; and outputting the FPGA data bit stream meeting the time sequence requirement of layout and wiring. According to the application, the partitioning efficiency is improved by adopting a method of firstly thinning and then partitioning on the basis of a protocol feature partitioning module, and then the limitation that data is completely transmitted in a single parallel clock period in traditional partitioning is eliminated in a credit protocol conversion mode by utilizing a time division multiplexing method PTDM specially designed for partitioning; besides, on the basis of an algorithm strategy of dynamically adjusting partitions, no human intervention can be truly realized, and finally, the purpose of obtaining FPGA data bit streams capable of being tested on a board is achieved.

The application discloses a kind of FPGA prototype verification platform based on vehicle gauge grade millimeter wave radar SOC chip, belong to chip verification technical field.It includes: data selection unit, data generation unit, data storage unit, data transmission unit, data processing unit, analysis and verification unit and result display unit.Different data is selected using signal selector, dial code switch is dialled to 0 to select the data of real acquisition of radio frequency front end, dial to 1 to select the test data in HBM, the overall function of millimeter wave radar SOC chip is verified by building verification platform using integrated radio frequency front end analog chip, ADC chip and FPGA minimum system, the function of real millimeter wave radar SOC chip can be restored as far as possible using the verification platform built by multiple discrete devices, greatly reduce the risk of tape-out failure, using the HBM high bandwidth memory integrated in FPGA can replace the external DDR grain, and higher transmission rate can be obtained, so as to reduce the development cost and power consumption of verification platform.

The application discloses a kind of controller's FPGA prototype verification method, system, medium and computing device, it is applied to controller's FPGA prototype verification system, the controller's FPGA prototype verification system includes DFI-AXI protocol bus bridge and controller IP core, the method includes by the DFI-AXI protocol bus bridge to the DFI protocol signal received is converted, obtains AXI protocol signal;Wherein, the DFI-AXI protocol bus bridge is based on FIFO to the DFI protocol signal is written and read;The AXI protocol signal is sent to the controller IP core;By the controller IP core, the AXI protocol signal is converted, obtains target protocol signal;The target protocol signal is sent to controller memory grain, to realize the FPGA prototype verification of the controller;Wherein, the controller memory grain is hung on FPGA.The application can be carried out to the complete FPGA prototype verification of controller.

The invention discloses a decoder based on an enhanced QOI algorithm, and aims to provide an image decoding hardware architecture with high throughput rate and low time delay, which is used for efficiently converting an enhanced QOI coded data stream into an RGB888 pixel stream. Compared with the traditional QOI decoding method, the method has the advantages that the original coding type is redefined through the pre-decoding unit, the decoding logic is simplified, and the complexity of the main decoding unit is reduced; a read-ahead line caching strategy and a zero-delay index table are adopted, and single-cycle pixel generation is achieved. The decoder consists of a coding group extractor, a pre-decoding unit, a main decoding unit and an output bit width conversion module, supports input and output of an AXIS interface, and can optimize a time sequence by configuring a register piece. The FPGA prototype only occupies 726 LUT and 710 FF while the throughput rate of 1 pixel / clk is kept, the total time delay is as low as 3-7 clk, and the method is suitable for a high-real-time image processing system.

The embodiment of the application provides a FPGA prototype verification method and device, comprising: a system on chip of FPGA receives a target signal sent by an upper computer; the system on chip of FPGA determines the type of the target signal according to the time interval between the target signal and an adjacent signal; if the type of the target signal is a control instruction, the corresponding operation of the control instruction is executed; if the type of the target signal is configuration data, the configuration data is executed according to the previous control instruction of the configuration data; the configuration data is the software code of a chip module to be verified. The system on chip of FPGA can distinguish the control instruction and the configuration data more accurately according to the time interval between the target signal and the adjacent signal, which is convenient for finding problems and making corrections quickly subsequently, and the system on chip of FPGA has a certain expansibility, which is convenient for expanding more control instructions subsequently.

The application provides a chip design test method, system, medium, equipment and FPGA prototype verification platform; the FPGA prototype verification platform comprises at least two verification blocks; each verification block comprises a control FPGA and a test FPGA; the control FPGA is connected with the test FPGA and is used for controlling the test FPGA to test the design of a chip; the FPGA prototype verification platform is divided into resources, a plurality of users can be simultaneously provided with a design verification environment, the waste of the FPGA prototype verification platform resources is effectively avoided, the verification efficiency of the customer is improved, and the cost is reduced.

The application relates to the field of chip design, in particular to a video data processing debugging system and method based on FPGA prototype verification. The system comprises a DDR memory for storing data; a data generation module for generating original video data to be tested; a compression module for compressing the original video data to be tested to generate compressed data, and for providing an internal bus interface for accessing the DDR memory; a bus interface debugging module for providing an external bus interface for accessing the DDR memory; when the compression module generates the compressed data, a bus arbitration module is enabled to connect the internal bus interface with the DDR memory to store the compressed data into the DDR memory; when it is needed to verify the video data processing function, the bus arbitration module is enabled to connect the external bus interface to enable an external device to read the compressed data from the DDR memory. The scheme of the application avoids wasting internal RAM resources and realizes convenient and fast acquisition of debugging data.