5 results about "FPGA prototype" patented technology

The application relates to an FPGA prototype verification method and system of a smart meter chip, and belongs to the field of integrated circuit testing and electric power metering. The method aims to solve the problems of ASIC design transplantation to an FPGA platform, large difference between a verification environment and a real power grid, and lack of a real-time closed-loop verification mechanism. A technical scheme efficiently transplants the design to the FPGA by optimizing ASIC front-end synthesis constraints and adopting a netlist-level IP replacement strategy; a hardware-in-the-loop system is constructed, which comprises a real power grid signal source, a separation device simulation front end, an FPGA verification board, a high-precision standard electric energy meter and a host computer. The system can generate a real power grid excitation and realize synchronous collection of prototype output and the standard meter, real-time error analysis and dynamic adjustment of parameters, thereby forming a closed-loop verification. The application significantly improves code transplantation efficiency, provides a highly consistent real power grid verification environment, and greatly improves verification iteration and defect positioning speed.

This invention relates to the field of integrated circuit technology, and in particular to an FPGA prototype verification system for a 16-channel clock-interleaved ADC, comprising a host computer and a verification board connected thereto; the verification board has an FPGA core board in the center and 16 ADC acquisition modules arranged compactly around it, the ADC acquisition modules being connected to the FPGA core board via a JTAG interface; the ADC acquisition module includes an ADC module and a clock generation module and a power supply module connected thereto; this invention innovatively introduces a hardware-level correction mechanism based on programmable phase-locked loop phase modulation, effectively reducing the complexity and logic resource overhead of subsequent digital domain signal processing.

Provided in the present application are an FPGA prototype verification system, a chip verification method and an upper computer. The FPGA prototype verification system comprises: N chipsets, each chipset comprising M Chiplet units, each Chiplet unit being used for configuring a functional module to be verified, and N and M both being positive integers; a first communication bus unit, said functional modules configured in all of the Chiplet units being connected to the first communication bus unit, and the first communication bus unit being configured with a first communication protocol for enabling the communication between said functional modules; and a memory connected to the first communication bus unit, said functional modules configured in the Chiplet units accessing the memory by means of the first communication bus unit. The FPGA prototype verification system can improve the efficiency of verifying Chiplets.

The present application relates to the technical field of hardware verification, and discloses an FPGA prototype energy efficiency verification and iteration method for power patrol, which comprises the following cyclic execution: image data of a scene subsequence is input to an FPGA prototype verification board for target detection, and board-level power consumption data is obtained at the same time; based on the target detection result and the board-level power consumption data, a current efficiency index of the scene subsequence to be verified is calculated; the current efficiency index is evaluated: if the current efficiency index is not up to standard, the current bottleneck type is determined according to the size relationship between the current efficiency index and a current efficiency target value, and the hardware configuration scheme is updated according to the current bottleneck type. The method of the present application divides an image sequence into multiple groups of scene subsequences with different feature complexities, and each group of scene subsequences enters an independent cyclic verification, so that the final hardware configuration scheme can cope with diversity and complexity; through the cyclic verification process, the verification efficiency is improved, and the verification period is shortened.

The application provides an FPGA prototype verification method and system based on incremental compilation, which comprises the following steps: obtaining a current chip design and dividing the current chip design into multiple partitions; comparing the current chip design with a previous chip design to obtain partitions that have changed and partitions that have not changed in the current chip design; synthesizing the partitions that have changed to obtain a current netlist of the partitions that have changed, merging the current netlist of the partitions that have changed with a previous netlist of the partitions that have not changed to obtain a netlist of the current chip design; mapping the netlist of the current chip design to an FPGA chip to obtain a current placement and routing design; and verifying the current placement and routing design, if the current placement and routing design does not meet the requirements, modifying the chip design and repeating the above process, and if the current placement and routing design meets the requirements, performing board debugging according to the current placement and routing design. The application improves the efficiency of FPGA prototype verification and the development speed of chips.