FPGA prototype automatic verification method and system based on GitLab-CI

Abstract

The invention discloses a method and system based on GitLab-CI FPGA prototype automatic verification, the invention adopts a GitLab-CI continuous integration mode, the process of compiling and simulating, synthesizing, realizing, testing, analyzing and submitting test report in the verification process of FPGA prototype is processed automatically. The system includes computer systems, including interconnected GitLab repositories, triggering the continuous integration tool GitLab-CI and at least one client GitLab-Runner. An FPGA board is connected to the client GitLab- runner through a networkinterface. The invention can automatically realize the process of chip code compilation and simulation, synthesis, realization, test, analysis of test result and submission of test report, etc., and has the advantages of reducing waste of manpower and energy and improving the efficiency of prototype verification work.

Description

technical field [0001] The invention relates to the field of chip design prototype verification, in particular to a GitLab-CI-based FPGA prototype automatic verification method and system. Background technique [0002] As the difficulty and challenges of integrated circuit design further increase, in the chip development and verification stage, there are more and more iterative versions of the design code, and each design version requires functional verification. How to accelerate the iteration of the verification process is a key issue that needs to be solved in the chip design stage. [0003] For large-scale chips, FPGA prototype verification has become the mainstream method in the field of functional verification of integrated circuits. Its operating speed is generally between several megabytes and hundreds of megabytes, which can quickly test the performance and correctness of the design. like figure 1 As shown, the specific process of traditional FPGA prototype verif...

AI Technical Summary

Problems solved by technology

However, based on the traditional FPGA prototype verification process, each of the above prototype verification sub-processes requires developers to compare and analyze the results of each sub-process in person to ensure that the current sub-process is correct before manually starting and executing the next sub-process. Each stage requires the manual intervention of testers, which is time-consuming and labor-intensive. Moreover, when the design code has multiple sets of iterative versions at the same time, the traditional prototype verification method is limited by the number of testers and work efficiency, which will reduce the overall efficiency of prototype verification.

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