Message filtering system and message filtering method of high-speed interconnection bus

Abstract

The invention discloses a message filtering system and a message filtering method of a high-speed interconnection bus. The message filtering system comprises a decoding module, a bubbling module connected with the decoding module, a combining module connected with the bubbling module and a converting module connected with the combining module. By the aid of the message filtering system of the high-speed interconnection bus, data transmitted on the high-speed interconnection bus are decoded, effective data messages are kept, invalid information in the data is filtered, and a data stream after filtering is subjected to clock domain conversion by means of asynchronous FIFO (first in first out) and further is converted from a high-frequency clock domain of the high-speed interconnection bus to a lower-frequency clock domain of an FPGA (field programmable gate array) chip core logic, so that requirements on frequency and resources are lowered, the problem about limitation of an FPGA verification system is solved, and design flexibility of the high-speed interconnection bus is improved. By means of reducing risks and difficulty of an FPGA prototype system, a product verification cycle is shortened, and the success rate of chip putting is increased.

Description

Technical field [0001] The invention belongs to the technical field of computer integrated circuit design, and relates to a message filtering system and method for a high-speed interconnected bus. Background technique [0002] At present, with the rapid development of computer and integrated circuit technology, the direct interconnection between the internal chip and the chip of the computer is often based on the serial high-speed point-to-point connection protocol of message transmission, which uses differential signals and special clocks for transmission. There are very high requirements on the bandwidth and power consumption of each pin. In the high-end processors on the market, the high-speed bus interconnection mode enables the speed of each serial high-speed channel to reach 6.4Gb / s. The high-speed interconnection bus between the CPU and the CPU adopts a point-to-point design, including a pair of lines, respectively responsible Data transmission and reception, the peak ban...

AI Technical Summary

Problems solved by technology

For the characteristics of high bandwidth and high speed of the high-speed interconnection bus, some FPGA prototype systems often cannot reach the clock frequency required by the high-speed interconnection bus due to the limitations of chip resources, layout and wiring, and there is a problem that the bus frequency does not match the logical frequency of the FPGA chip.

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