Back-to-back loopback validation method for large-scale interconnection chips based on detection logic addition

A technology of detection logic and verification method, which is applied in the field of back-to-back loopback verification based on added detection logic for large-scale interconnection chips, can solve problems such as the superposition of module uncertainty factors, and achieve the effect of fast processing speed

Active Publication Date: 2014-08-06
LANGCHAO ELECTRONIC INFORMATION IND CO LTD
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Problems solved by technology

[0003] In order to solve the above two problems, first of all, according to the signal transmission sequence of each module in the NC interconnection chip connected to the CPU, first verify the modules directly connected to the CPU, and then successively Add the idea of ​​​​subsequent modules to solve the problem of superposition of uncertain factors in each module in the interconnection logic

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  • Back-to-back loopback validation method for large-scale interconnection chips based on detection logic addition

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Embodiment Construction

[0025] The purpose of the present invention is to provide a method for verifying simulation testing of large-scale interconnection chips and FPGA prototype verification by adding detection logic modules and back-to-back verification.

[0026] The realization of the present invention at first satisfies three prerequisites:

[0027] 1) The messages sent by each CPU / BFM ​​(1-0, 1-1) can be divided into different types, and the number of unprocessed messages of the same type that can be sent must be within a certain range. First, avoid channel blockage. In addition, too much unprocessed message data will double the logic of the detection module (3), occupy too many logic resources and wiring resources in FPGA prototype verification, and make it difficult to meet the timing requirements of wiring.

[0028] 2) The time for each message to pass through the detected module must be less than a certain fixed value, which is determined through delay experiments, otherwise the detection m...

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Abstract

The invention provides a back-to-back loopback validation method based on detection logic addition to validate NC interconnection logic through simulation validation and FPGA prototype validation. According to the characteristics that NC messages can be divided according to types and transmitted through channels, the mode of module back-to-back loopback validation and detection logic addition validation is put forward, problems of large data size, low manual validation efficiency and difficult in positioning during simulation validation and FPGA prototype validation of large-scale interconnection logic are solved, and validation results and efficiency are ensured.

Description

technical field [0001] The invention belongs to the category of computer architecture and relates to the technical field of verification methods for large-scale interconnection chips, in particular to a back-to-back loopback verification method for large-scale interconnection chips based on added detection logic. Background technique [0002] In order to realize a large-scale CC-NUMA (Cache Coherence Non-Uniform Memory Access) multiprocessor system, it is necessary to expand the coherence domain space with the help of the node interconnection chip NC (Node Controller). In the process of NC simulation verification and FPGA verification, because the multi-level consistency domain CC-NUMA system protocol based on the extended Cache Coherence protocol is often relatively complicated, in the process of verification of a large number of test cases, datagrams with a large amount of data text delivery. In the process of simulation verification, especially in the process of FPGA ve...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/25G01R31/28G01R31/3177
Inventor 刘强陈继承赵元王京
Owner LANGCHAO ELECTRONIC INFORMATION IND CO LTD
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