Field programmable gate array (FPGA) prototype verification device and method

Abstract

The invention discloses field programmable gate array (FPGA) prototype verification device and method. The device comprises a packet signal selection module, an asynchronous first in first out (FIFO) module, a memory control module, a data transmission module and a main control module, wherein an input end of the packet signal selection module is connected with at least one packet signal of an FPGA prototype; when an error occurs during the FPGA prototype verification, one of the packet signals is selected from the input end of the packet signal selection module according to a selection instruction to serve as a monitored signal; the packet signal is output to the asynchronous FIFO module to be synchronized into a signal with a speed same as that of the memory control module; the synchronized signal is stored to an external memory by the memory control module and then is read to the data transmission module by the external memory; and the monitored signal is transmitted to an external computer by the data transmission module to carry out data analysis so as to positioning the error. By using the FPGA prototype verification device and method, the operability, the visibility and the efficiency of the FPGA verification can be improved.

Description

technical field [0001] The invention relates to a field programmable gate array (FPGA, Field Programmable Gate Array) prototype verification technology, in particular to an FPGA prototype verification device and a verification method. Background technique [0002] System prototype verification is a key factor for the success of system on chip (SoC, System on Chip) and application specific integrated circuit (ASIC, Application Specific Integrated Circuit) design. Traditional verification methods include software simulation technology and hardware accelerator technology. The software simulation technology uses software to simulate SoC or ASIC design and verify it. Its advantage is that it has absolute visibility for the design, and its disadvantage is that the simulation speed is slow. As SoC designs become more and more complex, designers find it difficult to verify the correctness of hardware design only by software simulation due to the limitation of simulation speed and m...

AI Technical Summary

Problems solved by technology

For large-scale SoC FPGA prototype verification, it will take more than ten to twenty hours to change the pin constraint each time, which has poor operability and low efficiency.

[0013] 2) Using an oscilloscope to observe the signals inside the FPGA in real time will face the shortcomings of too few observable signals and too short signal length, and the visibility is poor, so the efficiency of positioning errors is relatively low

[0021] 1) Because the problem of locating the FPGA operation error is mainly adopted the method of elimination, it is first judged that the position most relevant to the current error is a problem, and then it is normal to exclude these positions one by one according to the degree of correlation, so the prior art 2 will be repeatedly modified and sent to The signal of the built-in logic analyzer hard core, and every change to the logic analyzer hard core will be re-synthesized, placed and routed, which brings a lot of time consumption, poor operability, and relatively low efficiency

[0022] 2) The positioning method of the hard core of the built-in logic analyzer in the FPGA needs to occupy FPGA resources. For a large-scale FPGA prototype verification platform, FPGA resources are limited, so the positioning method of the hard core of the built-in logic analyzer cannot analyze The amount of data is relatively limited, and it will also face the disadvantage of too few observable signals, and the visibility is relatively poor, so the efficiency of positioning errors is relatively low

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