15 results about "Hard core" patented technology

The invention discloses a preparation method of a core-shell structure hard alloy with high strength and high toughness, and belongs to the technical field of hard alloys and powder metallurgy. According to the preparation method, a micro heterostructure is formed after sintering through a pre-constructed'fine grain hard core-coarse grain tough shell 'powder system, and deflection and energy dissipation are promoted during crack propagation by utilizing the performance difference and interfacial effect between the core and a matrix, so that the strength and toughness of the material are synergistically improved. The method is simple in process and low in cost, the material performance can be flexibly designed by adjusting the core particle size, the core-shell components and the core-shell proportion, and the method is suitable for tools, drilling tools, wear-resistant parts and the like with strict requirements for obdurability.

The invention discloses an embedded ARM hardcore FPGA time sequence simulation test method and system, and aims to overcome the defects of low hardcore FPGA time sequence simulation test efficiency and test quality caused by lack of a time sequence simulation model in a tested netlist in the prior art. The system comprises a test bed, an interface simulation model module and a signal mapping module, the test bed provides a simulation test environment, the interface simulation model module is connected to the test bed to simulate an ARM hardcore interface protocol behavior, and the signal mapping module realizes signal mapping of a netlist and the test bed through a simulation tool system task. The method is based on the system, a corresponding interface simulation model is selected according to an ARM hardcore interface protocol, a test bed interface signal is defined, a system task mapping signal is called, a model port is bound to replace an original model, a file is compiled to execute time sequence simulation, and waveform verification is observed. According to the method, the defect of model deficiency is made up, the testing efficiency and quality are greatly improved, and the requirement for time sequence simulation testing of the hard-core FPGA is met.

The utility model discloses a novel mechanical sealing structure, and relates to the technical field of sealing. The pipe joint comprises a pipe end to be connected, an inner connecting pipe, an outer sleeve, an inner seal and a push ring, a machine connecting seat is arranged at one end of the inner connecting pipe, the inner connecting pipe and the outer sleeve are integrally provided with flanges and are concentrically connected through bolts, the inner seal comprises a hard core ring, an embedded groove is formed in one side of the hard core ring, and a convex ring part is arranged on the inner side of the other side of the hard core ring. By designing the novel sealing structure, the connection sealing between the pipe end to be connected and the inner connecting pipe can be realized through the matching of the inner seal and the sealing ring, the connection sealing between the outer sleeve and the inner connecting pipe can be realized through the matching of the inner seal, the push ring and the sealing mechanism, the sealing effect is better, and meanwhile, if the loosening condition occurs, the sealing effect is better. The sealing effect between the push ring and the inner seal can be continuously maintained through the elastic force of the spring, and the sealing effect of the sealing point is greatly improved.

The invention provides acrylate latex as well as a preparation method and application thereof, and belongs to the technical field of pressure-sensitive adhesives. The acrylate latex provided by the invention has a core-shell structure with a hard core and a soft shell, the inner core is the acrylate copolymer with a high glass transition temperature, high cohesion is provided, the creep resistance of the pressure-sensitive adhesive is ensured, the glass transition temperature of the inner core is-25-30 DEG C, and the pressure-sensitive adhesive has the best adhesive overflow resistance; the shell is made of the acrylate copolymer with low glass transition temperature, and the glass transition temperature of the shell is-35 to-65 DEG C, so that the pressure-sensitive adhesive is endowed with enough initial adhesion and stripping force, and the adhesive property is ensured. The result of the embodiment of the invention shows that the initial adhesion of the acrylate latex provided by the invention is more than 10N / 25mm, the 90-degree stripping force is more than 7N / 25mm, the permanent adhesion is not displaced for 120 hours, and the acrylate latex has good comprehensive performance.

A system and method for securing a system-on-chip (SoC) field programmable gate array (FPGA) is provided, wherein the SoC FPGA includes an FPGA fabric, a soft core processor hosted within the FPGA fabric, a hard core processor, and a secure boot environment for the SOC FPGA. Monitoring logic monitors for a change in the FPGA fabric. External watchdog logic is configured to receive a trigger signal from the monitoring logic, and force the hard core processor(s) of the SoC FPGA into a reset state with no ability to recover unless power is cycled when a change has been made to the FPGA fabric, so as to provide a “fail secure” scenario. The monitoring logic may be firmware hosted on the FPGA fabric, software hosted on the soft core, software hosted on the hard core, and / or external hard logic.

The utility model discloses a hollow pointed-end heating rod, which comprises a heating pipe body and a pointed-end plug, the heating pipe body is a hollow thin-wall piece formed by winding a casting sheet around an auxiliary hard core rod for two circles, then pressing by using an isostatic pressing process, and drawing out the hard core rod after pressing; the tail end of the tape casting sheet in the winding direction is coated with glue; a heating circuit is printed on the casting sheet, an electrode of the heating circuit is connected with a lead, and the heating tube body is provided with a first end for mounting the lead and a second end for mounting the pointed plug; the pointed plug comprises a conical head part and a cylindrical insertion part, the cylindrical insertion part is tightly inserted into the inner hole of the second end of the heating tube body, the conical head part is exposed outside the heating tube body, and the pointed plug and the heating tube body are sintered into a whole. According to the hollow pointed-end heating rod disclosed by the utility model, the heating tube body is hollow, so that the actual volume is smaller than that of a conventional solid heating rod, the mass is smaller, and the temperature rise is faster.

The invention relates to a low-defect high-selection-ratio core-shell composite abrasive material, a preparation method and a polishing solution, and belongs to the technical field of chemical mechanical polishing of integrated circuits, the low-defect high-selection-ratio core-shell composite abrasive material comprises a multilayer structure formed by an inner core and an outer shell, and the inner core comprises alpha-phase aluminum oxide particles and gamma-phase aluminum oxide particles; the preparation method of the Al2O3-coated SiO2-Betaine comprises the following steps of: mixing an inner core, coating the outer shell with a silicon oxide coating layer, performing grafting modification on the surface of the silicon oxide coating layer through a betaine type zwitterionic compound to obtain Al2O3-coated SiO2-Betaine, performing mixing on the inner core, coating the outer shell, dispersing core-shell particles, preparing modifier hydrolysate and performing surface grafting to obtain the Al2O3-coated SiO2-Betaine, and the Al2O3-coated SiO2-Betaine can be used for preparing a polishing solution. Through the unique three-layer structure design of the hard core, the soft shell and the surface modification, high removal rate, low defect and controllable selection ratio are synchronously realized.

The invention belongs to the technical field of digital chip system design, and provides a multi-cycle path synchronization circuit which comprises at least one multi-cycle path synchronization sub-circuit. Each multi-cycle path synchronization sub-circuit comprises a counter, combinational logic, a first-class trigger group, a second-class trigger group located in front of a clock gate, the clock gate and a plurality of second-class trigger groups located in hard cores, and a chip is subjected to hard core division to obtain a plurality of hard cores; and each multi-cycle path synchronization sub-circuit is provided with a second type trigger group in each hard core. And a trigger group is inserted into a related path, so that the time sequence is optimized without influencing the area and the performance.

A system and method for securing a system-on-chip (SoC) field programmable gate array (FPGA) is provided, wherein the SoC FPGA includes an FPGA fabric, a soft core processor hosted within the FPGA fabric, a hard core processor, and a secure boot environment for the SOC FPGA. Monitoring logic monitors for a change in the FPGA fabric. External watchdog logic is configured to receive a trigger signal from the monitoring logic, and force the hard core processor(s) of the SoC FPGA into a reset state with no ability to recover unless power is cycled when a change has been made to the FPGA fabric, so as to provide a “fail secure” scenario. The monitoring logic may be firmware hosted on the FPGA fabric, software hosted on the soft core, software hosted on the hard core, and / or external hard logic.

The invention relates to separation of metal and non-metal parts, in particular to the technical field of rubber hose hard core method production, and discloses a rubber hose hard core removing machine and a core removing method.The rubber hose hard core removing machine comprises a bottom beam, a vibration part is installed on the bottom beam, an adjusting part is further installed on the bottom beam, and a side beam is integrally connected to the bottom beam; a first driving part is installed on the side beam, a second driving part is arranged on the first driving part, a guide part is connected to the second driving part, the vibration part comprises a machine box, the machine box is fixedly connected to one end of the bottom beam, and an ultrasonic transducer, an amplitude-change pole and a vibration sleeve are arranged through the vibration part. A micron-sized instantaneous gap is formed between the hard core mold and the inner rubber of the rubber pipe, the viscous attaching state of the hard core mold and the inner rubber is destroyed, rigid contact friction between the hard core and the inner rubber is fundamentally eliminated, the technical problems that the inner wall of the rubber pipe is scratched and peeled due to an existing rigid pulling force depoling mode are solved, and the lossless machining effect in the depoling process of the rubber pipe is achieved.

To provide a core that can be used repeatedly.SOLUTION: A core 3 includes: a soft core 5 that comes into contact with a raw material; and a hard core 4 that is arranged inside the soft core 5 and reinforces the soft core 5. The soft core 5 and the hard core 4 are provided with a soft resin and a hard resin. At the time of demolding, the hard core 4 is removed from the soft core 5, and the soft core 5 is deformed to remove it from a molded body 6. The hard core 4 and the soft core 5 are reused.SELECTED DRAWING: Figure 1

This application discloses a method, apparatus, device, and medium for online backplane upgrades, relating to the field of computer technology. The method includes: receiving an online upgrade command and filtering out the target backplane soft core address corresponding to the online upgrade command; determining the target soft core channel and target hard core channel corresponding to the target backplane soft core address from soft core channels and hard core channels connected to the motherboard; closing the target soft core channel and opening the target hard core channel to upgrade the target backplane corresponding to the online upgrade command through the target hard core channel, obtaining an upgraded backplane; and closing the target hard core channel and opening the target soft core channel. When multiple identical backplanes exist in the same group of I2C BUS, the above solution, utilizing the target backplane soft core address and switching between soft core channels and hard core channels, enables low-cost and low-complexity backplane upgrades.

This invention discloses a chip that saves bus traces, including a master hard core module and at least two slave hard core modules. The master hard core module includes a chip bus master device, and the slave hard core modules include an instruction conversion unit, a data synchronization unit, and registers. The chip bus master device generates JTAG instructions and sends the clock signal, TMS signal, and TDI signal contained in the JTAG instructions to each instruction conversion unit via the TCK signal line, TMS signal line, and TDI signal line, respectively. The instruction conversion unit converts the TDI signal into an APB operation instruction and sends it to the data synchronization unit. Driven by the clock signal, the output data based on the TMS signal and TDI signal is obtained and sent to the chip bus master device via the TDO signal line. The data synchronization unit performs timing synchronization of the APB operation instructions and sends them to the registers for configuration. The chip bus master device selects each output data and outputs it to the APB. Applying this invention can achieve low power consumption.

The present invention provides an FPGA-based circuit system for balancing clock skew and a control method. The system comprises: a hard core circuit module comprising a clock source unit, a delay control unit and a first interaction unit, wherein the clock source unit generates a source clock, and the delay control unit generates a delay clock and an in-phase signal on the basis of the source clock and an in-core source clock; and an FPGA module comprising a clock dedicated wire unit and a second interaction unit, wherein the clock dedicated wire unit generates the in-core source clock on the basis of the delay clock, the first interaction unit transmits and receives data under the control of the source clock and the in-phase signal, and the second interaction unit transmits and receives data under the control of the in-core source clock and the in-phase signal. In this way, the delay control unit is used to balance clock skew between a register at a clock source end and a register on an FPGA, so that the FPGA module can effectively reduce the clock skew without increasing hardware resources, thereby solving the problem of how to effectively balance the clock skew without increasing FPGA hardware resources.