30 results about "Hard core" patented technology

The present invention relates to a photonic crystal coating, a preparation method, and its application, belonging to the technical field of photonic crystal structure color generation. The photonic crystal coating comprises the following components, measured in parts by weight: 100 parts of a hard-core-soft-shell nanosphere dispersion, 1 to 8 parts of a leveling agent, 0.1 to 0.4 parts of a stray light absorber, and 0 to 6 parts of a high-boiling-point additive. The photonic crystal coating is directly prepared from hard-core-soft-shell colloidal nanospheres. The resulting structural color coating exhibits excellent structural stability (associated with high color fastness), high color saturation, and a significant iridescent effect.

The invention relates to the technical field of chip simulation, in particular to a chip simulation method, a chip simulation device, chip simulation equipment and a medium, the method comprises the following steps: in a comprehensive logic stage of a chip, performing comprehensive logic simulation after reading an actual layout plan to obtain a comprehensive netlist, the comprehensive netlist comprises interconnection line delay data and time sequence library information, the layout planning comprises specific position information of a hard core and a standard unit of the chip; generating a standard delay format file according to the interconnection line delay data and the time sequence library information; the integrated netlist and the standard delay format file are read into a static time sequence analysis tool for integration post-simulation, and a time sequence report is obtained; and determining whether a time sequence problem exists or not according to the time sequence report, and if so, repairing the path with the time sequence problem. According to the method, the accurate delay problem can be obtained through quick simulation.

The invention discloses a preparation method of a core-shell structure hard alloy with high strength and high toughness, and belongs to the technical field of hard alloys and powder metallurgy. According to the preparation method, a micro heterostructure is formed after sintering through a pre-constructed'fine grain hard core-coarse grain tough shell 'powder system, and deflection and energy dissipation are promoted during crack propagation by utilizing the performance difference and interfacial effect between the core and a matrix, so that the strength and toughness of the material are synergistically improved. The method is simple in process and low in cost, the material performance can be flexibly designed by adjusting the core particle size, the core-shell components and the core-shell proportion, and the method is suitable for tools, drilling tools, wear-resistant parts and the like with strict requirements for obdurability.

The invention relates to an instrument channel capable of realizing multi-angle deformation, which is used for being matched with a hard core rod to be used as a puncture outfit, and a main body is a deformable sheath tube; the deformable sheathing canal comprises a sheathing canal head, a flexible sheathing canal and a sheathing canal tail which are sequentially connected from top to bottom, and the flexible sheathing canal is made of a soft material; a plurality of sheathing canal supporting rings which are sequentially arranged from top to bottom are attached to the inner wall of the flexible sheathing canal. Compared with the prior art, the device has the unique advantage of super-large bendable angle, in the operation process, an operator can adjust the position and direction of entering an instrument according to the actual scene requirement, the device is not affected by the straight-in and straight-out form of a traditional puncture sheath, the device can be adjusted to the designated position more flexibly in the operation application process, and therefore the operation difficulty is reduced, and the operation time is shortened.

1. The name of the design product: jacket (high-performance multi-scene hard core lifesaving). 2. The use of the design product: for use in jackets. 3. The design points of the design product: in shape. 4. The picture or photo that best indicates the design points: reference Figure 1 in use. 5. The design product is a thin product, and other views are omitted. 6. The mannequin in the design picture is a prop and does not belong to the protected design content.

The invention discloses an embedded ARM hardcore FPGA time sequence simulation test method and system, and aims to overcome the defects of low hardcore FPGA time sequence simulation test efficiency and test quality caused by lack of a time sequence simulation model in a tested netlist in the prior art. The system comprises a test bed, an interface simulation model module and a signal mapping module, the test bed provides a simulation test environment, the interface simulation model module is connected to the test bed to simulate an ARM hardcore interface protocol behavior, and the signal mapping module realizes signal mapping of a netlist and the test bed through a simulation tool system task. The method is based on the system, a corresponding interface simulation model is selected according to an ARM hardcore interface protocol, a test bed interface signal is defined, a system task mapping signal is called, a model port is bound to replace an original model, a file is compiled to execute time sequence simulation, and waveform verification is observed. According to the method, the defect of model deficiency is made up, the testing efficiency and quality are greatly improved, and the requirement for time sequence simulation testing of the hard-core FPGA is met.

The invention belongs to the technical field of composite material processing, and provides a method for removing a hard core material of a composite material, which comprises the following steps of: determining a position close to a hole according to a defect range; covering a metal protective plate on the defect, and forming a through hole; primary holes are formed in the upper panel and the core material according to the positions of the through holes; removing tools including a spherical grinding tool and a cylindrical grinding tool are designed; the removing tool is used for conducting graded grinding till the core material is completely removed; core material powder is sucked out in a vacuum mode, and the metal protection plate is removed; and the initial hole is expanded to the final hole to facilitate the use in the subsequent process. The technical problem that no applicable maintenance scheme for the debonding defect of the existing foam sandwich structure exists is solved, and the selective removal of the core material is realized on the premise of ensuring the relative completeness of the panel interface.

The utility model discloses a novel mechanical sealing structure, and relates to the technical field of sealing. The pipe joint comprises a pipe end to be connected, an inner connecting pipe, an outer sleeve, an inner seal and a push ring, a machine connecting seat is arranged at one end of the inner connecting pipe, the inner connecting pipe and the outer sleeve are integrally provided with flanges and are concentrically connected through bolts, the inner seal comprises a hard core ring, an embedded groove is formed in one side of the hard core ring, and a convex ring part is arranged on the inner side of the other side of the hard core ring. By designing the novel sealing structure, the connection sealing between the pipe end to be connected and the inner connecting pipe can be realized through the matching of the inner seal and the sealing ring, the connection sealing between the outer sleeve and the inner connecting pipe can be realized through the matching of the inner seal, the push ring and the sealing mechanism, the sealing effect is better, and meanwhile, if the loosening condition occurs, the sealing effect is better. The sealing effect between the push ring and the inner seal can be continuously maintained through the elastic force of the spring, and the sealing effect of the sealing point is greatly improved.

1. The name of the design product: mattress (hard core Lite2 generation). 2. The use of the design product: for mattress. 3. The design points of the design product: in shape. 4. The picture or photo that best indicates the design points: perspective view.

The invention provides acrylate latex as well as a preparation method and application thereof, and belongs to the technical field of pressure-sensitive adhesives. The acrylate latex provided by the invention has a core-shell structure with a hard core and a soft shell, the inner core is the acrylate copolymer with a high glass transition temperature, high cohesion is provided, the creep resistance of the pressure-sensitive adhesive is ensured, the glass transition temperature of the inner core is-25-30 DEG C, and the pressure-sensitive adhesive has the best adhesive overflow resistance; the shell is made of the acrylate copolymer with low glass transition temperature, and the glass transition temperature of the shell is-35 to-65 DEG C, so that the pressure-sensitive adhesive is endowed with enough initial adhesion and stripping force, and the adhesive property is ensured. The result of the embodiment of the invention shows that the initial adhesion of the acrylate latex provided by the invention is more than 10N / 25mm, the 90-degree stripping force is more than 7N / 25mm, the permanent adhesion is not displaced for 120 hours, and the acrylate latex has good comprehensive performance.

A system and method for securing a system-on-chip (SoC) field programmable gate array (FPGA) is provided, wherein the SoC FPGA includes an FPGA fabric, a soft core processor hosted within the FPGA fabric, a hard core processor, and a secure boot environment for the SOC FPGA. Monitoring logic monitors for a change in the FPGA fabric. External watchdog logic is configured to receive a trigger signal from the monitoring logic, and force the hard core processor(s) of the SoC FPGA into a reset state with no ability to recover unless power is cycled when a change has been made to the FPGA fabric, so as to provide a “fail secure” scenario. The monitoring logic may be firmware hosted on the FPGA fabric, software hosted on the soft core, software hosted on the hard core, and / or external hard logic.

The invention relates to the field of abrasive discs, and particularly discloses a soft and hard matrix composite type wet and dry abrasive disc. The grinding block composed of the outer soft wrapping layer and the inner hard grinding block is arranged on the substrate, and when the grinding block is used for grinding, the outer soft wrapping layer can serve as a buffer barrier between the terrace and the inner hard grinding block, so that the inner hard grinding block is prevented from leaving deep scratches on the ground; meanwhile, the inner hard grinding block can also serve as a hard core of the outer soft wrapping layer, excessive deformation of the outer soft wrapping layer is avoided, abrasion of the outer soft wrapping layer is reduced, the service life of the outer soft wrapping layer is prolonged, and due to the arrangement of the outer-soft-inner-hard grinding block structure, the service life of the outer soft wrapping layer is prolonged, and the service life of the outer soft wrapping layer is prolonged. And deeper grinding scratches can be prevented from being left on the ground, and the grinding machine can be suitable for grinding the ground made of different materials and has high practicability.

The utility model discloses a hollow pointed-end heating rod, which comprises a heating pipe body and a pointed-end plug, the heating pipe body is a hollow thin-wall piece formed by winding a casting sheet around an auxiliary hard core rod for two circles, then pressing by using an isostatic pressing process, and drawing out the hard core rod after pressing; the tail end of the tape casting sheet in the winding direction is coated with glue; a heating circuit is printed on the casting sheet, an electrode of the heating circuit is connected with a lead, and the heating tube body is provided with a first end for mounting the lead and a second end for mounting the pointed plug; the pointed plug comprises a conical head part and a cylindrical insertion part, the cylindrical insertion part is tightly inserted into the inner hole of the second end of the heating tube body, the conical head part is exposed outside the heating tube body, and the pointed plug and the heating tube body are sintered into a whole. According to the hollow pointed-end heating rod disclosed by the utility model, the heating tube body is hollow, so that the actual volume is smaller than that of a conventional solid heating rod, the mass is smaller, and the temperature rise is faster.

The invention relates to a low-defect high-selection-ratio core-shell composite abrasive material, a preparation method and a polishing solution, and belongs to the technical field of chemical mechanical polishing of integrated circuits, the low-defect high-selection-ratio core-shell composite abrasive material comprises a multilayer structure formed by an inner core and an outer shell, and the inner core comprises alpha-phase aluminum oxide particles and gamma-phase aluminum oxide particles; the preparation method of the Al2O3-coated SiO2-Betaine comprises the following steps of: mixing an inner core, coating the outer shell with a silicon oxide coating layer, performing grafting modification on the surface of the silicon oxide coating layer through a betaine type zwitterionic compound to obtain Al2O3-coated SiO2-Betaine, performing mixing on the inner core, coating the outer shell, dispersing core-shell particles, preparing modifier hydrolysate and performing surface grafting to obtain the Al2O3-coated SiO2-Betaine, and the Al2O3-coated SiO2-Betaine can be used for preparing a polishing solution. Through the unique three-layer structure design of the hard core, the soft shell and the surface modification, high removal rate, low defect and controllable selection ratio are synchronously realized.

The present invention discloses a soft error injection method and an FPGA chip. The method is applied to the soft core IP of an FPGA chip. The injection interface of a soft error correction (SEC) hard core in the FPGA chip is encapsulated in the soft core IP. The method comprises: receiving a setting signal from a user to obtain setting information; generating soft error injection information based on the setting information; and sending the soft error injection information to the SEC hard core via the injection interface, so that the SEC hard core injects soft errors according to the soft error injection information. The present invention does not rely on the JTAG interface when performing soft error injection, occupies less FPGA resources, and has high injection efficiency.

The invention belongs to the technical field of digital chip system design, and provides a multi-cycle path synchronization circuit which comprises at least one multi-cycle path synchronization sub-circuit. Each multi-cycle path synchronization sub-circuit comprises a counter, combinational logic, a first-class trigger group, a second-class trigger group located in front of a clock gate, the clock gate and a plurality of second-class trigger groups located in hard cores, and a chip is subjected to hard core division to obtain a plurality of hard cores; and each multi-cycle path synchronization sub-circuit is provided with a second type trigger group in each hard core. And a trigger group is inserted into a related path, so that the time sequence is optimized without influencing the area and the performance.

The invention discloses a multi-channel NVMe SSD (Non-Volatile Memory Express Solid State Disk) storage acceleration system based on an FPGA (Field Programmable Gate Array), which is used for reading and writing the multi-channel NVMe SSD and comprises an NVMe Target controller, a Raid controller, a DDR (Double Data Rate) controller and NVMe Host controllers, the number of the NVMe Host controllers corresponds to that of the NVMe SSD, and the NVMe Host controllers are connected with the NVMe SSD in a one-to-one correspondence manner. According to the FPGA-based multi-channel NVMe SSD storage acceleration system, the device end is presented to the CPU host end, so that the CPU host end performs synchronous read-write operation on the multi-channel NVMe SSD of the device end, storage resource pooling is realized, the CPU host end can conveniently manage and maintain the device end, and the working efficiency is further improved; in the system, the number of the NVMe SSDs depends on the number of links between the NVMe Host controller and the NVMe SSDs in the system, a PCIe hard core controller and a PCIe exchange chip are not needed, the whole system is simpler, and the cost is lower; and meanwhile, the RAID function in the scheme does not depend on an external CPU and is autonomously realized by the storage acceleration system.

A system and method for securing a system-on-chip (SoC) field programmable gate array (FPGA) is provided, wherein the SoC FPGA includes an FPGA fabric, a soft core processor hosted within the FPGA fabric, a hard core processor, and a secure boot environment for the SOC FPGA. Monitoring logic monitors for a change in the FPGA fabric. External watchdog logic is configured to receive a trigger signal from the monitoring logic, and force the hard core processor(s) of the SoC FPGA into a reset state with no ability to recover unless power is cycled when a change has been made to the FPGA fabric, so as to provide a “fail secure” scenario. The monitoring logic may be firmware hosted on the FPGA fabric, software hosted on the soft core, software hosted on the hard core, and / or external hard logic.

The invention relates to separation of metal and non-metal parts, in particular to the technical field of rubber hose hard core method production, and discloses a rubber hose hard core removing machine and a core removing method.The rubber hose hard core removing machine comprises a bottom beam, a vibration part is installed on the bottom beam, an adjusting part is further installed on the bottom beam, and a side beam is integrally connected to the bottom beam; a first driving part is installed on the side beam, a second driving part is arranged on the first driving part, a guide part is connected to the second driving part, the vibration part comprises a machine box, the machine box is fixedly connected to one end of the bottom beam, and an ultrasonic transducer, an amplitude-change pole and a vibration sleeve are arranged through the vibration part. A micron-sized instantaneous gap is formed between the hard core mold and the inner rubber of the rubber pipe, the viscous attaching state of the hard core mold and the inner rubber is destroyed, rigid contact friction between the hard core and the inner rubber is fundamentally eliminated, the technical problems that the inner wall of the rubber pipe is scratched and peeled due to an existing rigid pulling force depoling mode are solved, and the lossless machining effect in the depoling process of the rubber pipe is achieved.

To provide a core that can be used repeatedly.SOLUTION: A core 3 includes: a soft core 5 that comes into contact with a raw material; and a hard core 4 that is arranged inside the soft core 5 and reinforces the soft core 5. The soft core 5 and the hard core 4 are provided with a soft resin and a hard resin. At the time of demolding, the hard core 4 is removed from the soft core 5, and the soft core 5 is deformed to remove it from a molded body 6. The hard core 4 and the soft core 5 are reused.SELECTED DRAWING: Figure 1

This application discloses a method, apparatus, device, and medium for online backplane upgrades, relating to the field of computer technology. The method includes: receiving an online upgrade command and filtering out the target backplane soft core address corresponding to the online upgrade command; determining the target soft core channel and target hard core channel corresponding to the target backplane soft core address from soft core channels and hard core channels connected to the motherboard; closing the target soft core channel and opening the target hard core channel to upgrade the target backplane corresponding to the online upgrade command through the target hard core channel, obtaining an upgraded backplane; and closing the target hard core channel and opening the target soft core channel. When multiple identical backplanes exist in the same group of I2C BUS, the above solution, utilizing the target backplane soft core address and switching between soft core channels and hard core channels, enables low-cost and low-complexity backplane upgrades.

The present invention discloses a collagen-based hard-core sandwich composite membrane for guiding bone regeneration, and its preparation method and application, which belong to the technical field of biomedical materials. The composite membrane of the present invention consists of a hard core and a soft shell. The present invention cross-links and biomimetic mineralizes self-assembled collagen fibers through a dicarboxylic acid ester cross-linking agent and Zr-MOP to form a hard-core cross-linked mineralized collagen fiber membrane, and then wraps it with a soft-shell methacrylated collagen gel, and presses it to obtain the membrane. The soft shell of the composite membrane of the present invention is loose and porous, which is conducive to the adhesion and proliferation of bone cells; the hard core is a dense layer, which can provide better support performance and effectively block epithelial cells and fibroblasts from invading the osteogenic area; the controllable pore structure provided by Zr-MOP can ensure normal material exchange in the defect area. Therefore, the composite membrane of the present invention has high mechanical strength, controllable degradation rate and good biocompatibility, and can play a good barrier role and promote bone regeneration in the process of bone repair.

The invention relates to the technical field of oral cavity materials, and discloses a novel root canal filling composite material and a preparation method thereof.The composite material comprises a solid hard core and a pasty paste material, and the outer surface of the hard core is evenly coated with the paste material; the hard core is prepared from the following raw materials: medical synthetic eucommia ulmoides rubber, liquid rubber, a silane coupling agent, white carbon black, an anti-aging agent, zinc oxide, stearic acid, an accelerant, sulfur and barium sulfate; the paste material comprises medical synthetic eucommia ulmoides rubber, zinc oxide and barium sulfate. The method has excellent operability and enhanced sealing performance, damage to periapical tissues can be reduced, and processing safety and system hardness are improved.

1. The name of the design product: mattress (hard core Max2 generation). 2. The use of the design product: for mattress. 3. The design points of the design product: in shape. 4. The picture or photo that best indicates the design points: perspective view.

The invention discloses a chip capable of saving bus routing, which comprises a master hardcore module and at least two slave hardcore modules, the master hardcore module comprises a chip bus master device, each slave hardcore module comprises an instruction conversion unit, a data synchronization unit and a register, the chip bus master device generates a JTAG instruction, and the JTAG instruction is transmitted to the slave hardcore module. A clock signal, a TMS signal and a TDI signal contained in a JTAG instruction are sent to each instruction conversion unit through a TCK signal line, a TMS signal line and a TDI signal line respectively, and the instruction conversion unit converts the TDI signal into an APB operation instruction and sends the APB operation instruction to the data synchronization unit; under the driving of the clock signal, based on the TMS signal and the TDI signal, obtaining output data, and sending the output data to a chip bus master device through a TDO signal line; the data synchronization unit carries out time sequence synchronization on the APB operation instruction and sends the APB operation instruction to the register for configuration; and the chip bus master device selects the output data and outputs the output data to the APB. According to the invention, low power consumption can be realized.

The invention discloses a high-speed broadband large-capacity data storage and reading method based on an SSD (Solid State Disk), which comprises the following steps of: firstly, storing data needing to be stored in an FPGA (Field Programmable Gate Array), and then controlling solid-state storage equipment through the FPGA, so that the storage rate is improved; specifically, a PCIe device is initialized, link establishment of a PCIe protocol and initialization configuration of an NVMe protocol are completed, then stored data are stored in an FPGA, an NVMe instruction is generated according to the size and position of data needing to be read or written, the NVMe instruction is transmitted and cached in the FPGA, and after a command is issued to an SSD device through a PCIe hardcore, the SSD device sends the command to the PCIe device. And when the NVMe instruction is received, the SSD goes to the buffer to fetch the instruction, the SSD performs a corresponding read-write function according to the obtained NVMe instruction, and goes to the BRAM to read data or write the data into the BRAM. In this way, in the whole processing process, the transmission speed of instructions and data is greatly increased.

This invention discloses a chip that saves bus traces, including a master hard core module and at least two slave hard core modules. The master hard core module includes a chip bus master device, and the slave hard core modules include an instruction conversion unit, a data synchronization unit, and registers. The chip bus master device generates JTAG instructions and sends the clock signal, TMS signal, and TDI signal contained in the JTAG instructions to each instruction conversion unit via the TCK signal line, TMS signal line, and TDI signal line, respectively. The instruction conversion unit converts the TDI signal into an APB operation instruction and sends it to the data synchronization unit. Driven by the clock signal, the output data based on the TMS signal and TDI signal is obtained and sent to the chip bus master device via the TDO signal line. The data synchronization unit performs timing synchronization of the APB operation instructions and sends them to the registers for configuration. The chip bus master device selects each output data and outputs it to the APB. Applying this invention can achieve low power consumption.

The present invention provides an FPGA-based circuit system for balancing clock skew and a control method. The system comprises: a hard core circuit module comprising a clock source unit, a delay control unit and a first interaction unit, wherein the clock source unit generates a source clock, and the delay control unit generates a delay clock and an in-phase signal on the basis of the source clock and an in-core source clock; and an FPGA module comprising a clock dedicated wire unit and a second interaction unit, wherein the clock dedicated wire unit generates the in-core source clock on the basis of the delay clock, the first interaction unit transmits and receives data under the control of the source clock and the in-phase signal, and the second interaction unit transmits and receives data under the control of the in-core source clock and the in-phase signal. In this way, the delay control unit is used to balance clock skew between a register at a clock source end and a register on an FPGA, so that the FPGA module can effectively reduce the clock skew without increasing hardware resources, thereby solving the problem of how to effectively balance the clock skew without increasing FPGA hardware resources.