Embedded cubic star task computer based on FPGA (Field Programmable Gate Array) and reconstruction method thereof

Abstract

The invention provides an embedded cubic star task computer based on an FPGA (Field Programmable Gate Array). The computer comprises a processing chip, wherein the processing chip is integrated with an FPGA hard core, an FPGA logic unit and a CPU (Central Processing Unit) inner core; the FPGA hard core is used for communicating with a peripheral circuit and various subsystems of a cubic star; the FPGA logic unit is used for controlling the peripheral circuit and meanwhile timing the star task local time of the cubic star; the CPU inner core is used for performing whole star control algorithm implementation, whole star data management, gesture control algorithm implementation, control command dispatching and load data management on the cubic star. The embedded cubic star task computer has the advantages of flexibility in use, optimized performance, high integration level, low cost and high reliability.

Description

technical field [0001] The invention relates to the fields of aerospace and electronic science and technology, in particular to an FPGA-based embedded cubic star service computer, a starting method thereof, and an on-orbit reconfiguration method. Background technique [0002] With the rapid development of aerospace and electronic science and technology in recent years, micro-nano satellites with low cost, low weight and high functional density have been widely used in earth observation, electronic reconnaissance, communication, navigation, space science detection, space detection and new technologies. Technology experiments and many other fields, and has become an important part of the space system. The cube star is a special kind of micro-nano satellite, which was proposed by Bob Twiggs of Stanford University in 1999. A cube star is a cube with a side length of 10cm, its power consumption is in the range of a few watts, and its weight is about 1~2kg. According to the need...

AI Technical Summary

Problems solved by technology

The disadvantages are: Andrews Model 160 is very expensive ($77,500), and it is designed with a high-power SRAM-type FPGA as the core, which consumes a lot of power. At the same time, the configuration cells of the SRAM-type FPGA are very sensitive to spatial single event effects , single event upset (Single-Event-Upset, referred to as SEU) events are more likely to occur. Even if the anti-radiation hardening measures on the software are taken, it needs to be reloaded from the external EEPROM, resulting in the temporary loss of system functions.

In addition, this star computer is embargoed to China. Therefore, it cannot be used in China to carry out high-performance star computer design.

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