136results about "Electric unknown time interval measurement" patented technology

The invention relates to a carry chain calibration method and device, a time measurement unit and equipment. The method comprises the following steps: acquiring a bit output sequence of a carry chain; segmenting the bit output sequence to obtain a plurality of segments to be processed; screening a target segment from the segments to be processed, and counting the number of times that each bit carry output is 1 in the target segment; and generating a remapping table of the physical bit position and the logic bit index of the carry chain based on the number of times that each bit carry output in each target segment is 1, and remapping the bit output sequence of the carry chain. By adopting the method, the precision of the multi-stage carry chain can be improved, so that systematic jitter is inhibited.

The invention relates to a two-step time-to-digital converter and a method thereof, a phase-locked loop and an analog-to-digital converter. The method comprises the following steps of: performing N1-stage delay on a reference signal rs in sequence, and performing coarse quantization on the delayed signal of each stage relative to a feedback signal fb; when the two signals are different, after the time t1 is delayed, the first arriving signal is selected as a time starting signal Start and the fb is delayed for the time t1 and then serves as a time stopping signal Stop in the delayed period, and when the two signals are the same, the rs is selected as Start after the time t2 is delayed, and the fb is selected as Stop after the time t2 is delayed; performing fine quantization formation on the Start and the Stop; and decoding the code into n1-bit high-bit binary codes and decoding the code into n2-bit low-bit binary codes. The technical problem that the area and power consumption of an existing two-step TDC are increased due to the fact that the number of logic gates of a selector is greatly increased along with the increase of coarse quantization bits is solved.

A clock device is in communication with a remote computing device that is configured to adjust the time of a countdown and define an adjusted time value. The remote device communicates the adjusted time to the clock device, which automatically displays the adjusted time on a screen. The adjusted time is further communicated to a cloud server via API. The adjusted time is accessible by authorized third parties for display or broadcast. Accordingly, a user may adjust and track a countdown and may define an official time that is automatically displayed to a variety of end-users in real-time. The clock device may be positioned adjacent a competition area and may include a rigid metal frame and a flexible LED screen extending around the perimeter of the frame. The clock device may include hardware and software for processing and outputting the adjusted time to the cloud server.

The application discloses a time-to-digital converter based on pulse stretching. The time-to-digital converter structure combines frequency multiplication delay locked loop, pulse stretching circuit and calibration circuit, guarantees high resolution, effectively increases the range of the time-to-digital converter, and can reduce the influence of PVT. The calibration circuit has simple structure, low calibration cost, and is suitable for the calibration of the pulse stretching circuit. In addition, the calibration algorithm for the static phase error of the frequency multiplication delay locked loop only needs to increase a 1bit counter, the additional circuit cost is very small, and the influence of the static phase error of the frequency multiplication delay locked loop can be overcome.

This application relates to a high-precision timing system and method based on dual-channel time measurement. The system includes: a filtering module for receiving analog signals output from a particle detector, filtering and denoising the analog signals, and converting the processed signals into two co-source valid signals for output; a time measurement module for receiving the two co-source valid signals, and by configuring a first discrimination threshold and a second discrimination threshold, performing discrimination processing on the two co-source valid signals respectively, capturing the characteristic time when each signal reaches the corresponding discrimination threshold, and outputting the first characteristic time and the second characteristic time; and a data processing module for calculating and storing the high-precision arrival time based on the approximately linear characteristics of the rising edge of the signal pulse, according to the first discrimination threshold, the second discrimination threshold, the first characteristic time, and the second characteristic time. Using this system, particle arrival time measurement can be achieved with both stability and high precision, meeting the application requirements of high-precision timing scenarios.

The application relates to a configurable time domain pipeline analog-to-digital converter, comprising: a first configurable analog-to-digital converter and a plurality of cascaded second configurable analog-to-digital converters, wherein the first configurable analog-to-digital converter serves as a first stage of the configurable time domain pipeline analog-to-digital converter, is used for converting an input voltage signal into a time signal, and transmitting the quantized time signal to the plurality of cascaded second configurable analog-to-digital converters; the second configurable analog-to-digital converter is used for amplifying and quantizing the input residual time signal stage by stage to generate corresponding digital codes and residual time signals; wherein the first configurable analog-to-digital converter and the second configurable analog-to-digital converter realize the time gain configurable function through a set of discharge and charge switch capacitor arrays. The application adopts the structure of the configurable TA and SA TDC, avoids the use of a voltage amplifier, has high linearity, meets the precision configuration requirements of the ADC, and does not need a time residual generator.

The invention relates to a satellite clock frequency difference and phase difference determination method, system and device, a medium and a product, and the method comprises the steps: carrying out the bidirectional comparison clock difference measurement of adjacent satellites when a time-frequency reference reported by an operation control center is received, and obtaining the initial frequency difference and initial phase difference of a satellite clock; performing volume Kalman filtering prediction on the initial phase difference according to the current time frequency information and a clock phase difference value at a previous moment of the current moment to obtain a phase difference prediction value; according to a preset period, taking a frequency difference average value measured by the neighbor satellites of the adjacent satellites as a target frequency difference of a satellite clock, and taking a phase difference average value measured by the adjacent satellites as an updated initial phase difference; and processing the phase difference predicted value, the target frequency difference and the updated initial phase difference by adopting a volume Kalman filtering strategy to obtain the target phase difference of the satellite clock, so that an accurate adjustment basis is provided for calibration of the satellite clock, and the clock synchronization precision is improved.

The application discloses a kind of based on limited observation data's simulation residual determination method, comprising: pulsar observation data is obtained after processing timing residual, timing residual includes time value and timing residual value;Timing residual value is arranged from big to small, corresponding time value is also arranged;The number of sample timing residual value in different interval range is counted, and the frequency distribution diagram of sample timing residual value in different interval is drawn;Determine the probability statistical distribution model to which frequency distribution belongs;Specific parameters of probability statistical distribution model are solved;The number of simulation residual value is determined;According to probability statistical distribution model, simulation is obtained simulation residual value, set corresponding time value for simulation residual value, simulation residual value is added to sample observation data.The application establishes probability statistical model based on actual data according to the actual residual data obtained, and then simulates to obtain simulation residual value according to the model, which is closer to the original sample value, and improves the accuracy of pulsar time.

The invention discloses a time-to-digital converter based on a vernier double-chain structure, and relates to the technical field of integrated circuits. The converter comprises a signal holding circuit, a vernier double-chain rough measurement module, a data selector, a special time amplifier module and a digital coding unit, the vernier double-chain rough measurement module is composed of a main delay chain and a vernier delay chain, and 10ps-level rough measurement is achieved by adjusting the width-to-length ratio of an MOS tube of a phase inverter to control the delay difference of a unit. The data selector gates a residual time difference signal to the special time amplifier module, and the special time amplifier module is matched with a transmission gate through an RC network to realize 11mV / ps high-linearity time-voltage conversion; the digital coding unit integrates the rough measurement result and the accurate measurement result, and finally the 3.0 ps system resolution is achieved. A'rough measurement-fine measurement 'two-stage measurement architecture is adopted, a single-amplifier time division multiplexing design is adopted, a measurement dead zone is effectively eliminated, the chip area and power consumption are greatly reduced, and the device is particularly suitable for high-precision time measurement application such as laser radar and quantum calculation.

Monitoring track tension of track-enabled work machines using work machine acceleration and transmission speed sensors is provided. When a speed change of a work machine is detected, a timer is started. When an acceleration or deceleration of the work machine is detected, the timer is stopped. Elapsed time between the start of the speed change and the detection of acceleration or deceleration may indicate an amount of time required for taking up slack or sag in a work machine track. If the time required for taking up the slack or sag is excessive, an indication may be received that the track is too loose. If time required for taking up the slack or sag is minimal, an indication may be received that the track is too tight. The determination of the time required for taking up the slack or sag may indicate that tension in the track requires adjustment.

The invention discloses a bipolar voltage-time converter based on phase inverter threshold detection. The bipolar voltage-time converter is characterized in that a differential sampling circuit is connected with a sign bit comparator and a bipolar voltage-time conversion circuit; the sign bit comparator is used for receiving the differential sampling voltage output by the differential sampling circuit and judging the polarity of an input differential analog signal, and is connected with the bipolar voltage-time conversion circuit to output a sign bit signal and a polarity control signal; the bipolar voltage-time conversion circuit is used for charging or discharging the differential sampling voltage under the control of the polarity control signal to generate two paths of voltage ramp signals with opposite polarities, and is connected with the common-mode feedback circuit and the inverter threshold detection circuit; the common-mode feedback circuit is used for detecting a common-mode level of the differential sampling voltage or two paths of voltage ramp signals; the threshold voltage of the inverter threshold detection circuit is configured to be a predetermined common-mode level, and is used for detecting a crossover event of the two voltage ramp signals at the predetermined common-mode level and outputting a threshold detection signal.

A processing system includes a peripheral device configured to store security information and having a clock input to receive a gated clock; a watch clock generator configured to generate a watch clock having a reduced duty cycle relative to the system clock; and clock control circuitry configured to select the system clock as a gated clock during normal operation of the peripheral device and select the watch clock as a gated clock during a low power mode of the peripheral device. The watch clock generator may include a counter that counts system clock cycles and a clock pulse selector, such as a mode circuit, configured to select the cycles of the system clock to generate a watch clock. For multiple peripherals, the delay circuitry may skew a watch clock between two or more peripherals. A plurality of watch clocks having different delayed duty cycles may be generated, each for a corresponding group of a plurality of groups of peripherals.

The invention provides a pulse timing method and system based on mixed supervised learning and electronic equipment, the method comprises a self-supervised learning part and a weak supervised learning part, and the self-supervised learning part comprises the following steps: carrying out random sub-sequence sampling on sampling waveforms of an analog-to-digital converter at the same or lower sampling rate to obtain sampling sub-sequence matching pairs, recording a label of a self-supervised learning loss function by using the relative position of the sampling sub-sequence matching pair, inputting the sampling sub-sequence matching pair into a neural network, and calculating self-supervised loss; the weak supervision learning comprises the steps of obtaining a reference time sequence and a timing label, inputting the reference time sequence into a neural network, and calculating weak supervision loss; and finally, forming a mixed supervision loss function by the sum of the self-supervision loss and the weak supervision loss, and jointly applying the mixed supervision loss function to neural network reverse conduction training. According to the method, the neural network timing model can be trained under the condition that only a small number of labeled samples are provided, and the purpose of high-precision pulse timing is achieved.

This utility model discloses a comprehensive monitoring sensor for the braking time of a start-stop mechanism brake, relating to the field of brake monitoring technology. The sensor includes an acceleration sensor, a high-voltage detection device, a brake wheel accessory, and a fixing device. The brake wheel accessory includes a mounting frame and a permanent magnet. The fixing device includes a mounting base, with a base fixedly connected to its upper surface. A top cover is positioned directly above the base, and a connecting buckle is provided at the connection between the base and the top cover. Both the base and the top cover contain PCB boards. The outer surface of the PCB boards contains a microcontroller, parallel-input / serial-output IC chips, a Hall effect ring array sensor, and electrical connection pads. This utility model achieves integrated monitoring of brake action time, braking time, running time, brake wheel speed, number of braking cycles, and brake anomalies.

The application discloses a cathode partition-based image intensifier local exposure time and delay calibration system and method, solves the problem that the shortest exposure time calibration of the cathode whole surface of the gated image intensifier cannot distinguish the influence of the gate pulse width and the propagation time, causes the exposure time to be unable to be accurately measured and further introduces the timing error, and the application comprises a femtosecond pulse laser, a half-transmission half-reflection mirror, a gate power module, a CMOS camera, a high-voltage power supply, a signal source, a high-bandwidth oscilloscope, a photoelectric detector and an upper computer; the influence of the gate electric pulse propagation time and the gate electric pulse half-height width on the optical exposure time is decoupled and separated, and is respectively attributed to the sub-area relative delay and the sub-area local exposure time, the time resolution capability of the gated image intensifier can be improved, and the time measurement precision can be improved when the same half-height width of the gate electric pulse is selected for the same gated image intensifier.

The application relates to a TDC system, in particular to a high-resolution TDC system based on a complementary blind mechanism and a time interval measurement method; a first processing chip, as a main processing channel, is responsible for high-speed coarse-grained sampling of a to-be-measured analog signal, determination of a blind area position of a time interval, provision of a coarse delay measurement value, and calculation of a fine time measurement value sent by a second processing chip to obtain a high-precision time interval measurement result; the second processing chip, as an auxiliary processing channel, is responsible for fine complementary blind of the blind area determined by the first processing chip, fine-grained sampling of the to-be-measured analog signal, accurate measurement of a high-resolution fine time measurement value in the blind area, and sending to the first processing chip; the technical scheme provided by the application can effectively overcome the defects of the prior art, i.e., the high-performance TDC solution does not simultaneously consider high resolution, high data bandwidth, high integration and reasonable cost.

The utility model provides a pigeon clock pedal debugging system, and relates to the technical field of debugging systems. A to-be-debugged pigeon clock pedal is arranged at the top of the pedal positioning tool; a receiving coil matched with an induction coil in the pigeon clock pedal to be debugged is mounted in the pedal positioning tool; positioning abutting blocks are arranged on the front side, the left side and the right side of the top of the pedal positioning tool correspondingly. A capacitance adjusting hole of a to-be-debugged pigeon clock pedal faces upwards, and when the front end, the left end and the right end of the to-be-debugged pigeon clock pedal abut against the three positioning abutting blocks, the induction coil and the receiving coil are connected with a power source and the to-be-debugged pigeon clock pedal relative to the pigeon clock host. The receiving coil is connected with the oscilloscope; the technical scheme of the utility model solves the problem that a pigeon clock pedal debugging system capable of quickly and accurately adjusting parameters is urgently needed because the frequency, the phase and the amplitude cannot be quickly and accurately adjusted to factory required parameters in the conventional device.

The application discloses a motion timing method and device, electronic equipment and storage medium, and relates to the technical field of detection. The method comprises the following steps: acquiring instantaneous state information of a target object at each moment in a motion process, wherein the motion process comprises a static state of the target object; for any moment, determining a state difference value of the moment according to the instantaneous state information of the moment and the instantaneous state information of the previous moment; determining a motion starting moment and a motion ending moment of the target object according to the state difference values of the moments and a critical value, wherein the critical value is determined according to the state difference value of the static state of the target object; and determining a motion time of the target object according to the motion starting moment and the motion ending moment. Therefore, the accuracy of detecting the motion time of the moving object is improved.

The present application relates to the technical field of precise time synchronization and trigger control, and particularly relates to a multi-stage system synchronous trigger device and method based on laser pulses. The multi-stage system synchronous trigger device based on laser pulses comprises: a photoelectric detection module, configured to receive laser pulses and convert the laser pulses into initial electrical signals; a constant fraction timing module, connected with the photoelectric detection module, configured to extract a zero-crossing point irrelevant to the amplitude of the laser pulses from the initial electrical signals, take the trigger time of the zero-crossing point as a time zero point, and output a reference trigger signal corresponding to the time zero point; and a trigger signal distribution module, connected with the constant fraction timing module, configured to distribute the reference trigger signal to multiple subsequent devices, so that the trigger time of each subsequent device is traced back to the time zero point.

The present technology pertains to a signal processing device and a distance measuring sensor capable of more appropriately improving distance measuring accuracy. A signal processing device according to the present technology is provided with: a plurality of latch units that hold data based on a light detection signal output from a light detection unit that detects reflected light generated by reflection of laser light by an object; during exposure of the light detection unit, the plurality of latch units output data according to the light detection signal; and during a period except the exposure period, the plurality of latch units output data according to the dummy pulse. The present technology can be applied, for example, to a distance measuring sensor that measures a distance to a measurement object using a ToF method.

The invention provides a fractional phase-locked loop circuit and a working method thereof.The circuit comprises a modulation module, a first digital time converter, a second digital time converter and a phase-locked loop module, and the modulation module is used for outputting a first control signal and a second control signal according to an input frequency control signal; the first digital time converter is used for responding to a first control signal and obtaining a first delay signal according to a reference clock signal, the second digital time converter is used for responding to the first control signal and obtaining a second delay signal according to a feedback clock signal, and the phase-locked loop module is used for responding to a second control signal and obtaining a second delay signal according to a feedback clock signal. And outputting a feedback clock signal with the same frequency as the reference clock signal according to the phase difference between the first delay signal and the second delay signal. The average delay offset of the first digital time converter and the second digital time converter in the circuit is 0, so that the noise and the power consumption of the first digital time converter and the second digital time converter are relatively low.

The application belongs to the field of integrated circuit design, and discloses an undersampling analog-digital conversion circuit for a high-speed radio frequency direct sampling receiver, which comprises a radio frequency input end, a first-stage sampling and holding module, a layered charge distribution time interleaver, a plurality of time domain unit analog-digital conversion channels, and a clock generation and distribution module. By introducing passive charge distribution and a plurality of sub-buffers after single-stage sampling and holding, and by carefully optimizing the time windows and load distribution of each stage, the application can eliminate or significantly weaken the deviation and bandwidth mismatch problems caused by time interleaving from the architecture; at the same time, by using a "ping-pong passive residual transmission" accelerated hybrid time domain unit ADC structure, a high-speed unit ADC at a level of 3GS / s is realized, the length of high-frequency signal wiring and the distributed parasitic are further reduced, and thus the overall spectral purity and energy efficiency are improved.

The invention relates to the technical field of precise time synchronization and trigger control, in particular to a multistage system synchronous trigger device and method based on laser pulses. The multistage system synchronous triggering device based on the laser pulse comprises a photoelectric detection module used for receiving the laser pulse and converting the laser pulse into an initial electric signal; the constant fraction timing module is connected with the photoelectric detection module and used for extracting a zero crossing point irrelevant to the laser pulse amplitude from the initial electric signal, taking the triggering moment of the zero crossing point as a time zero point and outputting a reference triggering signal corresponding to the time zero point; and the trigger signal distribution module is connected with the constant fraction timing module and is used for distributing the reference trigger signal to a plurality of back-stage devices, so that the trigger time of each back-stage device is traced to the time zero point.

The invention provides a multi-path nanosecond time sequence recording method and system, and the method comprises the steps: generating pulses with fixed frequency through an external timing pulse generator, and transmitting the pulses to different electronic devices for time measurement; after the electronic equipment used for time measurement receives the flag bit of the pulse, the flag bit is recorded in a time sequence of the electronic equipment, and the time sequence is recorded as a starting point of a time period; and in a time period, the time of different event signals received by each electronic device for time measurement is subjected to accumulation calculation by taking the time of the starting point as a reference, and a time sequence of each electronic device for time measurement is obtained. According to the method, the problem that multiple paths of TDC circuit signals cannot be synchronized mutually is effectively solved, the overall timestamps are sorted through an internal time calibration method, the expansion capacity of the TDC circuit is remarkably improved, and orderliness among the multiple paths of signals is kept.

This application proposes an anomaly timing processing system and method, relating to the field of electronic digital data processing. The proposed anomaly timing processing system includes an anomaly processing circuit and a timing circuit. The anomaly processing circuit is configured to receive an anomaly signal from a chip, wherein the anomaly signal includes a first type of anomaly signal. The anomaly processing circuit is further configured to receive a timing signal from the timing circuit and generate a first driving signal based on the timing signal and the anomaly signal, for enabling control of the timing circuit. The timing circuit is configured to generate a timing signal with a preset period based on its clock signal under the enabling control of the first driving signal. The timing circuit is also configured to generate a first reporting signal based on the first driving signal and the timing signal. The proposed anomaly timing processing system can generate a reporting signal of suitable duration according to the duration of the anomaly signal and can also achieve flexible processing of different types of anomalies.

The application relates to a correction method and system of a ring oscillator structure TDC, and relates to the technical field of time-to-digital conversion.The application is used to solve the problem that the sampling circuit of the existing ring oscillator structure TDC may be wrong when sampling the output changing delay unit, leading to inaccurate measured time interval.The application can eliminate the error caused by sampling the delay unit near the signal transmission edge by finding the boundary of the ring oscillator unit state change, i.e. the position of the signal transmission, and correcting the sampled ring oscillator state through logical judgment.

The present application relates to a kind of folding wing deployment time test method, belong to product detection field, solve the low precision of the wing piece deployment time test of folding wing in prior art.The present application is tested using folding wing deployment time test device, the test method includes the following steps: step S1: the folding wing to be detected is fixed to folding wing fixed component and is fixed, and the wing piece is locked and positioned by wing piece bundle group component;Step S2: unlock folding wing;The wing piece of folding wing is unfolded, and the release time of wing piece is monitored by release photoelectric sensor;Step S3: when folding wing unfolds, the in-place time of each wing piece is monitored by in-place photoelectric sensor.The present application realizes the release time and in-place time of wing piece are monitored, and the unfolding time and unfolding consistency of wing piece are detected.

The utility model discloses a self-calibration timing circuit, a timing device and an ignition device, and relates to the field of timing, the self-calibration timing circuit comprises a calibration circuit, an output end is connected with a clock end of a calibrated circuit, and the calibration circuit is used for outputting a clock signal to the calibrated circuit; the output end of the calibrated circuit is connected with the input end of the ignition device, and the calibrated circuit is used for timing based on the clock signal; and the ignition device is used for outputting detonation when the ignition signal is received through the input end of the ignition device at the end of timing. The calibration circuit and the calibrated circuit are separately arranged, the calibration circuit does not participate in actual control, the high overload circuit is prevented from influencing the timing accuracy, the calibration circuit outputs the time to the calibrated circuit, the ignition device is further controlled, and the timing can be more accurate.

A system and method for estimating vehicle battery charging time using big data are provided. The system may include: a big data server configured to collect charging-related parameters of batteries in multiple vehicles to group the vehicles into groups based on the collected charging-related parameters, and to calculate and send a first estimated charging time for the group to which a vehicle belongs during vehicle charging; and a controller installed in each of the multiple vehicles and configured to calculate a second estimated charging time based on the state of the battery in the vehicle when the corresponding battery in the vehicle is being charged, and to calculate a final estimated charging time for the battery by combining the first and second estimated charging times.