30 results about "Electronic hardware" patented technology

The invention relates to a satellite-borne electronic hardware design guarantee method and system. The method comprises the following steps: determining a satellite-borne hardware guarantee level (SHL) of satellite-borne electronic hardware; integrating a fault mode injection FM I into a design process of satellite-borne electronic hardware, and adjusting the execution depth of the FM I based on the SHL level; and providing a process cutting engine, and realizing adaptive process cutting based on a DO-254 standard according to the SHL level and in combination with the execution depth of the FM I. The system comprises an SHL evaluation module; an FM I management module; a space environment effect knowledge base; and a process cutting engine. According to the method, the problem that the DO-254 standard is insufficient in adaptability in the aerospace field is solved, the reliability design and verification efficiency of satellite-borne electronic hardware is remarkably improved, and the method is suitable for aerospace tasks such as various satellites and deep space probes.

The invention belongs to the field of aerospace electronic measurement, and provides an inductance type proximity sensor resolving method and system based on an improved DFT algorithm, and the method comprises the steps: applying a sine excitation signal of an excitation frequency; synchronously acquiring a sine excitation signal and a sensor response signal of the output end of the proximity sensor; an improved DFT algorithm is adopted, the amplitude and the phase under the excitation frequency are extracted, and the voltage vector relation among the excitation voltage, the output voltage of the sensor and the complex impedance of the sensor is constructed; the inductance value and the parasitic resistance value of the proximity sensor are calculated through triangular transformation and calibrated, and the calibrated inductance value is obtained. According to the method, the reliability is high, complex electronic hardware is not needed, the development cost is low, the inductance value of the sensor is obtained on a DSP28335 platform based on the improved DFT algorithm, the precision reaches 0.15 mH, and the consumed time of single-path calculation does not exceed 2 ms. The expansion is easy, and the newly increased time is not more than 1ms when one path of sensor is newly increased.

The invention belongs to the field of aerospace electronic measurement, and provides an inductance type proximity sensor resolving method and system based on a time domain integration algorithm, and the method comprises the steps: applying a generated sine excitation voltage to a measurement loop; synchronously acquiring sine excitation voltage and response voltage of an inductive proximity sensor in a measurement loop; based on a time domain integration algorithm, respectively carrying out orthogonal integration on the sine excitation voltage and the response voltage, and calculating respective amplitudes and phases; according to the amplitude, the phase and the resistance value of the reference resistor, an inductance value and a parasitic resistance value of the inductive proximity sensor are calculated through a trigonometric function relationship; and establishing a piecewise linear fitting model through a least square method, and calibrating the inductance value to obtain a calibrated inductance value. The method has the advantages of high reliability, strong anti-noise capability, no need of complex electronic hardware, and reduction of the development cost at a lower development guarantee level.

Provided is an electronic hardware sub-system within a multi-tenant Hardware Security Module (HSM) for tamper response against physical and logical attacks against the HSM. An HSM Manager manages and orchestrates the vHSMs for dynamic fraud analysis by way of a Tamper Prevention System, wherein a Watchdog detects intrusions and declares Tamper Events, and a Tamper Enforcement Module signals HSM Actors about a tamper state action responsive to said Tamper Event and intrusions. Once enabled, it protects multi-tenant applications against cryptographic attacks and offers continuous fraud detection in a layered approach that intelligently detects a root cause of an attack and isolated an impacted area in a tenant partition. Other embodiments disclosed.

The invention provides a dual-binary turbo code processing method and electronic hardware. The method comprises the following steps: acquiring processing data; determining a processing module according to the length of the processing data; wherein the processing module uniquely corresponds to one storage unit; and performing multi-round parallel processing on the processing data based on the DVB-RCS2 standard through the determined processing module. According to the method, a processing module is determined according to the length of processing data; wherein the processing module uniquely corresponds to one storage unit; through the determined processing module, multi-round parallel processing is performed on the processing data based on the DVB-RCS2 standard, parallel processing of the processing data is realized, the processing time is reduced, and the processing efficiency is improved.

The invention provides a turbo code processing method and electronic hardware. The method comprises the following steps: acquiring processing data; partitioning the processed data into blocks; wherein the blocks correspond to different storage units; performing multi-path processing on each block based on each storage unit; wherein the processing is interleaving or de-interleaving. According to the method provided by the invention, the parallel processing of the processing data is realized by partitioning the processing data and then performing multi-path processing on each block, so that the processing time is shortened, and the processing efficiency is improved.

The application discloses a complex electronic hardware compliance verification test system based on simulation vector multiplexing, and belongs to the technical field of electronic hardware testing.The simulation test vector generation module is configured to receive a hardware design requirement document, establish a requirement pin mapping table, encapsulate a simulation excitation vector with timing annotation, generate a test vector file, and design a high-fidelity verification module board card module, so that the board card module is kept consistent with a target product board card, the measured hardware circuit is connected, preset test points monitor signals of the measured hardware circuit, the core control module includes a timing reconstruction engine, the test vector file is read, an actual output vector file is generated, the actual output vector file is verified by an automatic verification closed loop module, a test report including a compliance evidence chain is generated, efficient simulation vector multiplexing can be realized, simulation and actual measurement timing behaviors are consistent and aligned, synchronous linkage of excitation application and response acquisition is realized, and verification efficiency and checking accuracy are improved.

This invention discloses an IoT-based electronic hardware system for agricultural environmental monitoring, aiming to solve problems such as low monitoring accuracy, weak anti-interference capability, and poor adaptability in different agricultural scenarios. The system adopts a core architecture of multispectral coupled sensing, layered anti-interference packaging, dual-mode communication, and neural network self-calibration, making it adaptable to various scenarios such as desert oases, tea gardens, and northern arid lands. By optimizing the sensing unit, strengthening the protective structure, and implementing adaptive power supply and real-time calibration algorithms, it achieves accurate monitoring of multiple dimensions, including temperature and humidity, soil / water quality parameters, and crop status. Its simple structure, convenient installation, strong resistance to interference from wind, sand, freeze-thaw cycles, and high humidity, and stable data transmission provide reliable data support for precise agricultural production management, adapting to various agricultural environmental monitoring needs.

Provided is an electronic hardware sub-system within a multi-tenant Hardware Security Module (HSM) (10) for tamper response against physical and logical attacks against the HSM. An HSM Manager (60) manages and orchestrates the vHSMs (61 / 62) for dynamic fraud analysis by way of a Tamper Prevention System (70), wherein a Watchdog (71) detects intrusions and declaes Tamper Events (300), and a Tamper Enforcement Module (72) signals HSM Actors about a tamper state action responsive to said Tamper Event and intrusions. Once enabled, it protects multi-tenant applications against cryptographic attacks and offers continuous fraud detection in a layered approach that intelligently detects a root cause of an attack and isolated an impacted area in a tenant partition. Other embodiments disclosed.

The invention provides a self-adaptive negative pressure cavity structure and method for chip heat dissipation, and relates to the field of electronic hardware, the self-adaptive negative pressure cavity structure comprises a circuit board, and the lower surface of the circuit board is electrically connected with a chip; the heat dissipation substrate is arranged below the chip, and the heat dissipation substrate is fixedly connected with the circuit board; a heat dissipation conductor is arranged between the heat dissipation substrate and the chip, the heat dissipation conductor is in surface contact with the chip, and the heat dissipation substrate and the heat dissipation conductor are correspondingly provided with a first cavity and a second cavity respectively; the first cavity and the second cavity are in a negative pressure environment and are used for containing a cooling medium, the first cavity and the second cavity are communicated to form a circulating flow channel allowing the cooling medium to flow between the first cavity and the second cavity, and capillary structures are arranged in the first cavity, the second cavity and the circulating flow channel; the chip is efficiently cooled between the first cavity and the second cavity through flowing and phase change of the cooling medium, the heat dissipation mode is optimized under the condition that the size of the heat dissipation structure of the chip is not changed, and the heat dissipation effect is improved.

The invention provides a design method for reducing the whole life cycle cost of electronic hardware equipment, which relates to the field of electronic equipment management and comprises the following steps: S1, importing a component list of an initial design scheme; s2, determining an alternative replacement component for each component in the list, and forming a component alternative replacement mapping table; s3, constructing an alternative design scheme set based on the mapping table; s4, reliability evaluation is carried out on each alternative design scheme in the scheme set, and the severity level fault rate and the total product fault rate of each scheme are obtained; s5, calculating the whole life cycle cost of each scheme based on a reliability evaluation result; and S6, comparing the whole life cycle cost of all the alternative design schemes, and selecting the scheme with the optimal cost as the final design scheme. According to the method, the product life cycle cost formed by the manufacturing cost, the maintenance cost and the fault influence cost is reduced in the design stage of the electronic equipment, and comprehensive optimization of the economical efficiency and the reliability of the electronic equipment is achieved.

The utility model discloses an electronic hardware detection device, which comprises a conveying assembly, a mounting frame, a detection assembly, a first driving assembly and a second driving assembly, and is characterized in that the conveying assembly is suitable for bearing and conveying electronic hardware; the mounting frame is arranged on one side of the conveying assembly; the detection assembly is arranged above the conveying assembly so as to be suitable for detecting the electronic hardware conveyed by the conveying assembly; the first driving assembly comprises a limiting piece, a first transmission component and a second transmission component, and the first transmission component is suitable for rotating relative to the mounting frame and driving the detection assembly to do reciprocating rectilinear motion in the first direction; the second driving assembly is connected with the conveying assembly to drive the conveying assembly to operate intermittently. The electronic hardware detection device can be suitable for electronic hardware of different sizes, accurate positioning relative to the electronic hardware can be achieved, the detection precision is high, and errors are small.

This disclosure relates to adaptive thermal control for data centers and IT equipment. A data center thermal control system includes: a local cooler configured to cool a local coolant used for cooling electronic hardware; an external heat exchanger configured to exchange heat from a fluid to outside air; and a fluid circulation system configured to transfer heat from the local cooler to the external heat exchanger by circulating at least one fluid cooling medium, the fluid circulation system including a cold section pointing towards the air cooler. The thermal control system also includes one or more processors and a non-transitory computer-readable medium storing instructions that, when executed by the one or more processors, cause the one or more processors to control the external heat exchanger to cool the fluid in the cold section to a first target temperature during hot seasons and to cool the fluid in the cold section to a lower target temperature during cold seasons.

A method, system, apparatus, and architecture are provided for managing faults in a data processing system having multiple data processing subsystems, including a resource reallocation management subsystem which responds to a notification of a faulty resource by isolating the faulty resource and requesting an over-the-air (OTA) update from an external system controller to provide update code which is received and stored at a flash memory, and then used to reconfigure a spare resource subsystem which is connected to the data processing system by reprogramming the interconnect manager at the interconnect bus.

The application relates to the technical field of automobile electronic hardware-in-the-loop test, in particular to a wheel speed sensor hardware-in-the-loop simulation system and method, which comprises a wheel speed simulator, an actual vehicle wheel speed sensor, an actual vehicle gear ring and an upper computer, the wheel speed simulator comprises a motor, a motor controller, a gear ring fixing mechanism, a wheel speed sensor adjusting mechanism and an ABS / ESC controller; the application calculates target wheel speeds of each wheel through a vehicle dynamics model of the upper computer, drives the motor to coaxially rotate the actual vehicle gear ring, collects wheel speed signals through the actual vehicle wheel speed sensor and sends the wheel speed signals into the ABS / ESC controller, and then feeds back to the upper computer through a CAN network to form a closed-loop simulation, the core algorithm comprises four parts of signal generation, signal processing, mode switching and test verification; the application can discover and solve potential problems in the early development stage, improves test repeatability, effectively shortens the development cycle, reduces the research and development cost, and avoids the risk of hardware modification and product recall in the later stage.

Modular sensor and system platform for measurements, cleaning and calibration in analytical, gas temperature, pressure measurement, flow measurement and level measurement technology. - with integrated Ethernet technology Advanced Physical Layer (APL) and Single Pair Ethernet (SPE) as well as a modular electronics hardware and electronics software platform for measurement parameters, cleaning / calibration systems and service systems in liquid and / or gas analysis and / or temperature and / or pressure measurement technology and / or flow measurement technology and / or level measurement technology. - with integrated fieldbus Ethernet technology APL and / or SPE, PROFINET etherCAT, Ethernet TCP / IP, Ethernet UDP / IP and other similar and / or adapted fieldbus protocols, e.g. I / O-Link, USB, for potentially explosive (IECEX, ATEX, FM) and / or non-hazardous (non-EX) environments, - with direct connection option to programmable logic controllers (PLCs) and / or input / output units (I / Os or remote I / Os) of established system manufacturers, via fixed cable connection, implemented as a 2-wire and / or multi-wire connection, copper and / or fiber optic connection, and / or wireless connection, WLAN and / or Bluetooth as well as WirelessHART. - with direct connection option to PCs for explosion-hazardous and non-explosion-hazardous environments via USB and / or via interface or , USB modem for sensor-side Ethernet APL and / or SPE and / or PROFINET and other sensor-side fieldbuses, e.g. I / O-Link, PROFIBUS DP / PA or or FF, or HART-IP, or HART 4mA and specially adapted fieldbuses (where the modem can be used for explosion-hazardous and / or non-explosion-hazardous environments). - operable with standardized user interfaces, such as PACTware-FDT / DTM, and / or common field communicators, e.g. Emerson 475 Field Communicator for FF and HART or other systems from established manufacturers, or apps or application software for mobile operating systems, such as iPhone and / or PC, laptop with different operating systems (e.g. Apple, Windows and the like) and / or Visual Basic with Visual Basic XML Generator (which generates Simple Visual Basic Code to Read & Write XML Data and uses libraries for C++, Oracle Java, VB .Net, Silverlight, VB6).

The invention belongs to the technical field of wearable electronic equipment, and particularly relates to an OWS earphone and electronic equipment comprising the OWS earphone. The OWS earphone comprises a power supply unit, a main body unit and an elastic arm, and the main body unit is provided with a protruding sound production unit. The elastic arm is connected between the power supply unit and the main body unit; in the wearing state, the elastic arm and the auricle are attached in a self-adaptive mode so that the sound production unit of the main body unit can stretch into the auricular conchae cavity and cooperate with the auricular conchae cavity to form a semi-enclosed acoustic cavity communicated with the ear canal. The OWS earphone is fused with ergonomics, under the condition of not depending on complex electronic hardware compensation, balance among tone quality, comfort and stability is successfully achieved, wearing comfort and environment permeability are effectively kept, and meanwhile sound plumpness and low-frequency performance of the OWS earphone are remarkably enhanced.

The present disclosure relates to a method for verifying and recording an infusion treatment procedure (S100), having the following steps: receiving a drug prescription, preferably from an IT system (8); converting the medicine prescription into an operation instruction; performing a first verification of the drug and / or formulation by means of the scanner unit (1); second verification of at least a portion of the infusion pump by means of the scanner unit (1); performing a third verification on the patient by means of the scanner unit (1); monitoring infusion supply and fourth verification of infusion; and recording the infusion treatment by transmitting all verification and monitoring data to the IT system (8). Furthermore, the present disclosure relates to an electronic hardware assembly (5) for verifying and recording infusion treatment procedures, having a user interface (6), a preferably wireless data connection (7) to at least one IT system (8), a scanner unit (1) for reading data, software or a controller (10) and an integrated or separate sensor (2).

The invention relates generally to cryptography in secure microchips using a password authentication scheme. More specifically, the invention is directed to a uniquely configured electronic hardware component and method of usage for providing secure password initialization and branch-free password authentication. The electronic hardware component together with a method of usage results in a system that, upon correctly entering a possibly low-entropy secret, such as a password, outputs a high-entropy cryptographic key while allowing only a limited number of attempts to enter the correct password. The invention effectively enforces the limit on the number of password attempts without employing a numeric counter, thus eliminating the use of conditional branching operations and making it suitable for use in secure tamper-resistant integrated circuits.

The invention relates to an electronic hardware implantation fixing structure for intelligent wearable equipment, which comprises an intelligent bracelet rear shell, a mounting clamping position is arranged on the intelligent bracelet rear shell, a plastic pad is fixedly mounted in the mounting clamping position, and a bayonet for mounting a display screen is formed in one side, far away from the plastic pad, of the intelligent bracelet rear shell; two ECG sensors are arranged on the side face, away from the bayonet, of the intelligent bracelet rear shell, two fixing mechanisms used for positioning the ECG sensors are arranged on the side face, away from the bayonet, of the plastic pad, and the two fixing mechanisms are symmetrically arranged; the two ECG sensors are sequentially attached to the corresponding positions of the plastic pad, in the slow attaching process, the first inverted buckle piece is inserted into the first limiting groove, the second inverted buckle piece is inserted into the second limiting groove, and the stability of the ECG sensors installed on the plastic pad is improved through cooperation of the first inverted buckle piece and the second inverted buckle piece; and the ECG sensor is prevented from falling off due to tension or pulling force generated by frequent contact between the ECG sensor and the arm of a user.

Provided is an electronic hardware sub-system within a multi-tenant Hardware Security Module (HSM) for tamper response against physical and logical attacks against the HSM. An HSM Manager manages and orchestrates the vHSMs for dynamic fraud analysis by way of a Tamper Prevention System, wherein a Watchdog detects intrusions and declares Tamper Events, and a Tamper Enforcement Module signals HSM Actors about a tamper state action responsive to said Tamper Event and intrusions. Once enabled, it protects multi-tenant applications against cryptographic attacks and offers continuous fraud detection in a layered approach that intelligently detects a root cause of an attack and isolated an impacted area in a tenant partition. Other embodiments disclosed.

A data center thermal control system includes a local cooler configured to cool a local coolant used for cooling electronic hardware, an outer heat exchanger configured to exchange heat from fluid to outside air, and a fluid circulation system configured to convey heat from the local cooler to the outer heat exchanger by circulating at least one fluid cooling medium, the fluid circulation system including a cold portion directed to the air cooler. The thermal control system also includes one or more processors and a non-transitory computer-readable medium storing instructions that, when executed by the one or more processors, would cause the one or more processors to govern the outer heat exchanger to cool fluid in the cold portion to a first target temperature during a hot season, and cool fluid in the cold portion to a lower target temperature during a cold season.

The invention relates generally to cryptography in secure microchips using a password authentication scheme. More specifically, the invention is directed to a uniquely configured electronic hardware component and method of usage for providing secure password initialization and branch-free password authentication. The electronic hardware component together with a method of usage results in a system that, upon correctly entering a possibly low-entropy secret, such as a password, outputs a high-entropy cryptographic key while allowing only a limited number of attempts to enter the correct password. The invention effectively enforces the limit on the number of password attempts without employing a numeric counter, thus eliminating the use of conditional branching operations and making it suitable for use in secure tamper-resistant integrated circuits.

The invention belongs to the technical field of infrared image transmission performance testing, and particularly relates to an infrared image transmission delay testing method and system based on pendulum timing, and the method comprises the following specific steps: S1, simulating a typical severe scene of infrared transmission, and maintaining the stability of scene parameters in combination with environment monitoring and closed-loop feedback, it is ensured that the whole test process is performed in a target application scene; and S2, constructing a dynamic scene which swings periodically and stably through the pendulum body, the pendulum length adjusting mechanism, the angle identification assembly and the infrared reflective marker, and providing recognizable and quantifiable time correlation reference for the infrared image in combination with the angle identification and the infrared reflective marker. By adopting a pendulum mechanical periodic timing structure, the problems that software timing is influenced by CPU resource allocation and electronic hardware timing has synchronous deviation can be avoided, the advantage of realizing a stable and reliable timing reference is achieved, and the accuracy of basic data of delay calculation is ensured.

This invention discloses and provides a compact electronic hardware testing device, enabling universal testing of different project boards and devices, significantly reducing the design workload and error probability of dedicated test boards, and shortening debugging time. The invention includes at least one functional box and a power control box, wherein the power control box provides power to the functional box. The functional box is used for electronic hardware testing. The functional box includes a housing and an integrated module disposed within the housing. The integrated module includes an FPGA control module, a power integrated circuit, an audio output measurement circuit, a channel switching circuit, a ripple measurement circuit, a GPIO control circuit, and an AC / DC voltage measurement circuit. This invention applies to the technical field of electronic hardware testing.

The invention provides a function stack maintenance method, a function stack access method and electronic hardware, and the method comprises the steps: in a function preorder, when a stack space allocation statement is executed, allocating a hot stack space; wherein the hot stack space is located in a hot stack storage area in the CPU; in function subsequent, when a stack space release statement is executed, the allocated hot stack space is released. According to the method provided by the invention, the random access speed of the hot data is improved through the hot stack storage area in the CPU.

A computer system traces an original electronic design automation (EDA) implementation process for electronic hardware designs. The original EDA implementation process includes multiple subprocesses to convert a hardware model to a physically-realized electronic circuit. The system inputs a cryptographic key and design information that includes the hardware model, constraints, properties, implementation settings, and other directives for directing the conversion. The cryptographic key and design information are processed to generate a sequence of instructions to execute and provide traceability of each subprocess. For each subprocess, the system gathers intermediate design state and implementation settings resulting from or influencing execution of the subprocess; combines the intermediate design state and implementation settings into a data string and determines a cryptographic hash value for the data string; digitally signs the cryptographic hash value using a digital signature certificate derived from the cryptographic key to generate a signed hash; stores the signed hash and identifiers associated with data files used for determining the cryptographic hash value to an electronic ledger to generate an updated electronic ledger; authenticates the signed hash from the electronic ledger to generate an authenticated signed hash; reconstructs a hash from the data files stored in the electronic ledger to generate a reconstructed hash; compares the authenticated signed hash with the reconstructed hash, and in response to a mismatch, generates an error signal. The steps are repeated for each subsequent subprocess, and the traced EDA implementation process results are stored in memory.

The invention provides a programmable logic device configuration method and a hardware board card, and relates to the technical field of electronic hardware design and logic control. The method is applied to a hardware board card comprising a CPLD and comprises the steps that when the CPLD is powered on and started, configuration information is read from a user flash memory in the CPLD, and the configuration information at least comprises a hardware version identifier and a function configuration identifier; analyzing the read configuration information, and dynamically selecting and starting a specific logic function module matched with the hardware board card from the same set of logic codes solidified in the CPLD based on the hardware version identifier and the function configuration identifier obtained through analysis, therefore, on the hardware logic control level, traditional normal form conversion of'multiple sets of codes and multiple BOMs' is replaced with'one set of codes and multiple configurations', repeated logic code development and testing for hardware board cards with similar functions are effectively reduced, and then related manpower and time cost is remarkably reduced.

The invention provides a BRAM single event upset relieving method for an FPGA, belongs to the technical field of complex electronic hardware airworthiness, and particularly relates to a BRAM data content encoding method adopting a specific encoding mode during BRAM data writing. When data of the BRAM are read out, error data correction is achieved through a supervision vector and a data error vector related to a calculation and coding mode, so that the single event upset phenomenon of the BRAM can be detected, BRAM resources are saved compared with a triple modular redundancy mitigation measure, additional hardware circuits are saved compared with a refreshing method, and the cost is reduced. Compared with the similar common Hamming ECC coding mode, the FPGA logic levels realized by the method are fewer, the mitigation measure realized by the method supports fault injection and white-box testing, and the security of the FPGA is effectively enhanced in the civil aviation FPGA development process.

The invention provides a loop operation optimization method and electronic hardware, and the method comprises the steps: reading a structural body of loop cost information when a write-in operation of a loop cost control state register is captured; wherein the pointer of the structural body of the cycle cost information is stored in the cycle cost control state register; the structural body of the loop cost information is dynamically updated before the loop body is executed each time; according to the structural body of the cycle cost information, evaluating the cost of the cycle of the cycle body; and optimizing the current cycle of the cycle body according to the cost of the current cycle. According to the method provided by the invention, the cost of the current cycle of the loop body is evaluated through the structural body of the loop cost information dynamically updated before the loop body is executed each time, and then the current cycle of the loop body is optimized according to the cost of the current cycle, so that optimization of loop operation is realized.