58 results about "Electronic hardware" patented technology

An electronic hardware wallet for conducting cryptocurrency transactions, blockchain transactions, or other secure communications is embodied on a monolithic integrated circuit (IC) die supported on a single substrate. The monolithic semiconductor device can include a non-volatile data store for storing application software executable by the multi-core processor, and the secure element can include a secure data store for storing secret data (e.g., a private key) for use in a secure electronic transaction. In some embodiments, the secure element can include hardware logic embodying a cryptocurrency algorithm associated with executing the secure electronic transaction and can have a limited and selective communication bus between the secure element and the multi-core processor. The electronic hardware wallet can communicatively couple with one or more other devices to facilitate a multi-party computation (MPC) algorithm for authenticating the cryptocurrency algorithm and validating the secure electronic transaction.

The present disclosure relates to systems and methods for determining comprehensive and asset vulnerability ratings using models such as artificial intelligence (AI) and machine learning (ML) models. These models can identify relevant attributes, optimize attribute values, and determine logical relationships between attributes. The term “model” encompasses various types of AI and ML models, including neural networks, language models, multimodal models, and others. Models can be trained using supervised learning with labeled data to predict or classify new data items. The models can be locally hosted, cloud-managed, or accessed via APIs, and can be implemented in electronic hardware such as computer processors.

Various embodiments relate generally to autonomous vehicles and associated mechanical, electrical and electronic hardware, computer software and systems, and wired and wireless network communications to provide an autonomous vehicle fleet as a service. In particular, a method may include receiving first sensor data from a first sensor disposed on a vehicle, the first sensor data associated with a first sensor modality, and receiving second sensor data from a second sensor disposed on the vehicle, the second sensor data associated with a second sensor modality different than the first sensor modality. The method may further include generating fused sensor data representing at least a portion of the first sensor data and the second sensor data, generating a trajectory for the vehicle based in part on the fused sensor data, and controlling the vehicle based in part on the trajectory.

A liquid cooling apparatus and system for the immersion cooling of electronic devices including in particular servers and other IT hardware nodes having an array of heat generating devices including microprocessors, RAM, motherboards etc having different operational temperatures. The present apparatus and system is adapted for at least an in-series flow of cooling liquid in direct contact with the different heat generating devices so as to provide multi-stage heat transfer phases for enhanced energy efficiency and operational control and performance of the electronic device.

The invention discloses hardware detection equipment for electronic information engineering, and relates to the technical field of electronic hardware detection. The device comprises a detection table, a fixing mechanism is arranged above the detection table, the fixing mechanism comprises a clamping plate slidably connected to the upper portion of the detection table, the lower portion of the clamping plate is in threaded connection with a bidirectional threaded rod, the bidirectional threaded rod is fixedly provided with a first transmission wheel, and the first transmission wheel is in transmission connection with a second transmission wheel through a transmission belt; the second transmission wheel is fixedly installed on a threaded cylinder, the threaded cylinder is in threaded connection with an air rod, the air rod is fixedly provided with a piston, and the piston is slidably connected into the air cylinder. Through rotation of the bidirectional threaded rod, displacement of the clamping plate is controlled, the threaded cylinder is driven to rotate through the transmission wheel and the transmission belt, rotary motion is converted into linear motion of the air rod, the piston is pushed to reciprocate in the air cylinder to generate air flow, the air flow is sprayed out of the air spraying pipe through the splitter plate, and linkage of clamping and cleaning is achieved; dust or chippings on the surface of the electronic hardware are effectively removed, and the detection precision is ensured.

The invention relates to a satellite-borne electronic hardware design guarantee method and system. The method comprises the following steps: determining a satellite-borne hardware guarantee level (SHL) of satellite-borne electronic hardware; integrating a fault mode injection FM I into a design process of satellite-borne electronic hardware, and adjusting the execution depth of the FM I based on the SHL level; and providing a process cutting engine, and realizing adaptive process cutting based on a DO-254 standard according to the SHL level and in combination with the execution depth of the FM I. The system comprises an SHL evaluation module; an FM I management module; a space environment effect knowledge base; and a process cutting engine. According to the method, the problem that the DO-254 standard is insufficient in adaptability in the aerospace field is solved, the reliability design and verification efficiency of satellite-borne electronic hardware is remarkably improved, and the method is suitable for aerospace tasks such as various satellites and deep space probes.

The present invention relates to a current output module (1) which is used in 5 SLSC (Switch Load and Signal Conditioning) systems and in electronic hardware testing, particularly in HIL (Hardware-in-the-loop) testing, and which is connected to test equipment and / or products being tested and enables comprehensive testing and measurements.

The invention belongs to the field of aerospace electronic measurement, and provides an inductance type proximity sensor resolving method and system based on an improved DFT algorithm, and the method comprises the steps: applying a sine excitation signal of an excitation frequency; synchronously acquiring a sine excitation signal and a sensor response signal of the output end of the proximity sensor; an improved DFT algorithm is adopted, the amplitude and the phase under the excitation frequency are extracted, and the voltage vector relation among the excitation voltage, the output voltage of the sensor and the complex impedance of the sensor is constructed; the inductance value and the parasitic resistance value of the proximity sensor are calculated through triangular transformation and calibrated, and the calibrated inductance value is obtained. According to the method, the reliability is high, complex electronic hardware is not needed, the development cost is low, the inductance value of the sensor is obtained on a DSP28335 platform based on the improved DFT algorithm, the precision reaches 0.15 mH, and the consumed time of single-path calculation does not exceed 2 ms. The expansion is easy, and the newly increased time is not more than 1ms when one path of sensor is newly increased.

The invention belongs to the field of aerospace electronic measurement, and provides an inductance type proximity sensor resolving method and system based on a time domain integration algorithm, and the method comprises the steps: applying a generated sine excitation voltage to a measurement loop; synchronously acquiring sine excitation voltage and response voltage of an inductive proximity sensor in a measurement loop; based on a time domain integration algorithm, respectively carrying out orthogonal integration on the sine excitation voltage and the response voltage, and calculating respective amplitudes and phases; according to the amplitude, the phase and the resistance value of the reference resistor, an inductance value and a parasitic resistance value of the inductive proximity sensor are calculated through a trigonometric function relationship; and establishing a piecewise linear fitting model through a least square method, and calibrating the inductance value to obtain a calibrated inductance value. The method has the advantages of high reliability, strong anti-noise capability, no need of complex electronic hardware, and reduction of the development cost at a lower development guarantee level.

The invention relates to the technical field of electronic hardware detection, and discloses a hardware detection device for electronic information engineering, which comprises a box body, a transmission mechanism and a positioning mechanism, and further comprises a detection mechanism fixedly mounted on the top wall of the box body, and an intermittent blanking mechanism fixedly mounted on one side of the transmission mechanism, the conveying mechanism is in transmission connection with the intermittent discharging mechanism and the positioning mechanism. According to the technical scheme, through cooperative work of the conveying mechanism, the intermittent discharging mechanism and the positioning mechanism, the full-automatic process of intermittent conveying, precise positioning and one-by-one release of the circuit boards is achieved; the intermittent discharging mechanism and the positioning mechanism are synchronously driven by the transmission mechanism, the circuit boards are intermittently conveyed to the positioning mechanism, the positioning mechanism stops acting after receiving each circuit board, it is ensured that the circuit boards are accurately positioned to the position below the detection mechanism, the circuit boards are in a fixed state in the detection process, and the detection efficiency is improved. And accurate detection of the detection mechanism can be ensured.

The present invention discloses a magnetic small module system based on a three-axis fluxgate sensor, belonging to the field of magnetic induction detection. It includes a mounting plate. Four corners of the upper end of the mounting plate are respectively fixedly installed with three copper studs, and the four groups of the three copper studs are symmetric about the center axis of the mounting plate in pairs. A substrate is fixedly connected above the mounting plate through the three copper studs, and a connector is fixedly connected to the front end of the mounting plate. The present invention can realize the acquisition, internal storage and data reading of magnetic signals. An attitude sensor is added to detect the dynamic situation of the device. At the same time, the electronic hardware design meets the usage requirements and technical indicators, the structural design meets the technical indicator requirements, the power consumption is properly controlled, the continuous working time is long, and it has high practical value.

An electronic hardware wallet for conducting cryptocurrency transactions, blockchain transactions, or other secure communications is embodied on a monolithic integrated circuit (IC) die supported on a single substrate. The monolithic semiconductor device can include a non-volatile data store for storing application software executable by the multi-core processor, and the secure element can include a secure data store for storing secret data (e.g., a private key) for use in a secure electronic transaction. In some embodiments, the secure element can include hardware logic embodying a cryptocurrency algorithm associated with executing the secure electronic transaction and can have a limited and selective communication bus between the secure element and the multi-core processor. The electronic hardware wallet can communicatively couple with one or more other devices to facilitate a multi-party computation (MPC) algorithm for authenticating the cryptocurrency algorithm and validating the secure electronic transaction.

Disclosed herein are various embodiments relate generally to computer vision, graphics, image scanning, and image processing as well as associated mechanical, electrical and electronic hardware, computer software and systems, and wired and wireless network communications to form at least three-dimensional models or images of objects and environments and to identify, characterize, or differentiate material or tissues in objects and environments.

Provided is an electronic hardware sub-system within a multi-tenant Hardware Security Module (HSM) for tamper response against physical and logical attacks against the HSM. An HSM Manager manages and orchestrates the vHSMs for dynamic fraud analysis by way of a Tamper Prevention System, wherein a Watchdog detects intrusions and declares Tamper Events, and a Tamper Enforcement Module signals HSM Actors about a tamper state action responsive to said Tamper Event and intrusions. Once enabled, it protects multi-tenant applications against cryptographic attacks and offers continuous fraud detection in a layered approach that intelligently detects a root cause of an attack and isolated an impacted area in a tenant partition. Other embodiments disclosed.

The present disclosure relates to systems and methods for determining comprehensive and asset vulnerability ratings using models such as artificial intelligence (AI) and machine learning (ML) models. These models can identify relevant attributes, optimize attribute values, and determine logical relationships between attributes. The term "model" encompasses various types of AI and ML models, including neural networks, language models, multimodal models, and others. Models can be trained using supervised learning with labeled data to predict or classify new data items. The models can be locally hosted, cloud-managed, or accessed via APIs, and can be implemented in electronic hardware such as computer processors.

The invention provides a dual-binary turbo code processing method and electronic hardware. The method comprises the following steps: acquiring processing data; determining a processing module according to the length of the processing data; wherein the processing module uniquely corresponds to one storage unit; and performing multi-round parallel processing on the processing data based on the DVB-RCS2 standard through the determined processing module. According to the method, a processing module is determined according to the length of processing data; wherein the processing module uniquely corresponds to one storage unit; through the determined processing module, multi-round parallel processing is performed on the processing data based on the DVB-RCS2 standard, parallel processing of the processing data is realized, the processing time is reduced, and the processing efficiency is improved.

The present application relates to generating one or more brightness edges to form a three-dimensional model of an object. Various embodiments disclosed herein generally relate to computer vision, graphics, image scanning and image processing and associated mechanical, electrical and electronic hardware, computer software and systems, and wired and wireless network communications to form at least a three-dimensional model or image of an object and an environment.

The invention provides a turbo code processing method and electronic hardware. The method comprises the following steps: acquiring processing data; partitioning the processed data into blocks; wherein the blocks correspond to different storage units; performing multi-path processing on each block based on each storage unit; wherein the processing is interleaving or de-interleaving. According to the method provided by the invention, the parallel processing of the processing data is realized by partitioning the processing data and then performing multi-path processing on each block, so that the processing time is shortened, and the processing efficiency is improved.

An electronic hardware wallet for conducting cryptocurrency transactions, blockchain transactions, or other secure communications is embodied on a monolithic integrated circuit (IC) die supported on a single substrate. The monolithic semiconductor device can include a non-volatile data store for storing application software executable by the multi-core processor, and the secure element can include a secure data store for storing secret data (e.g., a private key) for use in a secure electronic transaction. In some embodiments, the secure element can include hardware logic embodying a cryptocurrency algorithm associated with executing the secure electronic transaction and can have a limited and selective communication bus between the secure element and the multi-core processor. The electronic hardware wallet can communicatively couple with one or more other devices to facilitate a multi-party computation (MPC) algorithm for authenticating the cryptocurrency algorithm and validating the secure electronic transaction.

The application discloses a complex electronic hardware compliance verification test system based on simulation vector multiplexing, and belongs to the technical field of electronic hardware testing.The simulation test vector generation module is configured to receive a hardware design requirement document, establish a requirement pin mapping table, encapsulate a simulation excitation vector with timing annotation, generate a test vector file, and design a high-fidelity verification module board card module, so that the board card module is kept consistent with a target product board card, the measured hardware circuit is connected, preset test points monitor signals of the measured hardware circuit, the core control module includes a timing reconstruction engine, the test vector file is read, an actual output vector file is generated, the actual output vector file is verified by an automatic verification closed loop module, a test report including a compliance evidence chain is generated, efficient simulation vector multiplexing can be realized, simulation and actual measurement timing behaviors are consistent and aligned, synchronous linkage of excitation application and response acquisition is realized, and verification efficiency and checking accuracy are improved.

This invention discloses an IoT-based electronic hardware system for agricultural environmental monitoring, aiming to solve problems such as low monitoring accuracy, weak anti-interference capability, and poor adaptability in different agricultural scenarios. The system adopts a core architecture of multispectral coupled sensing, layered anti-interference packaging, dual-mode communication, and neural network self-calibration, making it adaptable to various scenarios such as desert oases, tea gardens, and northern arid lands. By optimizing the sensing unit, strengthening the protective structure, and implementing adaptive power supply and real-time calibration algorithms, it achieves accurate monitoring of multiple dimensions, including temperature and humidity, soil / water quality parameters, and crop status. Its simple structure, convenient installation, strong resistance to interference from wind, sand, freeze-thaw cycles, and high humidity, and stable data transmission provide reliable data support for precise agricultural production management, adapting to various agricultural environmental monitoring needs.

The utility model relates to the field of electronic hardware circuit design, and particularly discloses a strain signal acquisition circuit for a pipeline strain test, and the circuit comprises a power supply management module which is used for converting power supply voltage to VCC and taking the power supply voltage as a voltage source and a voltage reference of other modules; the bridge module is used for converting a resistance change signal generated by the strain gauge into a voltage signal; the signal conditioning module is used for amplifying the voltage signal output by the bridge module into a strain analog signal by using an operational amplifier; and the Bluetooth wireless transmission module is used for converting the strain analog signal into a digital signal and sending the digital signal to an upper computer so as to complete the acquisition of the pipeline strain signal. The device is compact in structure, complete in function, and suitable for a pipeline strain test environment requiring miniaturization and battery off-line power supply.

Provided is an electronic hardware sub-system within a multi-tenant Hardware Security Module (HSM) (10) for tamper response against physical and logical attacks against the HSM. An HSM Manager (60) manages and orchestrates the vHSMs (61 / 62) for dynamic fraud analysis by way of a Tamper Prevention System (70), wherein a Watchdog (71) detects intrusions and declaes Tamper Events (300), and a Tamper Enforcement Module (72) signals HSM Actors about a tamper state action responsive to said Tamper Event and intrusions. Once enabled, it protects multi-tenant applications against cryptographic attacks and offers continuous fraud detection in a layered approach that intelligently detects a root cause of an attack and isolated an impacted area in a tenant partition. Other embodiments disclosed.

The invention provides a self-adaptive negative pressure cavity structure and method for chip heat dissipation, and relates to the field of electronic hardware, the self-adaptive negative pressure cavity structure comprises a circuit board, and the lower surface of the circuit board is electrically connected with a chip; the heat dissipation substrate is arranged below the chip, and the heat dissipation substrate is fixedly connected with the circuit board; a heat dissipation conductor is arranged between the heat dissipation substrate and the chip, the heat dissipation conductor is in surface contact with the chip, and the heat dissipation substrate and the heat dissipation conductor are correspondingly provided with a first cavity and a second cavity respectively; the first cavity and the second cavity are in a negative pressure environment and are used for containing a cooling medium, the first cavity and the second cavity are communicated to form a circulating flow channel allowing the cooling medium to flow between the first cavity and the second cavity, and capillary structures are arranged in the first cavity, the second cavity and the circulating flow channel; the chip is efficiently cooled between the first cavity and the second cavity through flowing and phase change of the cooling medium, the heat dissipation mode is optimized under the condition that the size of the heat dissipation structure of the chip is not changed, and the heat dissipation effect is improved.

The invention provides a design method for reducing the whole life cycle cost of electronic hardware equipment, which relates to the field of electronic equipment management and comprises the following steps: S1, importing a component list of an initial design scheme; s2, determining an alternative replacement component for each component in the list, and forming a component alternative replacement mapping table; s3, constructing an alternative design scheme set based on the mapping table; s4, reliability evaluation is carried out on each alternative design scheme in the scheme set, and the severity level fault rate and the total product fault rate of each scheme are obtained; s5, calculating the whole life cycle cost of each scheme based on a reliability evaluation result; and S6, comparing the whole life cycle cost of all the alternative design schemes, and selecting the scheme with the optimal cost as the final design scheme. According to the method, the product life cycle cost formed by the manufacturing cost, the maintenance cost and the fault influence cost is reduced in the design stage of the electronic equipment, and comprehensive optimization of the economical efficiency and the reliability of the electronic equipment is achieved.

The utility model discloses an electronic hardware detection device, which comprises a conveying assembly, a mounting frame, a detection assembly, a first driving assembly and a second driving assembly, and is characterized in that the conveying assembly is suitable for bearing and conveying electronic hardware; the mounting frame is arranged on one side of the conveying assembly; the detection assembly is arranged above the conveying assembly so as to be suitable for detecting the electronic hardware conveyed by the conveying assembly; the first driving assembly comprises a limiting piece, a first transmission component and a second transmission component, and the first transmission component is suitable for rotating relative to the mounting frame and driving the detection assembly to do reciprocating rectilinear motion in the first direction; the second driving assembly is connected with the conveying assembly to drive the conveying assembly to operate intermittently. The electronic hardware detection device can be suitable for electronic hardware of different sizes, accurate positioning relative to the electronic hardware can be achieved, the detection precision is high, and errors are small.

This disclosure relates to adaptive thermal control for data centers and IT equipment. A data center thermal control system includes: a local cooler configured to cool a local coolant used for cooling electronic hardware; an external heat exchanger configured to exchange heat from a fluid to outside air; and a fluid circulation system configured to transfer heat from the local cooler to the external heat exchanger by circulating at least one fluid cooling medium, the fluid circulation system including a cold section pointing towards the air cooler. The thermal control system also includes one or more processors and a non-transitory computer-readable medium storing instructions that, when executed by the one or more processors, cause the one or more processors to control the external heat exchanger to cool the fluid in the cold section to a first target temperature during hot seasons and to cool the fluid in the cold section to a lower target temperature during cold seasons.

Embodiments of the present application provide a printed circuit board, a printed circuit board assembly and an electronic device, and relate to the technical field of electronic hardware. The printed circuit board comprises signal layers and reference layers arranged in sequence; a region in the reference layer corresponding to a main wiring area of the signal layer is hollowed out; in the extension direction of the connection line on the printed circuit board, the distance between the main wiring area and the chip and the IO connector on the printed circuit board is greater than a preset distance; and the projections of the connection lines in the main wiring area on the two signal layers clamped by the same reference layer do not overlap. The printed circuit board provided by the embodiments of the present application can reduce the insertion loss of the wiring per unit length and realize higher signal integrity.

According to the self-adaptive harmonic injection type arc extinguishing system and the arc extinguishing method provided by the invention, the system can accurately diagnose and generate the optimal suppression current waveform based on a self-adaptive control strategy extracted based on arc characteristics, so that the conversion from passive compensation to active accurate suppression is realized, and the arc extinguishing efficiency and the success rate are greatly improved. And secondly, the hybrid multi-level topology in which the cascaded H bridge and the neutral point clamped inverter are connected in series is adopted, so that a high-performance hardware platform is provided for the advanced control strategy, low-harmonic and high-quality output waveforms can be synthesized to meet the high-voltage and high-power requirements, and the system loss is also remarkably reduced. Finally, the intelligent control algorithm is deeply fused with advanced power electronic hardware, so that rapid, accurate and efficient arc suppression can be realized, and safe and stable operation of the power distribution network is powerfully guaranteed.

A method, system, apparatus, and architecture are provided for managing faults in a data processing system having multiple data processing subsystems, including a resource reallocation management subsystem which responds to a notification of a faulty resource by isolating the faulty resource and requesting an over-the-air (OTA) update from an external system controller to provide update code which is received and stored at a flash memory, and then used to reconfigure a spare resource subsystem which is connected to the data processing system by reprogramming the interconnect manager at the interconnect bus.