IP hard core intellectual property protection method and device based on path delay

A technology of intellectual property rights and path delay, applied in the protection of internal/peripheral computer components, etc., can solve the problem that the arbitrator is vulnerable to attacks, and achieve the effects of protecting interests, easy implementation, and small additional area

Inactive Publication Date: 2015-05-13
TIANJIN UNIV
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  • Abstract
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Due to differences in the process of integrated circuit technology, the input and output responses of the same PUF on different integrated circuit

Method used

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  • IP hard core intellectual property protection method and device based on path delay
  • IP hard core intellectual property protection method and device based on path delay
  • IP hard core intellectual property protection method and device based on path delay

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Embodiment Construction

[0027] The invention provides a method for implementing intellectual property protection of hardware circuits by applying delay matching of two sequential logic paths. In the described method, the signal path delay is used as a reference, and the designed protection circuit needs to input the correct key to make it generate an unlocking signal after a specific delay. This specific delay is determined by a finite state machine and the routing delay of the physical layer. This method locks each hardware IP core very well, and the IP hard core cannot work normally without the key. Embedded in the key is proprietary information for the IP designer and buyer. The method mentioned in this paper can not only provide proof for the owner of the IP core, but also trace the source of the illegal dissemination of the IP core.

[0028] See the description below for details:

[0029] A method for implementing hardware circuit intellectual property (IP) protection using delay matching of ...

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Abstract

The invention relates to the field of integrated circuits and aims to provide an IP hard core intellectual property protection method and device based on path delay, wherein the IP hard core intellectual property protection method and device can be used for intellectual property protection of a timing sequence logic which can be applied to input and output and needs multiple delay periods. The IP hard core intellectual property protection method and device can effectively prevent various IP core theft problems, such as a brute force attack, a cleaning attack and reverse engineering. According to the technical scheme, the IP hard core intellectual property protection method based on the path delay comprises the following steps that 1, signals need to pass through a timing sequence logic path circuit of multiple time periods from input to output; 2, a protective path is designed; 3, a designed protective circuit comprises a shifting register, a finite state machine circuit and an interconnecting line, wherein the shifting register is used for storing an initialization secret key, the finite state machine circuit is used for secrete key checking, and the signal delay of the interconnecting line is adjustable; 4, the purpose of protecting a circuit IP is achieved by adjusting and controlling the input and output delay of the protective circuit and the protected circuit. The IP hard core intellectual property protection method and device based on the path delay are mainly applied to integrated circuits.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to a method for protecting IP hard core intellectual property rights based on sequential logic path delay matching. technical background [0002] Intellectual property infringement has become one of the key issues in SoC design based on IP reuse. The illegal use, duplication and dissemination of IP endanger the rights and interests of IP designers. Therefore, various methods of protecting hardware IP have emerged. [0003] Currently widely used hardware IP protection methods include encryption using encryption algorithm, hardware key protection method and hardware watermark protection method. Encryption algorithms such as AES can be used to encrypt the IP core, and only the authorized key can be decrypted and the original IP core can be extracted. The hardware key method is to lock each chip by correlating process difference characteristics and logical functions after the chip ...

Claims

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Application Information

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IPC IPC(8): G06F21/76G06F21/75
CPCG06F21/76G06F21/75
Inventor 刘强李海娥
Owner TIANJIN UNIV
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