Bus control device for field-programmable gate array (FPGA) prototype verification system

A system bus and prototype verification technology, applied in the field of FPGA prototype verification, can solve the problems of high cost and tediousness, and achieve the effect of reducing costs and improving system communication and control channels

Active Publication Date: 2012-01-04
无锡亚科鸿禹电子有限公司
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Problems solved by technology

, an FPGA prototype verification system can only work in one mode, and the mode configuration information is simple, which makes it cumbersome and expensive for users to perform FPGA prototype verification

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  • Bus control device for field-programmable gate array (FPGA) prototype verification system
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  • Bus control device for field-programmable gate array (FPGA) prototype verification system

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Embodiment Construction

[0032] In order to make the above objects, features and advantages of the present application more obvious and comprehensible, the present application will be further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0033] refer to figure 1 , which shows a schematic structural diagram of a bus control device for an FPGA prototype verification system of the present application.

[0034] Described FPGA prototype verification system bus control device comprises main control chip 101, HyperBus bus 102 and a plurality of from FPGA chip 103, wherein, main control chip 101 is connected with a plurality of from FPGA chip 103 by HyperBus bus 102, and HyperBus bus 102 includes mode control line, the main control chip 101 can also perform PC communication with an external PC.

[0035] The main control chip includes:

[0036] Main mode control module: used to set the working mode of the main control chip according to the stat...

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Abstract

The invention provides a bus control device for a field-programmable gate array (FPGA) prototype verification system, and relates to the field of FPGA prototype verification. The device comprises a master control chip, a HyperBus and a plurality of slave FPGA chips, wherein the master control chip is connected with the plurality of slave FPGA chips through the HyperBus; the HyperBus comprises a mode control line; the master control chip comprises a master mode control module, a master data transceiving module and a master data stream monitoring module; and each slave FPGA chip comprises a slave mode control module and a slave data transceiving module. In the device, the master control chip is connected with the HyperBus (HyperSilicon Bus), adjusts the state of the mode control line according to a mode control instruction, or sets the working mode of a system bus by manually setting the state of the mode control line in an initial state, so that a multibus working mode is operated in the same system, great convenience is brought to the FPGA prototype verification, cost is reduced, and the HyperBus provides a good system communication and control path particularly for HyperBus-based secondary development.

Description

technical field [0001] The present application relates to the field of FPGA prototype verification, in particular to an FPGA prototype verification system bus control device. Background technique [0002] FPGA (Field-Programmable Gate Array, Field Programmable Gate Array) prototype verification can not only speed up the development of ASIC and other designs, shorten the development cycle, reduce the development cost of ASIC application systems, but also improve the success rate of tape-out. [0003] However, in the existing FPGA prototyping technology, in the FPGA prototyping system, communication is completed from the FPGA chip through a bus with a fixed mode. , an FPGA prototype verification system can only work in one mode, and the mode configuration information is simple, which makes it cumbersome and expensive for users to perform FPGA prototype verification. Contents of the invention [0004] The technical problem to be solved in this application is to provide a bus...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/20
Inventor 郭文帅刘永宏
Owner 无锡亚科鸿禹电子有限公司
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