77 results about "Multibus" patented technology

The invention provides a bus control device for a field-programmable gate array (FPGA) prototype verification system, and relates to the field of FPGA prototype verification. The device comprises a master control chip, a HyperBus and a plurality of slave FPGA chips, wherein the master control chip is connected with the plurality of slave FPGA chips through the HyperBus; the HyperBus comprises a mode control line; the master control chip comprises a master mode control module, a master data transceiving module and a master data stream monitoring module; and each slave FPGA chip comprises a slave mode control module and a slave data transceiving module. In the device, the master control chip is connected with the HyperBus (HyperSilicon Bus), adjusts the state of the mode control line according to a mode control instruction, or sets the working mode of a system bus by manually setting the state of the mode control line in an initial state, so that a multibus working mode is operated in the same system, great convenience is brought to the FPGA prototype verification, cost is reduced, and the HyperBus provides a good system communication and control path particularly for HyperBus-based secondary development.

The invention provides a moonlet multi-bus multi-passage communication monitoring device and a monitoring method thereof, which relate to a communication monitoring device and a monitoring method thereof. The invention is provided by aiming at solving the problems that the monitoring device can only monitor the bus modes of the same type, in addition, the monitored passages are few. The data signal output end and the data signal input end of an interface module of each path of CAN bus respectively correspond to the signal input end and the signal output end of one path of CAN bus of a first monitoring control module, the interface module of each path of CAN bus respectively receives a path of CAN bus signals from an external bus, the data signal output end and the data signal input end of an interface module of each path of RS-422 bus respectively correspond to the signal input end and the signal output end of one path of RS-422 bus of a second monitoring control module, and the interface module of each path of RS-422 bus respectively receives one path of RS-422 bus signals. The invention can monitor two kinds of buses, can simultaneously monitor multi-passage data, and can be widely applied to various occasions needing simultaneous monitoring of multi-passage data.

The present disclosure relates to real-time data management for a power grid and presents a real-time data management system, a system, method, apparatus and tangible computer readable medium for accessing data in a power grid, a system, method, apparatus and tangible computer readable medium for controlling a transmission delay of real-time data delivered via a real-time bus, and a system, method, apparatus and tangible computer readable medium for delivering real-time data in a power grid. In the real-time data management system of the present disclosure, a unified data model covering various organizations and various data resource is designed and a management scheme for clustered data is used to provide a transparent and high speed data access. Besides, multi-bus collaboration and bus performance optimization approaches are utilized to improve efficiency and performance of the buses. The real-time data management system may also include an event integration and complex event process component to provide a credible prediction on status of the power grid. With embodiments of the present disclosure, it may efficiently manage the high volume of real-time data and events, provide data transmission with a low latency, provide flexible extension of both the number of data clusters and the number of databases to ensure high volume data storage, and achieve a high speed and transparent data access, Additionally, it also enable the rapid design and development of analytical applications, and support the near real-time enterprise decision-making business.

There is a problem that a bandwidth bottleneck occurs because a crossbar switch is used to cope with an increase in scale. In an example of a memory / logic conjugate system according to the present invention, a plurality of cluster memory chips each including a plurality of cluster memories 20 including basic cells 10 arranged in a cluster, the basic cell 10 including a memory circuit, and a controller chip that controls the plurality of cluster memories are three-dimensionally stacked, the plurality of cluster memories 20 located along the stacking direction of the plurality of cluster memory chips and the controller chip are electrically coupled to the controller chip via a multibus 11 including a through-via, an arbitrary one of the basic cells 10 is directly accessed through the multibus 11 from the controller chip so that truth value data is written therein, and whereby the arbitrary basic cell 10 is switched to a logic circuit as conjugate.

A storage device for a multibus architecture includes at least one memory to store data, information, and / or addresses, along with a memory connection having a port to connect the memory to one of the buses of the multibus architecture. The memory connection, the port, and the bus have data lines to transmit data along with address lines to transmit addresses, and / or control information to control the memory and other devices connected to each specific bus within the multibus architecture. A switching device selectively connects the memory connection to one of the buses to enable a memory access to transmit data, addresses, and / or control information to or from the selected one of these buses.

The invention belongs to the technical field of data transmission, aims at solving the problem that PCIE interfaces are insufficient when multiple acceleration cards are used in the same computer, andprovides a PCIE bus extension system. The system comprises a CPU and a PCIE extension backboard in communication connection with the CPU. The PCIE expansion backboard comprises a micro-control unit,a dial switch and an exchange chip. The dial switch and the exchange chip are in signal connection with the micro-control unit; the micro-control unit can set the working mode of the switching chip based on the working state of the dial switch. The system has the beneficial effects that through the at least two PCIE switching chips arranged in the system, a plurality of PCIE X16 slots can be connected in an extended manner, two different connection relationships can be realized between the system and the CPU, and one or two groups of PCIE X16 signal connection between the system and the CPU isrealized; the system can be flexibly set according to application scenarios requiring higher data bandwidth or more PCIE bus interfaces, and two different topology schemes are realized by adopting one set of system.

The invention discloses a unified module configuration strategy for multiple buses. The strategy comprises a tree-shaped module configuration structure for various bus protocols, a multi-bus protocolconfiguration method for the structure, a module channel offset allocation algorithm for the structure, and a protocol library logic organization method for realizing the structure. The device tree structure is composed of nodes and links, CPU nodes are used as root nodes, port nodes are used as child nodes of the CPU nodes, bus protocol nodes are used as child nodes of the port nodes, protocol slave nodes are used as child nodes of a protocol master node, and all the nodes are connected through the links to form a configuration tree. Aiming at the tree structure, the invention provides a multi-bus unified configuration method which comprises the steps of CPU node addition and configuration, port node addition and bus master-slave node addition and configuration. Meanwhile, a module channel offset allocation algorithm is provided for the tree-shaped equipment structure, and the algorithm is based on depth-first traversal and offset accumulation. In order to realize the structure, an infrastructure definition library and a configuration library of each bus need to be realized. The structure and the implementation method can conveniently support the configuration of various bus protocols, facilitate the addition and deletion of new protocols, and reduce the research and development cost and the error rate.

The invention discloses a high-security configurable real-time data transmission framework supporting a heterogeneous bus, which is a constructed unified transmission framework and comprises a transmission module, a unified transmission interface, configuration data and a packet format, wherein the unified transmission framework supports and can configure a heterogeneous bus, specifically supportsa programming interface registration bus based on application software and supports a unified transmission interface; the method has high security and configurable capability, specifically supports the configuration and filtering of data packets in different electromechanical application modes, and supports the transmission start and end positioning and data verification based on a state machine.And the system has the functions of receiving multi-bus data in real time and configuring the multi-bus data. According to the embodiment of the invention, the problems of multiple bus types and non-uniform interfaces are solved, the problems that load data transmission in an electromagnetic environment is easy to cause errors and messages cannot be distinguished due to continuous arrival of thedata are solved, and the problem of transmission real-time performance is solved.

A vehicle communication control module of multibus based on TCN consists of CPU processor, internal memory, reset circuit, LED, clock circuit, temperature control circuit, alarm circuit and power supply circuit. It is featured as connecting CPU processor to FPGA being connected with storage and CAN bus interface as well as MVB bus interface, connecting MVB bus interface to CPU processor through buffer and connecting CPU processor to universal communication interface.

The invention discloses a redundant communication method for seamless switching of multiple communication buses. The number of the communication buses is at least two, each communication terminal is connected with each communication bus, and the redundant communication method comprises the following steps that S1, when a sender sends a message each time, the messages with the same content are pressed into a message sending queue of each communication bus at the same time; S2, each communication bus takes data from the message sending queue of the communication bus and sends the data; and S3, the receiver puts the messages received through each communication bus into the same queue, and for a plurality of mutually redundant messages with the same content, the system uses the first arrived message and discards the later arrived redundant message. During multi-bus switching, bus communication message 'zero' loss, continuous communication data, no data loss and no data repetition can be achieved, so that multi-communication bus seamless switching is realized, and the safety, reliability and availability of a traffic control system are improved.

A bandwidth bottleneck occurs because a crossbar switch is used to cope with an increase in scale. A memory / logic conjugate system according to the present invention, a plurality of cluster memory chips each including a plurality of cluster memories 20 including basic cells 10 arranged in a cluster, the basic cell 10 including a memory circuit, and a controller chip that controls the plurality of cluster memories are three-dimensionally stacked, the plurality of cluster memories 20 located along the stacking direction of the plurality of cluster memory chips and the controller chip are electrically coupled to the controller chip via a multibus 11 including a through-via, an arbitrary one of the basic cells 10 is directly accessed through the multibus 11 from the controller chip so that truth value data is written therein, and whereby the arbitrary basic cell 10 is switched to a logic circuit as conjugate.