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38 results about "Multibus" patented technology
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Multibus is a computer bus standard used in industrial systems. It was developed by Intel Corporation and was adopted as the IEEE 796 bus. The Multibus specification was important because it was a robust, well-thought out industry standard with a relatively large form factor, so complex devices could be designed on it. Because it was a well-defined and well-documented industry standard, it allowed a Multibus-compatible industry to grow around it, with many companies making card cages and enclosures for it. Many others made CPU, memory, and other peripheral boards. In 1982 there were over 100 Multibus board and systems manufacturers. This allowed complex systems to be built from commercial off-the-shelf hardware, and also allowed companies to innovate by designing a proprietary Multibus board and then integrating it with other vendors' hardware to create a system. A good example of this was Sun Microsystems with their Sun-1 and Sun-2 workstations. Sun built custom-designed CPU, memory, SCSI, and video display boards, and then added 3Com Ethernet networking boards, Xylogics SMD disk controllers, Ciprico Tapemaster 1/2 inch tape controllers, Sky Floating Point Processor, and Systech 16-port Terminal Interfaces in order to configure the system as a workstation or a file server. Other workstation vendors who used Multibus-based designs included HP/Apollo and Silicon Graphics.
Multi-bus decoupling distributed embedded hardware rendering architecture, system and method
ActiveCN121985146Aavoid performance bottlenecksImprove computing powerTelevision signal transmission by single/parallel channelsSelective content distributionComputer architectureHardware rendering
The invention discloses a multi-bus decoupling distributed embedded hardware rendering architecture, system and method, and relates to the technical field of ultra-high-definition video hardware processing, and the key points of the technical scheme are that the architecture comprises a multi-bus decoupling module which comprises a plurality of hardware buses which are physically isolated from one another, each hardware bus is an exclusive hardware transmission link bearing a single-type manufacturing task; the modular processing unit is an independent hardware board card and is integrated with an external signal input port, an upstream bus signal input port and a downstream bus signal output port; the plurality of modular processing units are cascaded in sequence through a hardware bus in the multi-bus decoupling module to form a distributed assembly line rendering link; when the modular processing units are newly added, the signal processing capability and the rendering synthesis capability are linearly improved along with the increase of the number of the modular processing units. According to the invention, the problem of performance bottleneck of the traditional architecture in processing 4K / 8K ultra-high-definition and multichannel rendering is fundamentally solved.
Owner:CHENGDU SOBEY DIGITAL TECH CO LTD
Modular reconfigurable vehicle overall configuration self-identification method
This invention belongs to the field of vehicle network information technology, specifically relating to a method for self-identification of modularly reconfigurable vehicle configurations. It solves the problems of cumbersome manual vehicle configuration operations and low scalability in existing methods. Based on a multi-bus network topology, this invention integrates the attribute information of domain controllers on each independent module into the vehicle controller. This includes attribute identification of each module's information, integration of attribute information configuration tables, and distribution of attribute information configuration tables. This achieves interconnectivity of the entire vehicle's information architecture and plug-and-play functionality under module changes. The self-identification algorithm for vehicle configuration in this invention achieves rapid and accurate configuration of modularly reconfigurable vehicles through automation and intelligence, improving vehicle adaptability and flexibility, and providing strong technical support for future intelligent transportation systems.
Owner:CHINA NORTH VEHICLE RES INST
Equipment bus digital twin parallel training evaluation and control method and system
This invention discloses a method and system for parallel training, evaluation, and control based on a digital twin using an equipment bus. It unifies the time-stamping and state-space mapping of multi-bus observation data, and solves for a unified state estimate based on quality indicators, fusion residuals, and cross-bus physical consistency constraints. This drives the state evolution of the digital twin, executing the Lyapunov descent admission condition under synchronization error and end-to-end delay constraints. Further, multi-scenario parallel simulations are conducted to obtain an upper bound on the risk probability and construct a training evaluation function. When the evaluation is below a threshold or the risk exceeds the limit, only the affected control components are subject to safe feasible region projection correction, and closed-loop control commands are output. This invention improves state estimation accuracy, synchronization stability, risk prediction capability, and training control safety.
Owner:BEIJING ZHONGKE ZHIYI TECH CO LTD
Spacecraft-oriented software on-orbit multi-bus fault-tolerant reconstruction system and method
PendingCN122044937ARedundant data error correctionRedundant hardware error correctionData packElectronic information
The invention discloses a spacecraft-oriented software on-orbit multi-bus fault-tolerant reconstruction system and method, and relates to the technical field of spacecraft electronic information. The system comprises a ground uploading subsystem, an on-satellite reconstruction management subsystem, a CAN and RS485 dual-bus redundant network and a load reconstruction client. The on-satellite reconstruction management subsystem segments software to be reconstructed according to 256KB, data packets in the segments are transmitted out of order, and transmission continuity is guaranteed through dual-bus hot backup and fault switching; and the load reconstruction client executes three-level verification of data packets, segments and files, and selectively retransmits the data packets, the segments and the files according to abnormal degrees. According to the scheme, through multi-bus redundancy, segmented transmission and a multi-stage fault-tolerant mechanism, multi-load collaborative updating is achieved, the space extreme environment is adapted, the reliability and efficiency of software on-orbit updating are greatly improved, algorithm iteration can be completed without changing hardware, and the spacecraft task life cycle is prolonged.
Owner:BEIJING NORMAL UNIVERSITY
A train control and management system based on vehicle-mounted multi-bus fusion
This invention discloses a train control and management system based on multi-bus fusion in rail transit, relating to the field of onboard network control technology. Specifically, it includes: a multi-path acquisition module, a confidence assessment module, a cross-validation module, and a simulation prediction module; deploying three independent sensing paths, which are uploaded in parallel to the fusion processor via different onboard multi-buses at 100ms intervals; calculating confidence scores for the estimated data output by each sensing path based on Bayesian methods to determine the path's reliability and mapping it to discrete quality levels; performing three-way voting through weighted K-fold cross-validation to calculate a consistency index and compare threshold judgment instructions; constructing a digital twin model, and in case of conflict, performing Monte Carlo simulation for the next cycle, outputting the probability of the result to switch the bus fusion management strategy, effectively avoiding system blind spots caused by single sensor or bus failures, and improving the energy utilization efficiency of trains under high-speed sudden changes, severe load fluctuations, or strong interference scenarios.
Owner:BEIJING QIFAN FUTURE TECH CO LTD
Automated testing method and system for vehicle body control network communication signals
The application discloses a vehicle body control network communication signal automatic test method and system, comprising: analyzing a vehicle-mounted CAN network database file, extracting CAN bus, message ID, message name and signal name information, and generating a signal file; based on the signal file and a signal sending configuration file configured for each test signal, constructing a message sending queue through a priority queue and a real-time thread, sending a trigger CAN signal to a first to-be-tested hardware device based on the queue, triggering a second to-be-tested hardware device to run an Ethernet communication protocol executable file to send a trigger Ethernet signal to the first to-be-tested hardware device, receiving and recording response signals and time stamps of the to-be-tested hardware device; and analyzing signal values and communication timing and generating a test report. The application realizes automatic test, accurately coordinates multiple bus signal cooperation, forms a complete test closed loop, improves test efficiency and reliability, and is suitable for communication test of a vehicle body control multiple bus fusion architecture.
Owner:AUTOCORE INTELLIGENT TECH (NANJING) CO LTD
Vehicle backup radar off-line detection system and method
This application provides a vehicle reversing radar off-line detection system and method, including: a multi-bus data acquisition device, which synchronously acquires CAN, LIN, and Ethernet data streams during a standardized vehicle reversing process and configures time markers for each data stream based on the same hardware clock source; a spatiotemporal alignment determination module, which identifies the response signals of the same physical event in different buses, calculates the maximum timing deviation between time markers, and determines whether each data stream meets timing consistency requirements; a multimodal joint verification module, which, when timing consistency is met, performs joint determination on acoustic response, optical response, and image response characteristics based on the aligned time axis and outputs the detection result; and a response handling module, which triggers a vehicle interception command and maintenance scheduling process when the detection result is a failure. This application solves core problems such as the inability to synchronize cross-protocol data, the lack of acoustic-optical-image collaborative verification, the fact that faults are only located at the system level, and the lack of an automatic handling mechanism.
Owner:CHERY AUTOMOBILE CO LTD
Multi-bus wireless communication system
A multi-bus wireless communication system is disclosed. The multi-bus wireless communication system includes a network access circuit and a radio access circuit, which are physically separated but interconnected via a coaxial bus(es). The radio access circuit includes an antenna(s) and an electronic device(s) for optimizing the antenna(s) based on a bus telegram(s) communicated over a single-wire bus(es). The network access circuit generates and multiplexes the bus telegram(s) with a radio frequency (RF) signal(s) for communication to the radio access circuit over the coaxial bus(es). The radio access circuit, sequentially, demultiplexes the multiplexed signal(s) into the RF signal(s) and the bus telegram(s). Accordingly, the radio access circuit can control the electronic device(s) to optimize the antenna(s). By multiplexing and demultiplexing the RF signal(s) and the bus telegram(s) on opposite ends of the multi-bus wireless communication system, it is possible to optimize the antenna(s) over the coaxial bus(es) in a vehicular environment.
Owner:QORVO US INC
Multi-bus replicator using RF serializer / deserializer for chip-to-chip interconnect
ActiveUS12579085B1Digital computer detailsElectric digital data processingComputer architectureMultibus
Multiple examples are disclosed of a multi-bus replicator using RF SerDes components for a chip-to-chip interconnect. In one example, a multi-bus replicator comprises an initiator write bus replication unit to receive write commands and write data from a plurality of write buses and to transmit the write commands and the write data using one or more RF SerDes transmitters; and a target write bus replication unit to receive the write commands and the write data from the RF SerDes transmitters and to provide the write commands and the write data on a plurality of write buses.
Owner:TEXAS MILKYWAY INC
System capable of efficiently processing massive aviation bus data
The invention discloses a system capable of efficiently processing massive aviation bus data, which comprises a multi-bus protocol parallel acquisition module, a heterogeneous data analysis engine, a service calculation and statistical analysis module, a hierarchical storage management module and a resource scheduling and load management module, the multi-bus protocol parallel acquisition module comprises a protocol interface array, a many-core processing core and a dynamic buffer management unit; the heterogeneous data analysis engine comprises a configurable protocol analyzer, a data path selection and frame coding unit and a streaming data processing pipeline; the business calculation and statistical analysis module comprises a distributed real-time calculation unit, a multi-layer statistical analysis unit and a semantic analysis unit; the hierarchical storage management module adopts a three-layer storage architecture, and the resource scheduling and load management module comprises a load prediction unit, a self-adaptive resource allocation unit and a model migration and knowledge sharing unit. The problems that the real-time performance of aviation multi-bus data processing is insufficient, the protocol compatibility is limited, and the system resource utilization rate is low are solved.
Owner:CHENGDU GUYU LIZE TECHNOLOGY CO LTD
A loongson 2K-based vpX management control arbitration device and method
This invention relates to a VPX management and control arbitration device and method based on the Loongson 2K chip, belonging to the field of intelligent management and control and its localization technology. This invention, through a multi-bus, multi-redundancy mechanism, can achieve real-time decoding output of B-code timing information, multi-channel switching output of video and control functions, and interconnection of gigabit Ethernet networks. The core chip adopts an independently controllable domestic design, unaffected by bans. In unattended operation, the arbitration device can monitor the heartbeat of external host modules in real time, performing real-time monitoring, management, and control, achieving hot backup from modules to applications and rapid response intelligent management and control. All external display and control outputs are implemented by the arbitration device; the external host module only needs to focus on control calculations, while the management tasks are centralized in the arbitration device, and tasks are distributed among modules, reducing the failure rate.
Owner:TIANJIN JINHANG COMP TECH RES INST
Electronic product debugging equipment based on line multiplexing
The utility model relates to electronic product debugging equipment based on line multiplexing, and belongs to the technical field of electronic product debugging. Comprising a turntable external controller, a connecting cable and a turntable internal controller, the rotary table external controller sends a channel gating signal and a single bus signal to the connecting cable through a switch or a control signal from test equipment; the controller in the rotary table receives a channel gating signal and a bus signal of the controller outside the rotary table through the connecting cable and connects the bus signal to a corresponding channel according to the channel gating signal, and the connecting cable is used for connecting the controller outside the rotary table with the controller in the rotary table. According to the utility model, the requirements on the slip ring of the rotary table during testing of products with a large number of interfaces and a large number of buses can be reduced. The transmission capability of the existing rotary table slip ring can be economically and conveniently increased, and an automatic interface is provided, so that program control use is easy to realize.
Owner:BEIJING QINGYUN AVIATION INSTR CO LTD
Automatic test system and method for diagnosis and refresh of automobile controller
The invention provides an automatic test system and method for diagnosis and refresh of an automobile controller, and belongs to the field of automobile electronic testing. The system comprises: an instruction import and dynamic analysis module, which is used for converting a test instruction into a standardized test sequence recognizable in the system; the diagnosis service simulation and multi-dimensional error injection module is used for simulating a standard diagnosis process and injecting controllable faults; the response verification and self-adaptive process control module is used for verifying ECU response in real time and dynamically adjusting a test strategy; the multi-bus collaborative test module is used for simulating a complex network environment and verifying the ECU stability; and the CAN message recording and analyzing module is used for recording and analyzing bus message data in the whole process. Automatic verification, error injection testing and communication message recording of the refreshing process of the controller are achieved through the Labview upper computer, and the testing reliability and the abnormal scene coverage rate are improved; manual omission is avoided through automatic verification, and the test period is shortened.
Owner:SAIC GM WULING AUTOMOBILE CO LTD
Microcontroller bus arbitration method and device based on Round-Robin algorithm
The invention relates to the technical field of computer application, in particular to a microcontroller bus arbitration method and device based on a Round-Robin algorithm. According to the method and the device, an arbitration result is generated through pointer calculation in combination with a mask mode. The device comprises a multi-bus input interface, an internal interconnection matrix, a Round-Robin bus arbitration module and a slave device bus output interface. According to the method, priority data transmission of bus arbitration can be better processed and controlled, the situation that transmission of other buses is shelved due to the fact that a certain single high-priority channel suddenly occurs or occupies a system bus for a long time is prevented, and resources of bus allocation and data transmission are controlled in a more reasonable and efficient mode.
Owner:NO 47 INST OF CHINA ELECTRONICS TECH GRP
Multiplexing control circuit of multi-bus signal and image signal generator
The utility model provides a multiplexing control circuit for multi-bus signals and an image signal generator. The multiplexing control circuit comprises a controller, an output line switching module and an external interface module, the controller comprises at least one group of IIC bus protocol pins and six QSPI bus protocol pins; the controller is connected with a first group of input ends of the output line switching module through IIC bus protocol pins; the controller is connected with a second group of input ends of the output line switching module through a multiplexing target number of pins in the six QSPI bus protocol pins, and is connected with the external interface module through the remaining pins in the six QSPI bus protocol pins; the output end of the output line switching module is connected with the external interface module, and the output end of the output line switching module is communicated with the first set of input ends or the second set of input ends according to a switching control signal sent by the controller. Therefore, different bus signals can be provided to the outside through one external interface module.
Owner:MEGAROBO TECH CO LTD
Embedded hardware rendering signal processing method and device, terminal and medium
ActiveCN122053775ATelevision system detailsColor television detailsComputer architectureHardware architecture
The invention discloses an embedded hardware rendering signal processing method, an embedded hardware rendering signal processing device, a terminal and a medium, and relates to the technical field of ultra-high-definition video signal processing, and the technical scheme is characterized in that format unification and synchronous calibration are performed on multi-type heterogeneous signals, and a to-be-processed signal source is selected to obtain a standardized baseband signal; according to the manufacturing task requirements of different buses in the multiple buses, performing differentiated exclusive rendering operation on the standardized baseband signal; distributing the rendered signal to a corresponding bus based on logic of multi-bus isolation and distributed unit cascading, and transmitting the rendered signal to a next-level distributed processing unit; and synthesizing the cascaded signals of the buses, and converting the signals into a target format for independent output. According to the method, a complete pipelined processing method including signal standardization preprocessing, bus exclusive rendering, collaborative isolation distribution and synthesis output is constructed, and deep adaptation of software processing logic and a multi-bus distributed hardware architecture is achieved.
Owner:CHENGDU SOBEY DIGITAL TECH CO LTD
Multibus replicator using RF serializers / deserializers for inter-chip interconnection
PendingCN122086817Aeliminate overheadlower latencyArchitecture with single central processing unitElectric digital data processingComputer architectureMultibus
Several examples of using RF SerDes components for chip-to-chip interconnect multibus replicators are disclosed. In one example, the multibus replicator includes: an initiating write bus replicator unit for receiving write commands and write data from multiple write buses and transmitting write commands and write data using one or more RF SerDes transmitters; and a destination write bus replicator unit for receiving write commands and write data from RF SerDes transmitters and providing write commands and write data on multiple write buses.
Owner:TEXAS MILKWAY INC
A multi-bus ad-hoc network device with a three-CPU architecture
ActiveCN115343993BRich interactionHigh communication rateProgramme controlComputer controlComputer networkCpu architecture
The application belongs to the technical field of vehicle communication, and discloses a multi-bus self-organizing network device with a three-CPU architecture, which comprises a motherboard, a first bus board, a second bus board and a third bus board; the motherboard is connected with an external power supply, and the first bus board, the second bus board and the third bus board are all connected with the motherboard. The three bus boards can realize the starting of a FlexRay bus network, and can communicate with an upper computer through the CAN bus of the bus board; a CAN bus interface and two FlexRay bus interfaces are integrated in a small space, the interaction mode of the two buses is perfect, the communication rate is high, the protection level is high, and the anti-electromagnetic interference is high; the FlexRay bus can be connected with multiple bus nodes, and can communicate with the upper computer through the CAN bus, so that the FlexRay bus communication condition can be monitored in real time and fault positioning can be performed, and the use requirements of military armored vehicles on multiple bus communication, multiple bus information interaction, complex environment and strong anti-interference are met.
Owner:INNER MONGOLIA YIJI GRP HONGYUAN ELECTRIC APPLIANCE CO LTD
Multi-bus time sequence generation device and method based on FPGA (Field Programmable Gate Array)
PendingCN121958161AMeet complex timing generation needsArchitecture with single central processing unitTransmissionCommunication unitProcessing element
The invention provides a multi-bus time sequence generation device and method based on an FPGA (Field Programmable Gate Array), relates to the technical field of time sequence control, and solves the technical problem that efficient transmission of time sequence data and equipment universality are difficult to consider in the prior art. The device specifically comprises a communication unit used for receiving configuration parameters and command parameters issued by an upper computer; the multi-bus unit is used for realizing address mapping between an upper computer and an SRAM (Static Random Access Memory) through multiple buses, performing high-speed reading and writing of time sequence data and storing configuration parameters; the FPGA data processing unit is used for analyzing the configuration parameters and the command parameters, constructing address mapping, processing data, carrying out error code detection and generating a target time sequence; the external input unit is used for providing an operation main clock, a voltage-stabilized power supply, a verification signal and a synchronization signal; and the driving interface unit is used for providing a driving interface and converting the target time sequence into a signal adaptive to the tested equipment. The invention is used for generating the time sequence signal.
Owner:ANHUI SUN CREATE ELECTRONICS
High-speed data recording method and system based on multi-bus heterogeneous fusion
PendingCN121901072AEfficient use ofreduce wasteHardware monitoringBiological modelsData streamData recording
The invention relates to the technical field of data recording, and discloses a high-speed data recording method and system based on multi-bus heterogeneous fusion, and the high-speed data recording method based on multi-bus heterogeneous fusion comprises the steps: collecting real-time data characteristic parameters of each heterogeneous bus, and constructing a characteristic vector; extracting a time sequence mode of each bus feature vector; dynamically adjusting a cache resource allocation proportion of each bus based on a reinforcement learning technology; constructing a bus data feature knowledge graph by pre-training a basic strategy model under a plurality of working conditions; recognizing system working condition changes and triggering strategy switching; a two-stage cache architecture is realized, and the cache size of each bus is dynamically adjusted according to the cache resource allocation proportion; according to the method and the device, the technical problems that cache resource distribution is fixed in heterogeneous bus data recording, the adaptability to burst data streams is insufficient, and the performance is temporarily reduced during working condition switching are solved, and efficient cache resource utilization and stable data recording are realized.
Owner:BEIJING TIANCHEN HECHUANG TECH CO LTD
Multiple bus bleed-down
In some implementations, a supervisory electronic control unit (ECU) (110) may output, to a first controller (220a), a first control signal commanding the first controller (220a) to provide a first voltage to a first bus (210a) during a bleed-down operation. The supervisory ECU (110) may output, to a second controller (220b), a second control signal commanding the second controller (220b) to provide a second voltage to a second bus (210b) during the bleed-down operation. The supervisory ECU (110) may activate, during the bleed-down operation, a sinking device (225) electrically connected to the first bus (210a) and the second bus (210b).
Owner:CATERPILLAR INC
Flexible configurable data analysis device and method based on FPGA
The invention relates to the technical field of network message analysis, and discloses a flexible configurable data analysis device and method based on an FPGA (Field Programmable Gate Array), which can adapt to multi-protocol message analysis by storing a plurality of message analysis templates through an RAM (Random Access Memory) and matching a search module with message frame identification information, and break through the limitation that the existing FPGA analysis mostly aims at a single protocol and is poor in universality. Besides, the analysis module can analyze sub-data in the message load according to the matching template without depending on upper software, so that the problems of low efficiency and poor real-time performance caused by the fact that an existing FPGA only analyzes a frame header fixed field and load data needs to be processed by software are solved; therefore, the flexible and efficient application requirements of a multi-bus heterogeneous high-speed network system on multi-type data processing are met.
Owner:XIAN MICROELECTRONICS TECH INST
A bus fault hierarchical linkage control method for full liquid crystal instrument of a passenger car
ActiveCN122027439BAccurately reflect the comprehensive impactComprehensive representation of dynamic threat levelsCar passengerSingle fault
The application relates to the technical field of linkage control and discloses a passenger car full-liquid crystal instrument multi-bus fault hierarchical linkage control method, which comprises the following steps: collecting fault data of each bus of a target object in real time, analyzing the fault data, and generating a linkage influence weight value representing the influence of the bus fault on the cooperative operation of the target object, wherein the target object is a passenger car; through the generation of the linkage influence weight value, the comprehensive influence of a single fault on the cooperative operation of the whole vehicle is accurately reflected; then, according to a dynamic hierarchical reference value, the fault is divided into an emergency linkage level, a medium-priority linkage level and a low-priority linkage level, the adaptive grading of the fault processing sequence is realized, a linkage risk comprehensive value is calculated, the dynamic threat degree of concurrent faults to the stability of the vehicle is quantified, and finally, the differentiated linkage control is executed according to the linkage risk comprehensive value, so that the accurate and efficient linkage control under the concurrent fault of the passenger car is realized, and the safety and control cooperativity of the whole vehicle under the multi-bus concurrent fault scene are improved.
Owner:XIAMEN JINLONG CAR ACCESSORIES CO LTD
A multi-bus data fusion processing method and system based on a logging instrument
This invention relates to a multi-bus data fusion processing method and system based on a logging tool, belonging to the field of oil and gas drilling measurement data transmission technology. The method includes receiving logging data collected by the logging tool's measurement probe and different data packets sent by the system bus; performing preliminary processing on the received logging data, including self-identification, self-diagnosis, and self-correction; identifying and converting the different received data packets; performing real-time fusion processing on the self-identified, self-diagnosed, and self-corrected logging data and the identified and converted data packets; and packaging the real-time fused data according to different communication protocols, and sending the packaged data to the system bus and / or storage unit. This invention forms a multi-bus data fusion processing system, which is embedded in the logging tool connected to the drilling string, enabling data interaction between the logging tool and other instruments in the instrument string, and achieving parallel processing and self-diagnosis of multiple sets of data.
Owner:CHINA NAT PETROLEUM CORP +1
Evaluation and control method and system for digital twin parallel training based on equipment bus
The invention discloses a digital twin parallel training evaluation and control method and system based on an equipment bus. Performing unified time scaling and unified state space mapping on multi-bus observation data, and solving unified state estimation based on quality indexes, fusion residual errors and cross-bus physical consistency constraints; driving digital twinning state evolution, and executing a Lyapunov descent admission condition under the constraint of a synchronization error and an end-to-end time delay; further carrying out multi-scene parallel deduction to obtain a risk probability upper bound and constructing a training evaluation function; and when the evaluation is lower than the threshold value or the risk exceeds the limit, only performing safety feasible region projection correction on the influenced control component and outputting a control instruction in a closed loop. According to the method, the state estimation precision, the synchronization stability, the risk prediction capability and the training control safety can be improved.
Owner:BEIJING ZHONGKE ZHIYI TECH CO LTD
Multi-bus heterogeneous IP transmission system based on Rayleigh-core micro eight-core chip
The invention relates to a multi-bus heterogeneous IP transmission system based on a Rayleigh-core micro eight-core chip, and belongs to the technical field of computer network communication. According to the multi-bus heterogeneous IP transmission system based on the Raycore micro eight-core chip, all components of the main board and the interface board are domestic devices, and 100% localization of the board-level components is achieved; the structural parts are all domestic products; meanwhile, RK3576 master control CPU unit software, RK3576 algorithm CPU unit software and MCU software are self-researched; hardware, software and the whole machine can be completely produced in China, so that the IP information transmission system is completely autonomous and controllable.
Owner:BEIJING INST OF COMP TECH & APPL
Multi-bus proportional valve amplifier with display control panel
ActiveCN223839447UOperating means/releasing devices for valvesPower amplifiersCommunication interfaceProportional control
A multi-bus proportional valve amplifier with a display control panel comprises an amplifier main board, a proportional controller panel and a first fixing piece fixedly connected with the amplifier main board and the proportional controller panel. The amplifier mainboard comprises an analog quantity port, a digital communication interface, and a mainboard panel interface, a first dial switch and a second dial switch which are electrically connected with the digital communication interface respectively; the proportional controller panel comprises a display control panel and a fixed panel parallel to the display control panel; the display control panel comprises a panel screen, keys and a display control panel interface; the display control panel and the fixed panel are fixedly connected through a second fixing piece; and the mainboard panel interface is electrically connected with the display control panel interface. According to the utility model, the display state information is abundant, the real-time display and output can be effectively realized, the adjustment and modification of working parameters are convenient, under the control of multiple buses, the anti-interference capability and stability are improved, the control precision and flexibility are improved, the system expansion is convenient, the maintenance efficiency is optimized, the compatibility and standardization advantages are realized, and the cost is low.
Owner:BEIJING HYDRAULIC TECH RES INST CO LTD
Multi-bus PLC configuration method and system, electronic equipment and storage medium
The invention provides a multi-bus PLC configuration method and system, an electronic device and a storage medium, relates to the technical field of PLCs, and is used for controlling logic programming software of a master PLC to add management objects corresponding to the types of buses, and aiming at slave PLCs connected through a target bus, the management objects corresponding to the types of the buses are added in the logic programming software of the master PLC. The master PLC performs data interaction with the slave PLC through the following steps: a management object corresponding to a target bus forms task information matched with the master PLC in format based on received task information and stores the task information in a PLC memory bus cache space corresponding to the target bus; and when the PLC runs, the software carries the I / O data in the PLC memory bus cache space and the PLC memory I / O data cache space corresponding to the target bus according to a task period and a task rule, so that data interaction between the master PLC and the slave PLC is realized. The method and the device are used for realizing integration of different bus devices and are high in efficiency and low in development difficulty.
Owner:CLP INTELLIGENT TECH CO LTD
Multi-bus protocol network control method, device, equipment, storage medium and product
This application discloses a multi-bus protocol network control method, apparatus, device, storage medium, and product, relating to the field of vehicle communication technology. The method includes: waking up the target protocol node and the target area controller when a wake-up source is detected on the target protocol node corresponding to a certain bus protocol in a regional control topology; determining whether cross-segment wake-up and cross-region wake-up are needed based on preset vehicle sleep wake-up conditions; if needed, determining other area controllers to be woken up across regions and target network segments to be woken up in other regions based on preset vehicle sleep wake-up conditions; and performing wake-up control. This application achieves multi-bus protocol multi-segment network collaborative control by simultaneously determining whether cross-segment and cross-region control of other area controllers and other network segments is needed when controlling a bus protocol node and an area controller, thereby determining all area controllers and network segments that need to be controlled according to requirements.
Owner:DONGFENG MOTOR GRP
Multi-bus navigation computer and software architecture
PendingCN121207154ANavigational calculation instrumentsNavigation by speed/acceleration measurementsComputer architectureSoftware architecture
The invention provides a multi-bus navigation computer and a software architecture, and relates to the technical field of navigation. Comprising a programmable fusion chip FMQL used for IMU data acquisition and processing, navigation solution and multi-bus transmit-receive control; the storage circuit comprises a FLASH circuit and a DDR circuit and is used for storing programs and data; the power supply circuit is used for supplying power according to the voltage, current and power requirements of the programmable fusion chip FMQL and the storage circuit; and the peripheral interface circuit of various buses is used for realizing communication of an ARINC429 aviation bus, an MIL1553B aviation bus, the Ethernet and an RS422 / 232 serial communication bus. The problems that in the prior art, a navigation computer hardware circuit is high in cost and large in size and weight are solved.
Owner:贵州航天控制技术有限公司