Software segmentation method based on FPGA logic

A software and logic technology, applied in the field of software segmentation based on FPGA logic, which can solve problems such as incorrect function, poor operation performance of the entire IC circuit, and unstable operation.

Active Publication Date: 2021-01-05
S2C
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

[0003] The traditional software segmentation method based on FPGA logic adopts the minimum cut algorithm based on graph theory. Most of its multi-FPGA prototype systems only consider the resource weight and interconnection constraints of a single FPGA, resulting in poor operating performance of the entire segmented IC circuit, incorrect functions or job instability

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  • Software segmentation method based on FPGA logic

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Embodiment Construction

[0031] Embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings.

[0032] Embodiments of the present disclosure are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in this specification. Apparently, the described embodiments are only some of the embodiments of the present disclosure, not all of them. The present disclosure can also be implemented or applied through different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that, in the case of no conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in the present disclosure, a...

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Abstract

The invention belongs to the technical field of electronic computer software application, and particularly relates to a software segmentation method based on FPGA logic. The method comprises a FlipFlop and FPGA analysis step, a compression ratio presetting step and a segmentation step. Processing of related constraints such as clock domain grouping, FlipFlop and compression ratio which influence IC circuit operation is added into a traditional minimum cut algorithm based on resource weight, so that the operation clock frequency constraint of an IC circuit system can be met in a multi-FPGA prototype system segmentation process, an obtained segmentation result enables the whole IC circuit to be better in operation performance, correct in function and stable in work.

Description

technical field [0001] The invention belongs to the technical field of electronic computer software applications, and in particular relates to a software segmentation method based on FPGA logic. Background technique [0002] With the development of computing technology and the advent of the era of big data, the segmentation of VLSI has attracted more and more attention. Typical applications include the segmentation of multi-FPGA logic systems in VLSI simulation verification. Weights divide logic circuits into groups, enabling scalable, high-performance system verification. [0003] The traditional software segmentation method based on FPGA logic adopts the minimum cut algorithm based on graph theory. Most of its multi-FPGA prototype systems only consider the resource weight and interconnection constraints of a single FPGA, resulting in poor operating performance of the entire segmented IC circuit, incorrect functions or Work is unstable. Contents of the invention [0004...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/331G06F115/02G06F115/10
CPCG06F30/331G06F2115/02G06F2115/10
Inventor 张吉锋李伟
Owner S2C
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