12 results about "Hardware Trojan" patented technology

The application discloses a model training process-oriented computing power chip hardware Trojan design method, and relates to the field of integrated circuit security.The method is designed in view of the computing architecture of a GPU, and contains a flip-flop, a finite state machine and a load circuit.The flip-flop identifies the typical characteristics of deep learning training by monitoring the arithmetic instruction intensity and the Warp concurrent activity of the GPU runtime; when the characteristics meet a preset threshold, the finite state machine is triggered, so that the hardware Trojan enters an activated state.The load circuit has two types of designs: the first type is a gradient flipping circuit which interferes with the gradient update direction by modifying the sign bit output by a floating point calculation unit, so that the model cannot converge; the second type is a redundant calculation circuit which consumes computing resources by inserting invalid floating point operations, thereby prolonging the training time.The application designs and triggers the hardware Trojan by utilizing the architecture characteristics of the GPU, has high concealment, and can effectively destroy the accuracy and efficiency of a deep learning training task.

The invention discloses a chip Trojan horse detection and shielding system and method based on multiple confusion links, and relates to the technical field of integrated circuit safety. According to the method, a plurality of confusion links which are large in structural difference, identical in function and similar in time delay are designed for sensitive critical paths in a chip. A write-only unreadable register is adopted to store link selection information, so that an attacker is prevented from stealing or tampering a currently activated path by means of scanning a chain, debugging an interface and the like; a dual-stage operation mechanism is adopted, a test stage is combined with high-precision delay measurement and anomaly analysis to accurately identify a path in which Trojan is implanted, and a formal stage is dynamically switched to a Trojan-free path based on safety link information stored in a register, so that a chip is ensured to automatically avoid malicious logic during operation, and active defense instead of passive detection is realized. The method is superior to a traditional hardware Trojan horse protection scheme in detection precision, operation safety and implementation cost, and an efficient, reliable and easy-to-integrate solution is provided for chip safety.

The present disclosure describes various embodiments of hardware trojan triggering (HTT) signal analysis. As such, an exemplary method comprises capturing switching activity of nodes for a design of an integrated circuit during a simulation of an application of a test pattern to the design; identifying one or more nodes in a graphical representation of the design that do not toggle within an individual window of time across multiple windows of time; determining unique paths that can be formed by the identified nodes within each of the multiple windows of time; determining one or more unique paths that occur across consecutive windows of time; appending the one or more unique paths that occur across consecutive windows of time in a set; and outputting the one or more unique paths in the set as rare trojan horse triggering paths for the design. Other systems and methods are also presented.

The application discloses a GPU hardware Trojan detection method based on task function consistency and Kernel feature analysis, and belongs to the field of integrated circuit security. The application firstly selects multiple deep learning tasks, generates multiple different model structures and parameter configurations of code instances for each task by using a large model, and constructs a deep learning task instance set. Then, the task instance set is executed on a trusted GPU, and the output results and Kernel hardware performance features of each task instance are collected. The uniform manifold approximation and projection algorithm is adopted to reduce the features of the normal Kernel sample set on the trusted GPU, and a Kernel anomaly detection model based on a deep robust one-class classification algorithm is trained. Finally, the task instance set is executed on the GPU to be tested, and whether the hardware Trojan exists is determined through function consistency verification and Kernel anomaly detection. The application first proposes a hardware Trojan detection method for GPUs, does not need to access the details of the underlying hardware implementation of the GPU, does not depend on any hardware Trojan sample, and has good applicability and implementability.

The present invention is directed to an automated methodology based on GNN to model IC and mitigate hardware security threats. The present invention features a system for detecting hardware Trojans and IP piracy in a circuit. The system may be based on a GNN. The system may convert a plurality of base-level files from the circuit into a graph, convert this graph into a vectorized graph embedding through the use of the GNN, and use the vectorized graph embedding to identify and remedy potential hardware Trojans as well as identify potential IP piracy between two different circuits.

A hardware trojan security system may perform a computer implemented method to secure an electronic facility in relation to a hardware trojan, by performing a trojan vulnerability analysis, locating an instrument site location, identifying a selected instrument in relation to an effect of the trojan, marking instrument control-side markers and instrument operative-side markers, marking facility model control-side markers and facility model operative-side markers, marking access architecture control-side markers, and connecting the instrument with the facility model and access architecture by matching corresponding markers.

This invention discloses a sensor hardware Trojan detection method and system based on signal injection, belonging to the field of sensor anomaly detection. A clean sensor is placed in the target environment, and characteristic data such as response time are collected. Reinforcement learning is used to construct the environment using the sensor and the transmitting device, and a policy model is trained. The state space includes sensor output, transmission parameters, and signal type, while the action space contains adjustable parameters of the transmitting device. During training, the model adjusts parameters according to the state. The environment generates new signals that act on the sensor and provide feedback on the state and reward. In the testing phase, a transmitting device is selected, and a batch of sensors to be tested and clean sensors are placed in it. Initial parameters for frequency sweep are set, and the trained policy network optimizes the transmission parameters in real time. Based on the outputs of the two sensors, the 3σ outlier detection method is used to determine whether the response of the sensor under test is normal, thereby determining whether the sensor has been implanted with a Trojan. This invention utilizes reinforcement learning to optimize transmission signal parameters, enabling more efficient Trojan detection.

The invention relates to the technical field of integrated circuit hardware security, in particular to an interpretable hardware Trojan horse detection method based on an attention mechanism, and the method comprises the steps: obtaining a to-be-detected integrated circuit design, and carrying out the flattening processing; converting the flattened integrated circuit design to be tested into an abstract syntax tree; extracting paths from all leaf nodes to leaf nodes in the to-be-tested integrated circuit design based on the abstract syntax tree; inputting all the extracted paths into a code2vec model, and carrying out binary classification on the integrated circuit design to be detected to realize hardware Trojan horse detection; and sorting the attention scores of the paths obtained by the attention layer calculation of the code2vec model in the classification process according to a descending order, selecting a plurality of important paths with the highest attention score, and providing explanation for a detection result based on code information contained in the important paths. According to the method, automatic detection of the hardware Trojan horse in register transfer level integrated circuit design is realized, a decision mechanism of the model can be obtained based on an attention mechanism, and a detection result is explained.

The application discloses a hardware Trojan protection method and system based on observability, and relates to the technical field of hardware circuit security, so as to solve the problem that a hardware Trojan is difficult to be found after being inserted into a circuit, and comprises the following steps: modeling circuit netlist information by constructing a directed cyclic graph; calculating the observability of internal nodes according to the constructed directed cyclic graph, and judging the visibility of the logic values of the internal nodes of the circuit; improving the observability of the nodes by iteratively analyzing and inserting XOR / XNOR gates at appropriate positions; and restoring the function of the circuit. The application improves the pertinence and effectiveness of the protection strategy, enhances the resistance and reliability of the circuit, and reduces the success rate of hardware Trojan attacks, so that the stability and reliability of the circuit performance are maintained while the security is improved.

The invention discloses a hardware Trojan horse detection precision improving method and system and a computer readable storage medium, and relates to the technical field of integrated circuit safety. The system comprises a data acquisition module, a modeling analysis module, a machine learning module and a detection and compensation execution module. Based on a plurality of key performance parameter data of a Monte Carlo analysis set integrated circuit under different process corners, a quantitative relation model between process deviation parameters and the key performance parameters is established through regression analysis, and a machine learning vector machine model is constructed to train collected data and corresponding process deviation diffusion factors; and establishing a prediction model for predicting the influence of the process deviation, integrating the trained prediction model to a hardware Trojan horse detection system, predicting a deviation diffusion factor under the current process condition in real time, and dynamically adjusting a detection threshold value to compensate the influence of the process deviation so as to achieve the purpose of distinguishing the process deviation from the hardware Trojan horse. Therefore, the accuracy and reliability of hardware Trojan horse detection are improved, and the false alarm rate is reduced.

Various embodiments of the present disclosure provide hardware trojan detection using Shapley ensemble boosting. In one example, an embodiment provides for extracting a plurality of features related to hardware trojan detection from one or more circuit samples related to one or more circuits, training one or more machine learning models based at least in part on the plurality of features, modifying the one or more machine learning models based at least in part on a set of Shapley values to generate one or more enhanced machine learning models for hardware trojan detection related to the one or more circuits, and deploying the one or more enhanced machine learning models for the hardware trojan detection related to the one or more circuits.

The invention discloses a multi-task interpretable hardware Trojan horse detection method and system based on a graph attention mechanism, and belongs to the field of integrated circuit hardware safety. The method comprises the following steps: analyzing a gate-level netlist, abstracting the gate-level netlist into a directed graph, and extracting node features; the multi-head graph attention network is used for learning nodes and embedding representation of the graph; node-level Trojan classification and graph-level risk classification are executed at the same time through a multi-task learning framework, and joint optimization training is carried out; based on probability distribution output by the model, calculating a hazard severity risk value and a triggering score in combination with a preset risk assessment function, and fusing to obtain a comprehensive risk score; and for the high-risk netlist, the feature contribution degree is quantified by adopting GNNExplainer, an evidence chain is constructed, and a large language model is driven to generate an interpretable report containing risk composition, key evidence and an abnormal mode. According to the method, high-precision Trojan horse detection and fine-grained risk assessment are realized, an intuitive and credible decision basis is provided, and the practicability and interpretability of a detection result are remarkably improved.