46 results about "Hardware trojan horse" patented technology

The embodiment of the invention provides a structural information and semantic information fused hardware Trojan horse detection method, which can solve the technical problem of poor hardware Trojan horse detection capability. The method comprises the steps of determining a first file; the first file comprises a plurality of code files designed by a chip; establishing an abstract syntax tree based on the first file; extracting node features and node adjacency relations according to the abstract syntax tree; obtaining structure information based on the node features and the node adjacency relation; based on the multiple code files, code semantic features are obtained; based on a cross attention mechanism, fusing the structure information and the code semantic features to obtain a target feature vector; training a hardware Trojan horse detection model based on the target feature vector; and inputting the to-be-detected code into the hardware Trojan horse detection model to obtain a hardware Trojan horse detection result. In this way, suspicious signals or statements do not need to be manually processed and analyzed, the automation degree is improved, and therefore the hardware Trojan horse detection capacity is improved.

The invention discloses an FPGA (Field Programmable Gate Array) netlist-level hardware Trojan horse detection method based on a large language model, and relates to the technical field of integrated circuit safety and hardware Trojan horse detection, and the method comprises the following steps: constructing an original FPGA netlist into a text attribute graph containing textualized attributes, generating a path text sequence through bidirectional random walk, and carrying out two-way random walk on the path text sequence; constructing a corpus to pre-train a large language model; then, delimiting a local neighborhood by taking each node as a center, generating a path text set, extracting semantic vector representation of the path text set by utilizing a pre-training model, and further constructing a node-level training sample set; on the basis, supervised fine tuning is carried out by combining a classifier and CB-Focal Loss, and a final model is obtained; in the reasoning stage, representation construction and discrimination are carried out on nodes to be detected, and node-level hardware Trojan horse detection is achieved. According to the method, circuit topology and semantic information can be reserved at the same time, node-level hardware Trojan positioning is achieved, the detection precision and generalization ability are improved, and the automation degree is improved.

The invention discloses a hardware Trojan horse detection and positioning method based on a graph convolutional neural network, and the method comprises the steps: converting a circuit structure into a graph structure based on a graph learning method, and extracting the basic structure features of nodes in the process; constructing two new features Cov and Lfp based on a deep search strategy and a topological logic analysis method to perfect feature information of circuit nodes; aggregating neighbor features of the nodes based on the GCN and updating self node feature information to improve local sensing and generalization ability of the nodes; using a global feature fusion method based on an attention mechanism to extract and update global features of the graph, and fusing the global features with the node feature vectors after the neighbor features are aggregated; balancing training data based on a stochastic gradient descent thought in combination with a small-batch oversampling and undersampling method; and using a multi-layer perceptron model to train the balanced data based on a leave-one cross validation method, predicting an unknown circuit, and identifying potential HTs nodes in the circuit. According to the invention, HTs detection and positioning are realized.

The invention discloses a hardware Trojan defense method based on the game theory, and relates to the technical field of integrated circuit safety. The method comprises the following steps: S1, defining participants and a strategy space; s2, establishing a hardware Trojan attack and defense income model; s3, calculating an attack and defense payment matrix; s4, constructing a non-cooperative finite dynamic game model; and S5, determining an optimal defense strategy. According to the method, by simulating strategy selection and income calculation of an attacker and a defender, the attacker and the defender are enabled to confront in multiple rounds in combination with mixed strategy game, optimal response dynamic and strategy probability updating, the strategy can be adjusted in each round, adjustment is performed according to the result of the previous round, the evolution and optimal solution of the strategy are studied, and the optimal solution of the strategy is researched. And whether a stable strategy combination or periodic change exists in long-term confrontation is researched, so that a final optimal defense strategy is determined according to the stable strategy combination or a single strategy.

The invention discloses a sensor hardware Trojan horse detection method and system based on image processing, and belongs to the field of sensor anomaly detection. The method comprises the following steps: acquiring sensor circuit images containing different types and manufacturing processes and containing implanted and non-implanted Trojan horses and corresponding original design files, and introducing quality defects into part of the images; registering images and files, marking Trojan horse areas to construct a first training sample set, and cutting different types of interested areas to construct a second training sample set; the two sample sets are used for training a target recognition model for recognizing a Trojan horse area and a detection model for judging whether the interested area contains image quality defects or not, and finally, the two models are combined, an image restoration technology is introduced, and whether Trojan horses exist in a circuit image of a to-be-detected sensor sample or not is judged. The method can accurately identify the malicious circuit of the sensor, reduces the false alarm through image evaluation and feature extraction, improves the efficiency through automatic detection, guarantees the safety of the sensor, and is suitable for various circuit Trojan horses.

A method for detecting a hardware Trojan horse performed by a processor on hardware may be provided. The method for detecting a hardware Trojan horse includes the steps of: collecting an electromagnetic signal radiated from the hardware; converting the electromagnetic signal into frequency spectrum data; selecting frequency spectrum data of a first frequency band based on the operating frequency of the hardware from the entire frequency band of the frequency spectrum data; extracting a plurality of first feature values ​​from the frequency spectrum data of the selected first frequency band; and comparing an outlier score output from a classification model that takes the plurality of first feature values ​​as input with a set threshold to classify the hardware as normal hardware or abnormal hardware with a hardware Trojan horse inserted.

The invention discloses a hardware Trojan horse design method based on an RISC-V architecture processor branch predictor, and relates to the field of processors and hardware Trojan horses. The hardware Trojan horse designed by the invention is divided into three parts: an interference triggering module, an interference signal generator and a control signal generator, and can implement hidden attack on a branch predictor in a processor. The hardware Trojan is based on a condition triggering mechanism, and allows an attacker to set a specific triggering condition according to the actual operation state and environment of the system, so that the interference behavior is accurately controlled. When the interference triggering module detects a predefined triggering instruction, the interference signal generator generates a specific interference signal and injects the specific interference signal into the branch predictor, so that normal work of the branch predictor is interfered, and the performance of the processor is reduced. Aiming at the working principle of the branch predictor, a targeted interference mode and a non-targeted interference mode are designed and can be flexibly selected according to requirements. The purposeless interference mode comprises a random interference mode and a branch historical interference mode, and disordered interference is carried out on a processor branch prediction mechanism. The purposeful interference mode directly interferes the normal operation process of the processor by modifying the content of the branch target buffer in a targeted manner. The hardware Trojan can effectively interfere the normal operation of the branch predictor, so that the overall performance of the processor is remarkably reduced.

The invention discloses a performance evaluation method and device for a hardware Trojan detection algorithm, equipment and a medium, and relates to the technical field of information security, and the method comprises the steps: controlling a hardware Trojan simulation circuit to generate a first pseudo-random sequence according to a random number seed issued by an upper computer; comparing the first pseudo-random sequence with a second pseudo-random sequence issued by an upper computer to obtain a sequence comparison result; if it is judged that the hardware Trojan simulation circuit meets the preset activation condition according to the sequence comparison result, an encryption protection removal circuit in the hardware Trojan simulation circuit is enabled to replace a side channel protection design circuit in the encryption circuit to operate; performing hardware Trojan detection on the to-be-detected circuit by using the hardware Trojan detection algorithm to obtain a detection result, and performing performance evaluation on the hardware Trojan detection algorithm based on the detection result; wherein the circuit to be detected is a coupling circuit of the encryption circuit and the hardware Trojan simulation circuit. And the performance of the hardware Trojan horse detection algorithm can be evaluated more reliably.

The present invention discloses a method and system for constructing a deep-level characterization model of hardware Trojans and extracting features; it relates to the field of Trojan model construction and extraction technology, including collecting hardware Trojans and normal hardware data, performing data cleaning, eliminating outliers and normalization based on statistical analysis, minimum-maximum normalization, constructing a characterization model based on a deep learning algorithm, a convolutional or recurrent neural network, a multi-layer structure and a pooling operation, training with training data, introducing regularization term optimization, inputting the data to be detected into the trained model, and judging whether a Trojan exists and its type through a threshold and a rule set. The present invention combines deep learning automatic learning features, optimizes training, reduces dimensionality and improves efficiency, and visualizes results to improve the accuracy, efficiency and reliability of hardware Trojan detection and ensure system security.

The application discloses a hardware design security vulnerability qualitative analysis method and system, according to a mixed attribute label propagation logic element library and a mixed attribute model construction method based on discrete mapping, so that a corresponding mixed attribute model can be constructed for any HDL design in linear time; the label designed by the mixed attribute model integrates two types of attributes, so that the safety behavior related to the safety attribute and the clock attribute can be modeled simultaneously; the method provided by the application can realize effective discrimination of hardware Trojan horses and hardware time measurement channels by verifying the clock attribute and the safety attribute; the application is deployed in the design and verification stage of the EDA process, so that the HDL design security vulnerability can be detected early, and the design basis is provided for high-reliability hardware design.

The invention provides a hardware Trojan horse detection method and system based on LLM and RTL semantic compression. The method comprises the steps that a to-be-detected modular RTL design circuit containing coarse-grained hardware Trojan horses is prepared; an AST is generated by using PyVerilog and is stored; establishing a tree topology structure according to the instance circuit, and recording depth information; extracting port name and bit width information for each instance circuit; extracting an assignment logic occurrence frequency for each instance circuit; extracting a judgment condition occurrence frequency for each instance circuit; establishing feature similarity between instance circuits by using a cosine similarity algorithm; constructing a modular design current feature set, and preparing an LLM input prediction; proper cue words are designed, and cue word fine adjustment is carried out on the mainstream large model; and obtaining an output result, and carrying out statistical calculation according to the to-be-tested index. The technical problems that static analysis is restricted by code complexity and abstraction levels, and dynamic analysis is easily influenced by insufficient verification scenes are solved.

The application discloses a time-triggered Ethernet switch security test system, which is used for testing RTL design of a time-triggered Ethernet switch, taking RTL design code as platform input, converting the circuit design into a netlist based on a synthesis tool, and further converting the netlist into a model with a security attribute label by using a corresponding model library; meanwhile, according to the security requirement of the time-triggered Ethernet switch, the security attribute to be detected is determined, and the security attribute is mapped into the model by using a formal language. After the model is processed, the verification is carried out by a detection tool, and if a failure result is found, it is indicated that there may exist defects and vulnerabilities. The application is used for security evaluation in the design stage of the time-triggered Ethernet switch, and is used for detecting whether there exist security vulnerabilities and malicious modules in the time-triggered Ethernet switch, verifying whether there exist hardware Trojan horses and the like in third-party IP used in the time-triggered Ethernet switch, and verifying whether the syntax in a self-defined module is standard and whether there exist security vulnerabilities.

The invention discloses a hardware Trojan horse data set labeling method and system, and relates to the technical field of data labeling, and the method comprises the steps: carrying out the high-frequency extraction of an optimized integrated circuit chip image data set generated through the preprocessing of a low-quality integrated circuit chip image data set, and determining a high-frequency texture matrix; carrying out iterative solution on the subspace learning objective function related to the optimized integrated circuit chip image data set by adopting an alternating direction multiplier method based on the optimized integrated circuit chip image data set and the high-frequency texture matrix, and determining a frequency domain low-rank subspace matrix and a space domain low-rank subspace matrix; outputting fusion features based on a frequency domain adjacent matrix corresponding to the frequency domain low-rank subspace matrix and a spatial domain adjacent matrix corresponding to the spatial domain low-rank subspace matrix through the trained graph neural network; and carrying out spectral clustering by adopting the fusion features, and determining a labeled integrated circuit chip image data set. Noise of a low-quality integrated circuit chip image data set can be effectively suppressed, and the data set marking correctness can be improved.

The present invention discloses a method and device for measuring the concealment of hardware Trojans based on control difficulty analysis. The method comprises the following steps: step S01. parsing the logic gate circuits in the gate-level netlist under test; step S02. determining whether the clock signal is abnormal; step S03. determining the type of each logic gate circuit; if it is a combinational logic gate circuit, calculating the control difficulty values ​​C0 and C1 of the corresponding combinational logic gate circuit according to the type of the logic gate; if it is a sequential logic gate circuit, calculating the control difficulty values ​​C0 and C1 of the sequential logic circuit according to whether the clock signal is abnormal; step S04. calculating the corresponding concealment value based on the C0 and C1 control difficulty values ​​of each logic gate circuit to evaluate the concealment degree of each logic gate circuit. The present invention can eliminate the dependence on test stimuli and suppress the influence of hardware Trojan morphology and clock signals on concealment measurement.

The hardware Trojan detection method and system based on low activity and low observation node joint analysis belong to the technical field of integrated circuit security, and solve the problem of how to improve the accuracy of identifying high-concealment hardware Trojan; the gate-level netlist is abstracted into a signal propagation directed graph, the nodes in the low activity candidate trigger node set are taken as the starting nodes, the nodes in the low observation candidate load node set are taken as the target nodes, the effective signal propagation path from the starting node to the target node is searched in the directed graph, and if the effective signal propagation path exists, it is determined as a high-risk hardware Trojan potential link; the application proposes a method for identifying high-concealment hardware Trojan potential signal link based on gate-level netlist static analysis, which does not depend on the golden reference model, and does not need to know the Trojan feature library, and is especially suitable for third-party IP core access security detection, backdoor review and logic credibility verification scenes.

A hardware trojan detection method is provided including an input and output updating step of updating input and output values of all logic cells by performing computations according to logical expressions of all logic cells included in a netlist to be verified and a detection step of performing hardware trojan detection based on a comparison result of the updated input and output values and a threshold.

The application provides a multi-dimensional layered hardware Trojan evaluation method for an IP soft core, constructs a Trojan multi-dimensional feature library, performs function integrity analysis to identify a first module in which a Trojan may exist, obtains equivalent RTL level code for a module in which no anomaly is found, takes each module of the RTL level code as a node and takes the calling relationship between each module as a weight to establish an information flow graph, compares the information flow graph with the Trojan multi-dimensional feature library to obtain a second module in which a Trojan may exist, analyzes the information flow graph, and takes a module in which the calling is less than a set threshold, a module with an isolated node and a module adjacent to the isolated node in the information flow graph as a third module in which a Trojan may exist, analyzes the first module, the second module and the third module, calculates code coverage, signal flip rate, signal and clock delay anomaly, power consumption anomaly and layout blocking anomaly, and comprehensively evaluates to locate a module in which a Trojan exists in the to-be-detected IP soft core.

The present invention relates to an RTL-level hardware Trojan detection method based on subgraph isomorphism, belonging to the technical field of RTL-level hardware security analysis. The RTL-level hardware Trojan detection method based on subgraph isomorphism provided by the present invention optimizes the subgraph isomorphism algorithm by adding constraint and pruning conditions, quickly and accurately determines the location of the Trojan at a low cost, and gives the confidence level and graphical representation of the detection result, without relying on a reference model, which is convenient for use and popularization.

A kind of hardware Trojan detection and positioning method based on graph convolutional neural network, based on graph learning method, circuit structure is converted into graph structure, and the basic structure features of node are extracted in this process;Based on the construction of two new features Cov and Lfp with depth search strategy and topological logic analysis method to improve the feature information of circuit node;Based on the neighbor feature of GCN aggregation node and update its own node feature information to improve the local perception and generalization ability of node;Using the global feature fusion method based on attention mechanism to extract and update the global feature of graph, and fuse with the node feature vector after aggregating neighbor feature;Based on the idea of stochastic gradient descent and combined with small batch over-sampling and under-sampling method to balance training data;Using multilayer perception machine model to train balanced data based on leave-one-out cross-validation method, and predicting unknown circuit, identifying potential HTs node in circuit.The present application realizes the detection and positioning of HTs.

The application discloses a GPU delay type hardware Trojan design method for NVLink interconnection triggering, belongs to the field of integrated circuit security, and is suitable for a multi-GPU system adopting an NVLink high-speed interconnection. The method implants a hardware Trojan into an NVLink control circuit of a host GPU, collects and counts traffic features of multiple NVLink ports within a preset time window, and judges whether a triggering condition is met based on correlation measurement values between the ports. When the correlation measurement values exceed a preset threshold, delay control is preferentially exerted on control type transactions, atomic transactions and other time delay sensitive transactions in a target port. The application adopts a random bit sequence mapping mode to generate delay strength, and randomly implements non-uniform communication delay without analyzing communication content, so that communication time delay in a multi-GPU cooperative calculation process is increased and overall execution efficiency of the system is reduced.

The application discloses a gate-level netlist hardware Trojan test set generation method based on a large language model, and relates to the field of hardware security. The method firstly uses a carefully designed prompt word to make the large language model provide a hardware Trojan design service; then the large language model generates final design code after continuously iterating and reflecting according to the provided knowledge base and restriction constraints; the design code is evaluated by an evaluator, and the Trojan can be mounted on the parent netlist; the triggering node is determined by analyzing the node concealment, and finally the netlist file after mounting the Trojan is generated.

A method for online monitoring and tracing of hardware Trojans implanted in AI accelerators based on heterogeneous side-channel perception is proposed. This method collaboratively schedules heterogeneous native monitoring resources on FPGAs to capture multi-dimensional side-channel feature fingerprints in situ. It utilizes deep neural networks for spatiotemporal joint modeling and behavior reconstruction, and integrates adaptive compensation strategies to resist thermal drift interference. This enables autonomous monitoring of hardware Trojan behavior and precise physical region tracing within the AI ​​accelerator. This method significantly improves the robustness of hardware Trojan detection under complex conditions without requiring external audit intervention or significantly impacting accelerator inference performance. It also demonstrates good detection generalization ability for various unknown triggering mechanisms, providing a key technical path for the security assessment and risk hardening of convolutional neural network accelerators.

The application belongs to the technical field of integrated circuit hardware security, and discloses a hardware Trojan detection method based on machine learning and mixed sampling. First, the interconnection structure of all gates in the netlist is matched through the inducted low-flip-rate structure; all gates in the netlist are mixed sampled, if the gate does not belong to the low-flip-rate structure, the n-level circuit around the gate is searched and a subgraph is established; if the gate belongs to the low-flip-rate structure, the logic cone where the gate is located is wholly sampled; all connection structures in the feature subgraph are one-hot code encoded, and then accumulated to obtain a fixed-length feature vector; finally, all feature vectors are input to the trained machine learning classifier for node classification, and the hardware Trojan node is detected. The application retains part of the high-dimensional features of the graph, and adopts the mixed sampling mode to expand the feature difference between the hardware Trojan and the normal node, so that the machine learning model can better train and distinguish the hardware Trojan and the normal node, and the detection precision of the detection model is improved.

The invention discloses a hardware Trojan horse detection and recovery system based on a lightweight neural network. The hardware Trojan horse detection and recovery system comprises an RISC-V processor, a hardware Trojan horse detection device and a recovery device, the RISC-V processor comprises an instruction fetching unit, a decoding unit, an execution unit and a universal destination register group; the instruction fetching unit, the decoding unit and the execution unit form a three-level pipeline architecture; the hardware Trojan horse detection device is used for recording an execution path and a time sequence characteristic of each RISC-V instruction on the RISC-V processor, and performing hardware Trojan horse detection on the corresponding execution path by utilizing a constructed lightweight neural network based on the time sequence characteristic; and the recovery device is used for backing up the storage information of the general destination register group in real time and recovering the RISC-V processor to a normal state when the hardware Trojan is detected. The hardware Trojan horse detection and recovery system provided by the invention is higher in reliability and flexibility, higher in speed and lower in power consumption.

A sensing circuit for detecting hardware trojans in a target integrated circuit is provided. The sensing circuit includes an array of magnetic tunnel junction circuits where each magnetic tunnel junction circuit including one or more magnetic tunnel junctions. Characteristically, each magnetic tunnel junction circuit configured to provide data for and / or determine a temperature map or a current map of the target integrated circuit.

A hardware Trojan horse detection method based on circuit netlist characteristics belongs to the field of integrated circuit hardware security detection, solves the problem of how to improve the accuracy of hardware Trojan horse detection, and comprises the following steps: abstracting examples, a main input port and a main output port into nodes for processing, and abstracting wire type variables directly connected with the examples, the input port and the output port into directed edges for processing; after being abstracted, the netlist is regarded as a topological structure in which nodes are directly connected with one another, and each node feature comprises a directed edge taking the node as an initial node, a directed edge taking the node as an end point and a module type corresponding to the node; nine structural features including node fan-in and fan-out, the number of inverters before and after the node, the number of multiplexers, the number of triggers, the number of layers from the node to the main input and the main output, and the distance from the node to a key link are established; and higher distinguishing accuracy is achieved by using fewer feature types, and when different types of circuit nodes are distinguished, hardware Trojan horse node distinguishing can be flexibly adjusted to train a classifier data set.

The invention provides a reinforcement learning hardware Trojan horse detection method for an incomplete netlist, and the method comprises the steps: extracting an incomplete netlist file, carrying out the preprocessing of the incomplete netlist file, recognizing all nodes and logic gates, and analyzing a netlist representing the connection between components, so as to extract the information of the nodes and the logic gates; repairing the incomplete netlist into a complete netlist based on a reinforcement learning prediction model; the preprocessed nodes and the logic gate set are input into a prediction model, the prediction model carries out prediction generation according to the circuit conversion probability, and a complete netlist is obtained; and obtaining a hardware Trojan detection result through the hardware Trojan detection model. According to the method, the hardware Trojan in the incomplete gate-level netlist can be effectively detected.

The application discloses a chip Trojan horse test set generation method based on vulnerability analysis, which comprises the following steps: first, a register transfer level (RTL) code of a circuit is used to obtain a chip layout result, and a chip layout information point set is obtained from the chip layout result; then, a layout space margin and a routing channel margin after chip layout wiring is completed are analyzed to obtain a chip layout vulnerability matrix; and finally, a vulnerable point in the chip layout vulnerability matrix is selected for hardware Trojan horse implantation to generate a chip layout level hidden hardware Trojan horse test set. The application analyzes physical resources such as a layout space margin and a routing channel margin of a chip layout, analyzes power consumption characteristics of the chip layout on the basis, designs a vulnerability index of the chip layout, selects a vulnerable point, and obtains a chip layout hidden by a hardware Trojan horse, namely, a chip Trojan horse test set. The application promotes the development of a hardware Trojan horse detection technology and improves the defense capability of a chip.

The invention provides an integrated circuit side channel leakage and hardware Trojan horse detection system. The system comprises an acquisition device and a terminal system. The acquisition device comprises a micro-control unit and a field programmable gate array, and the micro-control unit is used for receiving a connection signal sent by the terminal system, returning power consumption data to the terminal system and storing an acquisition program for performing power consumption data acquisition on the chip to be tested. The field programmable gate array is used for collecting the power consumption data of the to-be-tested chip according to the collection program. And the terminal system is used for sending a connection signal for connecting the to-be-tested chip to the acquisition device, receiving the power consumption data of the to-be-tested chip returned by the acquisition device and inputting the power consumption data into the power consumption model to obtain a detection result of whether the to-be-tested chip has side channel leakage or hardware Trojan horse. The power consumption data of the to-be-detected chip is directly acquired by the acquisition device, so that the terminal system can analyze the power consumption data to obtain a detection result of whether side channel leakage or hardware Trojan exists, and rapid and safe detection of the to-be-detected chip is realized.

The invention provides a hardware circuit Trojan horse detection method and system based on machine learning, and the method comprises the steps: obtaining a reference model and a target model which have the same structure, inputting a circuit diagram data set of a known label into the reference model for learning training, and recording the loss as FLr; inputting the to-be-tested circuit and the pseudo benign node and the pseudo Trojan horse node of the to-be-tested circuit into the target model for learning and training, and recording the loss as FLt; performing weighted summation on the loss FLr and the loss FLt to obtain a joint loss FLtot, and performing adjustment and optimization by using the joint loss FLtot; after the training of the target model Ht is completed, marking the adjusted and optimized target model Ht as a GTD-SR model; and inputting all nodes of the circuit Gt to be detected into the GTD-SR model for Trojan horse detection, and outputting the final probability that each node in the circuit Gt to be detected has a hardware circuit Trojan horse through the GTD-SR model. According to the method, an unknown circuit and a novel hardware Trojan horse can be directly operated on the gate-level netlist, and a logic gate infected by the Trojan horse can be accurately positioned.