11 results about "Hardware trojan horse" patented technology

The invention discloses a hardware Trojan horse design method based on an RISC-V architecture processor branch predictor, and relates to the field of processors and hardware Trojan horses. The hardware Trojan horse designed by the invention is divided into three parts: an interference triggering module, an interference signal generator and a control signal generator, and can implement hidden attack on a branch predictor in a processor. The hardware Trojan is based on a condition triggering mechanism, and allows an attacker to set a specific triggering condition according to the actual operation state and environment of the system, so that the interference behavior is accurately controlled. When the interference triggering module detects a predefined triggering instruction, the interference signal generator generates a specific interference signal and injects the specific interference signal into the branch predictor, so that normal work of the branch predictor is interfered, and the performance of the processor is reduced. Aiming at the working principle of the branch predictor, a targeted interference mode and a non-targeted interference mode are designed and can be flexibly selected according to requirements. The purposeless interference mode comprises a random interference mode and a branch historical interference mode, and disordered interference is carried out on a processor branch prediction mechanism. The purposeful interference mode directly interferes the normal operation process of the processor by modifying the content of the branch target buffer in a targeted manner. The hardware Trojan can effectively interfere the normal operation of the branch predictor, so that the overall performance of the processor is remarkably reduced.

The application discloses a hardware design security vulnerability qualitative analysis method and system, according to a mixed attribute label propagation logic element library and a mixed attribute model construction method based on discrete mapping, so that a corresponding mixed attribute model can be constructed for any HDL design in linear time; the label designed by the mixed attribute model integrates two types of attributes, so that the safety behavior related to the safety attribute and the clock attribute can be modeled simultaneously; the method provided by the application can realize effective discrimination of hardware Trojan horses and hardware time measurement channels by verifying the clock attribute and the safety attribute; the application is deployed in the design and verification stage of the EDA process, so that the HDL design security vulnerability can be detected early, and the design basis is provided for high-reliability hardware design.

The application discloses a time-triggered Ethernet switch security test system, which is used for testing RTL design of a time-triggered Ethernet switch, taking RTL design code as platform input, converting the circuit design into a netlist based on a synthesis tool, and further converting the netlist into a model with a security attribute label by using a corresponding model library; meanwhile, according to the security requirement of the time-triggered Ethernet switch, the security attribute to be detected is determined, and the security attribute is mapped into the model by using a formal language. After the model is processed, the verification is carried out by a detection tool, and if a failure result is found, it is indicated that there may exist defects and vulnerabilities. The application is used for security evaluation in the design stage of the time-triggered Ethernet switch, and is used for detecting whether there exist security vulnerabilities and malicious modules in the time-triggered Ethernet switch, verifying whether there exist hardware Trojan horses and the like in third-party IP used in the time-triggered Ethernet switch, and verifying whether the syntax in a self-defined module is standard and whether there exist security vulnerabilities.

The hardware Trojan detection method and system based on low activity and low observation node joint analysis belong to the technical field of integrated circuit security, and solve the problem of how to improve the accuracy of identifying high-concealment hardware Trojan; the gate-level netlist is abstracted into a signal propagation directed graph, the nodes in the low activity candidate trigger node set are taken as the starting nodes, the nodes in the low observation candidate load node set are taken as the target nodes, the effective signal propagation path from the starting node to the target node is searched in the directed graph, and if the effective signal propagation path exists, it is determined as a high-risk hardware Trojan potential link; the application proposes a method for identifying high-concealment hardware Trojan potential signal link based on gate-level netlist static analysis, which does not depend on the golden reference model, and does not need to know the Trojan feature library, and is especially suitable for third-party IP core access security detection, backdoor review and logic credibility verification scenes.

The application provides a multi-dimensional layered hardware Trojan evaluation method for an IP soft core, constructs a Trojan multi-dimensional feature library, performs function integrity analysis to identify a first module in which a Trojan may exist, obtains equivalent RTL level code for a module in which no anomaly is found, takes each module of the RTL level code as a node and takes the calling relationship between each module as a weight to establish an information flow graph, compares the information flow graph with the Trojan multi-dimensional feature library to obtain a second module in which a Trojan may exist, analyzes the information flow graph, and takes a module in which the calling is less than a set threshold, a module with an isolated node and a module adjacent to the isolated node in the information flow graph as a third module in which a Trojan may exist, analyzes the first module, the second module and the third module, calculates code coverage, signal flip rate, signal and clock delay anomaly, power consumption anomaly and layout blocking anomaly, and comprehensively evaluates to locate a module in which a Trojan exists in the to-be-detected IP soft core.

The application discloses a GPU delay type hardware Trojan design method for NVLink interconnection triggering, belongs to the field of integrated circuit security, and is suitable for a multi-GPU system adopting an NVLink high-speed interconnection. The method implants a hardware Trojan into an NVLink control circuit of a host GPU, collects and counts traffic features of multiple NVLink ports within a preset time window, and judges whether a triggering condition is met based on correlation measurement values between the ports. When the correlation measurement values exceed a preset threshold, delay control is preferentially exerted on control type transactions, atomic transactions and other time delay sensitive transactions in a target port. The application adopts a random bit sequence mapping mode to generate delay strength, and randomly implements non-uniform communication delay without analyzing communication content, so that communication time delay in a multi-GPU cooperative calculation process is increased and overall execution efficiency of the system is reduced.

The application discloses a gate-level netlist hardware Trojan test set generation method based on a large language model, and relates to the field of hardware security. The method firstly uses a carefully designed prompt word to make the large language model provide a hardware Trojan design service; then the large language model generates final design code after continuously iterating and reflecting according to the provided knowledge base and restriction constraints; the design code is evaluated by an evaluator, and the Trojan can be mounted on the parent netlist; the triggering node is determined by analyzing the node concealment, and finally the netlist file after mounting the Trojan is generated.

A method for online monitoring and tracing of hardware Trojans implanted in AI accelerators based on heterogeneous side-channel perception is proposed. This method collaboratively schedules heterogeneous native monitoring resources on FPGAs to capture multi-dimensional side-channel feature fingerprints in situ. It utilizes deep neural networks for spatiotemporal joint modeling and behavior reconstruction, and integrates adaptive compensation strategies to resist thermal drift interference. This enables autonomous monitoring of hardware Trojan behavior and precise physical region tracing within the AI ​​accelerator. This method significantly improves the robustness of hardware Trojan detection under complex conditions without requiring external audit intervention or significantly impacting accelerator inference performance. It also demonstrates good detection generalization ability for various unknown triggering mechanisms, providing a key technical path for the security assessment and risk hardening of convolutional neural network accelerators.

The invention provides a hardware circuit Trojan horse detection method and system based on machine learning, and the method comprises the steps: obtaining a reference model and a target model which have the same structure, inputting a circuit diagram data set of a known label into the reference model for learning training, and recording the loss as FLr; inputting the to-be-tested circuit and the pseudo benign node and the pseudo Trojan horse node of the to-be-tested circuit into the target model for learning and training, and recording the loss as FLt; performing weighted summation on the loss FLr and the loss FLt to obtain a joint loss FLtot, and performing adjustment and optimization by using the joint loss FLtot; after the training of the target model Ht is completed, marking the adjusted and optimized target model Ht as a GTD-SR model; and inputting all nodes of the circuit Gt to be detected into the GTD-SR model for Trojan horse detection, and outputting the final probability that each node in the circuit Gt to be detected has a hardware circuit Trojan horse through the GTD-SR model. According to the method, an unknown circuit and a novel hardware Trojan horse can be directly operated on the gate-level netlist, and a logic gate infected by the Trojan horse can be accurately positioned.

The application provides a circuit gate-level feature hardware Trojan detection method based on a pre-trained NLP model. The Verilog file of the gate-level netlist is preprocessed, only the gate and its connection relationship are retained, and the description form of the netlist is naturalized, so that it is suitable for NLP model processing. Then the extracted text information is represented in a vector form, so that it is compatible with the Transformer structure. Finally, the self-attention mechanism in the Transformer structure is used to capture the complex relationship of the circuit components and their connections, and the detection of the hardware Trojan is realized. This method can make full use of the knowledge learned in the natural language processing task, effectively migrate to the hardware Trojan detection task, and realize efficient and accurate hardware Trojan detection.

This invention relates to a hardware Trojan side-channel detection method based on an autoencoder, belonging to the field of network security side-channel analysis technology, specifically a side-channel detection method for artificial intelligence hardware Trojans based on an autoencoder. The method of this invention is easy to implement, the normal data used for training is easy to collect, and the autoencoder method has relatively low computational cost, making it suitable for application in practical scenarios. This method uses side-channel information as input to the autoencoder and performs anomaly detection based on the encoding results obtained by the encoder, providing intuitive and accurate results.