Hardware trojan horse detection method based on waveform superposition

A hardware Trojan detection and hardware Trojan technology, applied in the direction of internal/peripheral computer component protection, etc., can solve the problems of high hardware Trojan detection cost, high implementation cost, and low detection efficiency, so as to reduce detection cost, improve recognition efficiency, and operate easy effect

Active Publication Date: 2015-11-11
NAT UNIV OF DEFENSE TECH
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Problems solved by technology

However, these methods usually have high implementation cost and heavy workload (such as reverse dissection analysis, etc.), which makes hardware Trojan detection cost relatively high and detection efficiency low

Method used

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  • Hardware trojan horse detection method based on waveform superposition
  • Hardware trojan horse detection method based on waveform superposition
  • Hardware trojan horse detection method based on waveform superposition

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Embodiment Construction

[0033] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0034] Such as figure 1 Shown, the hardware Trojan detection method based on waveform superposition of the present invention, its steps are:

[0035] S1: Obtain a clean chip as a reference;

[0036] That is, a clean chip (Golden chip) that does not contain hardware Trojan horse circuits can be obtained as a reference through the method of reverse dissection;

[0037] S2: Extract several chips from another batch as chips to be tested;

[0038] Since the chips in the same batch have the same security status, that is, all contain hardware Trojan horse circuits or are all normal chips, and there are process deviations between chips in different batches, in order to avoid process deviations from affecting the final judgment of whether the chip is safe or not, another Randomly select n chips from the batch of chips as the chips to be tes...

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Abstract

A hardware trojan horse detection method based on waveform superposition comprises the steps of: S1: acquiring a clean chip as reference; S2: extracting a plurality of chips from the other batch as to-be-detected chips; S3: acquiring power consumption data of the clean chip and the to-be-detected chips; S4: subtracting the power consumption data of the clean chip by the power consumption data of the to-be-detected chips respectively; S5: carrying out superposition processing on waveforms of the power consumption data obtained by the subtraction in the step S4; and S6: making a judgment according to a processing result obtained in the step S5, if a power consumption feature in a period is effectively clear after the superposition and the power consumption exceeds a preset threshold value, determining that a hardware trojan horse circuit possibly exists in the to-be-detected chips, and conversely, determining that the to-be-detected chips are normal. The hardware trojan horse detection method based on the waveform superposition has the advantages of simple principle, simplicity and convenience for operation, high detection efficiency, low detection cost and the like.

Description

technical field [0001] The invention mainly relates to the field of chip safety detection, in particular to a detection method for hardware Trojans based on waveform superposition. Background technique [0002] Hardware Trojan (hardware trojan) refers to an unscrupulous circuit that maliciously tampers with the underlying hardware of the chip. Hardware Trojan horse circuits are usually small in scale and have the characteristics of strong concealment, great destructive power, high design and implementation requirements, and difficult protection and detection. The implantation methods of hardware Trojans are flexible and changeable. They can be implanted in the design stage of the chip, or in the manufacturing stage of the chip. It can be implanted by kernel or EDA tools, and it can also be implanted by untrusted manufacturers. Once the hardware Trojan is triggered, it will cause security threats such as data leakage, function disruption, and even system crash, which will e...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F21/76
CPCG06F21/76
Inventor 陈吉华吴志凯李晓卫史玉博马卓张明乐大珩何小威隋强
Owner NAT UNIV OF DEFENSE TECH
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