49 results about "Logic testing" patented technology

The invention provides a database logic test method and device.The method comprises the steps that a target test request is received, a test case file of the target test request is obtained, the test case file comprises test cases of multiple SQL execution engines, and the test cases comprise meta-test instructions and SQL statements; based on the meta-test instruction of the test case, various SQL execution engines are applied to execute SQL statements in the test case matched with the SQL execution engines respectively, and database logic testing is completed; the test cases matched with the SQL execution engine comprise the test case which is corresponding to the meta test instruction, skips the specified SQL execution engine and is the same as the SQL execution engine, and the test cases except the test cases which are corresponding to the specified SQL execution engine and are different from the SQL execution engine, so that the database logic test compatible with various SQL execution engines can be realized; and the reliability of database logic testing is improved.

The invention discloses a logic protection module detection method and device, a program product and electronic equipment. The method comprises the following steps: determining a first test process based on the model and the component version of a to-be-tested module, and determining a second test process based on the logic version of the to-be-tested module; the method comprises the following steps: performing function test on X channels of a to-be-tested module according to a first test process through a first circuit to obtain a first test result, and performing logic test and pulse width test on the to-be-tested module according to a second test process through a second circuit to obtain a second test result, and determining a detection result of the to-be-tested module based on the first test result and the second test result. The technical problem that when the logic protection module is detected based on the prior art, a logic operation part in the logic protection module needs to be skipped, and an output channel of the logic protection module is directly controlled, so that the detection accuracy is low is solved.

The invention provides an intelligent fault processing FA logic test device and method, the intelligent fault processing FA logic test device comprises a master control MCU, three feeder terminals, a relay protection instrument and a connection circuit, the master control MCU simulates two-way section switches and one-way interconnection switch in a three-section three-interconnection line by using software, the three feeder terminals are accessed at the same time, the feeder terminals control the master control MCU through control signals, and the relay protection instrument is connected with the master control MCU. And the intelligent fault processing FA logic is tested by simulating the on and off states of the switch and recording the moments of voltage, no voltage and switch displacement. The device can simulate all switches participating in FA logic on a real 10kV three-section three-tie line, can simulate a time-delay opening and closing working scene of a field switch, provides multiple feedback points, and provides good support for field installation test work of a feeder terminal carrying an intelligent fault processing FA.

Run-time logic built-in self-test (LBIST) may be performed, while ensuring operational continuity. The compute elements in a machine learning accelerator contain LBIST circuitry that performs logic testing of the functional circuitry in the compute element. The LBIST circuitry may be self-sufficient, meaning that it contains the data and instructions needed to run and evaluate these tests. An LBIST manager enables the logic testing during idle time of the functional circuitry between blocks of statically scheduled instructions. As a result, the LBIST circuitry can perform the logic tests without disrupting the computation of the machine learning network.

The invention provides a function logic test case generation method, a test method and a device, and the method comprises the steps: automatically generating a directed conversion diagram containing the conversion relation between different hardware power states, and a test matrix containing the specific information of each software logic function through analyzing a demand document of the device; in the process of generating parameter difference information, hardware power supply states and software logic functions are tightly coupled, all possible state conversion paths are traversed through a directed conversion diagram, and functional parameter changes under different hardware power supply states and software logic functions are automatically identified. Therefore, basic test cases corresponding to different functions in each power supply state can be generated; on the basis, boundary parameters and a conversion relation are further adjusted, and a boundary test case and an abnormal test case are generated, so that the test case capable of realizing full-scene coverage is automatically generated, and high-coverage-rate efficient full-automatic test is conveniently carried out on functional logic of the equipment in a multi-power-supply state.

The invention relates to the technical field of semiconductor testing, and discloses a memory chip FT testing method based on probe contact. The method comprises the following steps: acquiring wafer-level process parameters, layout and wiring topology and historical yield data of a chip; dividing a logic test block; calculating the defect probability score of each block and sorting to generate a test sequence; executing full-function testing in sequence, collecting response signal characteristics in real time, comparing the response signal characteristics with the health reference model, and dynamically triggering proximity extension testing or failure judgment; the test result feedback is used for updating the yield data. Through a risk-oriented adaptive test strategy, the test time is shortened and the test cost is reduced while the defect coverage rate is guaranteed.

The application provides a multifunctional test point allocation method and system based on an adaptive switch matrix, relates to the technical field of electronic testing, and realizes dynamic connection of physical probes and logical test points by acquiring integrated circuit topology information to construct a switch matrix; the same probe is allocated to different test points in different time periods by using time division multiplexing technology, test response signals are collected and deviation values are calculated; a fault point is determined based on the deviation, the influence degree of the fault point on surrounding nodes is analyzed, and a test priority level is obtained; the test timing is dynamically adjusted according to the priority level, high-priority nodes are preferentially tested, the switch state is controlled to realize intelligent allocation of test resources, and the test efficiency and fault coverage are improved.

According to the system-level FPGA software testing method, device and equipment and the readable storage medium, the provided testing method is a digital simulation environment, physical equipment of a designer is not needed, and the cost is low; a system-level simulation test platform is built by adopting a modular idea, and the test method is clear in architecture, convenient and flexible to use and convenient to reuse in other system-level FPGA software tests, so that the efficiency of whole test verification is improved; an external interface of system-level FPGA software is subjected to modularization processing, a working interface is clearly divided, multi-person collaborative testing is facilitated, and the testing efficiency is improved; the testing method is in a digital simulation environment, any numerical value in system-level FPGA software can be checked, indexes (such as performance, delay and other time indexes) which cannot be tested due to physical limitation in a real object test are accurately measured, and therefore testing sufficiency is improved; the coverage rate of any statement can be checked in a digital simulation environment, all logic tests are realized, and the problem that full logic tests cannot be performed in physical tests is solved.

The present disclosure designs the technical field of data processing, and specifically discloses a business logic testing method and device, computer equipment, a storage medium and a computer program product. The method comprises: acquiring business test template data corresponding to a business test scene; determining a scene expected result of the business test scene according to the business test scene; generating business test data of the business test scene based on the business test scene, the scene expected result and the business test template data; and testing the business logic of the business test scene according to the business test data to obtain a business logic test result of the business test scene. The method can effectively improve the test efficiency of the business logic test and enhance the reliability of the operation of the business system.

This invention relates to a testing device for individual modules of a locomotive air piping system, comprising a cabinet, a pressure testing mechanism and an electrical testing mechanism disposed inside the cabinet, and a test bench disposed outside the cabinet for placing the module under test. The pressure testing mechanism includes an air supply pipeline and multiple testing pipelines, and is used to perform airtightness testing on the module under test. The electrical testing mechanism includes a control unit and a drive unit, and is used to perform electrical logic testing on the module under test. An industrial control computer is connected to the electrical testing mechanism and the pressure testing mechanism, and the industrial control computer is used to generate and edit testing instructions. This invention can adapt to various independent module models, performing automatic testing on their airtightness, circuit and air circuit logic, pressure switches, and electric gates, and can also perform manual testing.

The application relates to the technical field of semiconductor testing, and discloses a memory chip FT test method based on probe contact. The method comprises the following steps: acquiring wafer-level process parameters, layout and wiring topology and historical yield data of a chip; dividing a logic test block; calculating defect probability scores of each block and sorting to generate a test sequence; performing full-function testing in sequence, collecting response signal features in real time and comparing the response signal features with a health benchmark model, and dynamically triggering adjacent expansion testing or failure determination; and feeding back test results to update yield data. The application shortens the test time and reduces the test cost while guaranteeing the defect coverage rate through a risk-oriented adaptive test strategy.

The invention discloses a cabin environment control system test platform which can be used for realizing functions and dynamic performance test verification of a cabin environment control system, and the specific functions comprise sensor interface test; testing software and hardware function logic of the test product; bus transmission function testing and the like. The test platform is composed of a test board and a test resource cabinet. Wherein the test board consists of an industrial personal computer and a display screen, and is mainly used for human-computer interaction of model construction and system testing; the test resource cabinet is composed of a power box, a real-time simulation machine, a signal conditioning box, an interface box and an environmental control real object panel, and is used for carrying out analogue simulation and signal conditioning on characteristic signals of a test product. And application function test of a test product, bus transmission function test, sensor interface correctness test, sensor precision test and the like are realized.

The invention belongs to the technical field of software testing, and provides a defect retrieval method and system for software development testing, which comprises the following steps: aiming at the problem of integrated logic test missing caused by overuse of a Mock object in a recognition unit test, and combining code coverage rate analysis and a Mock object optimization strategy to obtain a defect retrieval result; software defects caused by excessive Mock are accurately positioned and retrieved, the limited number of Mock objects in the unit test cases is determined according to the coverage rate of integrated logic codes during replacement of the Mock objects, unqualified unit test cases are identified in the unit test cases according to the limited number of the Mock objects, and necessity analysis is performed on the Mock objects in the unqualified unit test cases, so that the unit test cases are identified. By quantitatively evaluating the necessity of the Mock object, determining the reasonable use threshold and optimizing the test case, the integrity of the integrated logic test is effectively improved, the production environment defects caused by test distortion are reduced, and the software quality and stability are improved.

Semiconductor devices having design for test interfaces are provided. The semiconductor devices can be tested in a manufacturing environment as either a die or a packaged die. The design for test interface comprises a physical layer having transmitter, receiver, and a common lane. The design for test interface also comprises test port interface logic that can interface with the semiconductor device logic. Test port interface logic can include 1:N de-serializer logic, 1:N CLK divider logic, and N:1 serializer logic.

The present invention discloses a method for testing the launch control logic of a universal suspension, comprising: constructing a simulated launch scenario for the suspension, and establishing a dynamic random environmental excitation model within the simulated launch scenario; utilizing the dynamic random environmental excitation model to apply different types of environmental excitations to the simulated launch scenario, simulating the launch of the suspension under the environmental excitation conditions; constructing an excitation signal vector during the launch process of the suspension, driving the suspension model into a launch state, and constructing an ideal state model of the suspension during the launch process; outputting the ideal state vector during the launch process of the suspension, constructing a control logic decision model during the launch control test of the suspension, and evaluating the logic control accuracy during the launch control process. The present invention analyzes and processes environmental excitation data within a target area, using this data as a basis for applying environmental excitations to the simulated launch scenario during the test. The simulated test results can truly reflect the target scenario, improving the reliability of the test.

The invention provides a fire-fighting linkage logic verification method and system based on analog simulation, and the method comprises the steps: obtaining and analyzing a fire-fighting host engineering file selected by a user, obtaining the basic information of a host, a linkage rule, an equipment point table and other information, and in a simulation test interface, based on the host selected by the user and a test mode, verifying the fire-fighting linkage logic. And performing equipment linkage operation according to the linkage logic rule, generating an operation result containing the target output equipment and a linkage instruction, executing the linkage instruction to simulate a real action response of the target output equipment, and displaying a linkage execution result in real time. According to the method, the fire-fighting linkage logic test can be completely carried out in the virtual and simulation environments without actual operation of field entity equipment, the test period is greatly shortened, the test efficiency is improved, the test process is completely carried out in the virtual simulation environment, equipment false triggering and operation in a high-risk environment are avoided, potential safety hazards of field test are eliminated, and the test efficiency is improved. And the equipment loss and the maintenance cost are reduced without depending on field equipment.

The calibration method and the test equipment for the detection chip provided by the embodiments of the present disclosure comprise the following steps: controlling a target detection chip to continuously generate a trigger signal according to a preset rule; and controlling the target detection chip to output a logic test signal until the logic test signal flips between a high level and a low level; determining the value of the trigger signal; calibrating the target detection chip by using a calibration algorithm according to the determined value of the trigger signal; wherein an internal calibration circuit is configured to provide a calibration channel between the detection chip and a sampling element in the internal calibration circuit; and the internal calibration circuit is configured to establish a target calibration channel according to a control instruction. The embodiments of the present disclosure adopt a linear search method to find the value of the trigger signal, and then calibrate the level comparator of the detection chip by using a preset calibration algorithm according to the value of the trigger signal. Thus, the problem that the level comparator cannot be calibrated in the related art is solved. The integration of the ATE equipment is improved, and the dependence on external equipment is reduced.

The present invention relates to a distribution terminal testing method using an IEC61850 extended FT3 data frame injection method, comprising: scanning a code to collect nameplate parameters of the distribution terminal and automatically generating a test plan; after both parties establish a link, automatically accessing an algorithm database to drive a device to output an extended FT3 data frame to simulate various types of short-circuit faults, ground faults, circuit breakers, load switches, etc.; simultaneously, a remote simulation master station unit is used to implement data interaction with the distribution terminal through a network port or a serial port, and further collect telemetry and telesignaling sensing data of the distribution terminal; finally, a big data fusion analysis is performed to judge the correctness and automatically generate a test report; and a loop is performed to determine whether the test of all test cases has been completed. If not, the next test case logic test is performed. The present invention implements an injection test of an extended FT3 data frame digital signal, realizes the automated execution of test cases during the test process, improves the efficiency of full or random inspections upon arrival, and reduces the skill level and ability requirements of technical personnel.

The present application is applicable to the field of power system automatic control technology, and provides a one-button sequential control test method, device, and terminal equipment. The one-button sequential control test method includes: obtaining the operation ticket file, substation configuration description SCD file, and substation main wiring diagram of the target substation; generating a first main wiring diagram containing interval information based on the substation main wiring diagram; generating a second main wiring diagram based on the SCD file and the first main wiring diagram; configuring the device state and the operation ticket in the second main wiring diagram according to the operation ticket file; performing an equipment state test on the target substation according to the configured device state, and performing an operation ticket test on the target substation according to the configured operation ticket. The present application enables complete and full logical testing and verification of the "one-button sequential control" operation.

The invention provides a threshold voltage test method, a threshold voltage test system and a readable storage medium, which can be used for carrying out logic sorting again on all tested devices in n test structures to be tested at present according to the sequence of threshold voltages from small to large or from large to small according to known threshold voltage data. According to the method, n'logic test structures are obtained, then serial test or parallel test is carried out according to the logic sequence, and in the test process, according to the test result of the previous tested device or the previous logic test structure, the test voltage initial value of the next tested device or the next logic test structure is dynamically modified, and the test voltage initial value of the next tested device or the next logic test structure is obtained. Therefore, the number of invalid scanning steps and the scanning time in the early stage can be greatly reduced, and the overall testing efficiency is greatly improved.

The invention provides a washing machine electric control test method and system based on parameter simulation and data driving. The method comprises the steps that a washing machine electric control system communicates with an upper computer software system through a serial port; importing the parameter configuration table in the database into an upper computer software system so as to simulate electric control operation parameters through the parameter configuration table to communicate with an electric control system of the washing machine; the parameter configuration table comprises a communication protocol table, a program parameter table and a model table; generating a control logic test case based on the control specification of the washing machine; generating a multi-scene combined fault simulation test case based on the washing machine fault triggering condition; the upper computer software system issues a setting command to the washing machine electric control system based on the control logic test case and / or the fault simulation test case; the washing machine electric control system reports and stores a test result to an upper computer software system; and performing automatic result judgment on the test result to generate a test report, thereby solving the problem that the washing machine electric control test is insufficient in flexibility and coverage rate.

A test method for performing a factory test on an automotive IC (120) includes: performing a logic test on the automotive IC (120) by sending one or more logic test input signals (Logic Test IN) to the automotive IC (120) to generate one or more logic test output signals (Logic Test OUT); while the automotive IC (120) is generating the one or more logic test output signals (Logic Test OUT), utilizing a safety detection circuit (123_1-123_M) within the automotive IC (120) to determine whether at least one analog voltage (VREG) of an analog circuit block (122_1-122_N) of the automotive IC (120) falls within a predetermined range to generate an analog test result; and determining whether the automotive IC (120) passes the factory test according to at least the logic test output signals (Logic Test OUT) and the analog test result.

A test structure and a method for forming the same include: a substrate having a cutting path including a plurality of pixel test areas and a plurality of logic test areas, the pixel test areas and the logic test areas being alternately arranged in a first direction; a pixel test gate structure located above the pixel test areas, the pixel test gate structure extending perpendicularly to the first direction; and a logic test gate structure located above the logic test areas, the logic test gate structure extending perpendicularly to the first direction. The test structure can reduce manufacturing costs, labor, and time.

A test method for performing a factory test on an automotive IC includes: performing a logic test on the automotive IC by sending one or more logic test input signals to the automotive IC to generate one or more logic test output signals; while the automotive IC is generating the one or more logic test output signals, utilizing a safety detection circuit within the automotive IC to determine whether at least one analog voltage of an analog circuit block of the automotive IC falls within a predetermined range to generate an analog test result; and determining whether the automotive IC passes the factory test according to at least the logic test output signals and the analog test result.

The invention discloses a COOLMOS aging test scheme generation method and platform, and relates to the semiconductor device aging test related field, and the method comprises the steps: obtaining COOLMOS specification information, and deploying a physical test scene; the method comprises the following steps: connecting an automatic test platform and introducing a logic test plug-in, initializing the logic test plug-in based on a physical test scene, and performing stage division on a COOLMOS service cycle by the automatic test platform to determine a stage test sequence; a logic test plug-in is triggered, test decision based on knowledge reasoning is carried out stage by stage by taking test circuit topology-stage circuit switching-circuit steady acceleration as a target, and an aging test sequence is generated; and introducing an edge node, connecting the edge node with a physical test end, and executing parallel test management based on cooperation of the automatic test platform and the physical test end. The technical problem that an existing COOLMOS aging test is insufficient in test efficiency and accuracy is solved, and the technical effect of improving the test efficiency and accuracy is achieved.

The invention relates to a method and a test machine for factory testing of integrated circuits using built-in analog voltage self-testing. A test method for performing a factory test on a vehicular integrated circuit includes: generating one or more logical test output signals by transmitting one or more logical test input signals to the vehicular integrated circuit to perform a logical test on the vehicular integrated circuit; when the vehicle integrated circuit is generating the one or more logic test output signals, a safety detection circuit in the vehicle integrated circuit is used for executing a self-test so as to determine whether at least one analog voltage of an analog circuit block of the vehicle integrated circuit falls in a preset range or not, so that an analog test result is generated; and determining whether the vehicle integrated circuit passes the factory test at least according to the one or more logic test output signals and the simulation test result.

The invention provides a multifunctional test point distribution method and system based on a self-adaptive switch matrix, and relates to the technical field of electronic testing, and the method comprises the steps: building a switch matrix through obtaining the topological information of an integrated circuit, and achieving the dynamic connection of a physical probe and a logic test point; distributing the same probe to different test points in different time periods by using a time division multiplexing technology, collecting test response signals and calculating a deviation value; determining a fault point based on the deviation, analyzing the influence degree of the fault point on surrounding nodes, and obtaining a test priority level; the test time sequence is dynamically adjusted according to the priority level, high-priority nodes are preferentially tested, the on-off state is controlled to achieve intelligent distribution of test resources, and the test efficiency and the fault coverage rate are improved.

The invention relates to an AGV forklift attachment control method which comprises an attachment inclination action control step, and the inclination action control step comprises the steps that an oil pump motor is controlled to drive an attachment to incline forwards or backwards, the current inclination angle of the attachment is obtained in real time, and the angle deviation value between the current inclination angle and the target inclination angle is obtained; the rotating speed of an oil pump motor of the AGV forklift is adjusted according to the current inclination direction and the angle deviation value; when the angle deviation value reaches a preset difference value I, the rotating speed of an oil pump motor is controlled to be reduced; when the angle deviation value reaches a second preset difference value, the oil pump motor is controlled to stop; wherein the second preset difference value is smaller than the first preset difference value. The system is reliable and clear in logic, is successfully applied to the AGV forklift, completes function and logic tests, is high in safety protection coefficient, is very low in use cost, and can achieve an intelligent safety protection function.

The invention relates to the technical field of chips, in particular to a method and device for ensuring UPF model file accuracy based on low-power-consumption simulation. The method comprises the steps of obtaining a power supply architecture file of a to-be-verified RTL model, and generating a first UPF model file according to the power supply architecture file; performing difference analysis on the first UPF model file and a manually written second UPF model file to obtain at least one risk point; compiling a logic test case based on the at least one risk point, and performing dynamic simulation on the RTL model to be verified according to the logic test case to obtain a simulation result corresponding to each risk point; and comparing the simulation result with the second UPF model file so as to selectively modify the second UPF model file. According to the method, possible problems of the UPF model file can be found in the initial stage of a project, and timely modification is performed to reduce manpower and time cost and shorten the chip development period.

The invention provides an interface change detection method and device based on a behavior contract, equipment and a medium, and the method integrates dominant change detection and implicit service logic verification to complete the construction of a comprehensive interface change analysis framework. The dominant change analysis result is generated through structured comparison, meanwhile, the test state data and the behavior contract object are associated, and then the logic test is executed based on the business rule, so that the problem that the internal business logic implicit change cannot be detected under the condition that the interface definition is kept unchanged is solved; and interface change detection inaccuracy caused by business logic modification is avoided, so that the accuracy of an interface detection result is improved. The method can be applied to an interface change detection function in the financial field or the medical field, so that the prediction accuracy of the car insurance claim settlement amount in the financial field is improved, or the accuracy of a medical data analysis result in the medical field is improved.