115 results about "Logic testing" patented technology

A circuit and method for testing an eDRAM through a test controller with direct access (DA) mode logic is provided. The circuit and method of the present invention allows the testing of eDRAMs with a conventional memory tester. The present invention provides a semiconductor device including an embedded dynamic random access memory (eDRAM) for storing data, the eDram including a plurality of memory cells, and a test controller for testing the plurality of memory cells to determine if the cells are defective, the test controller including built-in self-test (BIST) logic circuitry for performing tests and for interfacing to a logic tester, and direct access mode logic circuitry for interfacing the eDRAM with an external memory tester. The test controller further comprises a multiplexer for multiplexing data, commands, and addresses from the BIST logic circuitry and the direct access mode logic circuitry to the eDRAM.

The invention discloses a vehicle gear-shifting quality evaluation testing method, which comprises the steps of: 1) at a vehicle gear-shifting quality evaluation testing preparation stage: establishing a vehicle database by adopting an SQL (structured query language) server; establishing a vehicle gear-shifting quality evaluation module by adopting MATLAB/Simulink and determining the core algorithm of the vehicle gear-shifting quality evaluation module; and selecting the type of a vehicle to be tested and a testing system to be used; 2) at a vehicle gear-shifting quality testing stage: conducting gear-shifting rule testing, Tip in testing, Tip out testing, Fast Off testing, brake control logic testing, operability testing, start testing, acceleration testing and driving during a traffic jam; and 3) at a vehicle gear-shifting quality evaluation stage: calling data of the vehicle database as data input of the vehicle gear-shifting quality evaluation model and obtaining an evaluation result through data processing and the like; and outputting the evaluation result a graphical user and result display interface. The invention additionally provides a vehicle gear-shifting quality evaluation testing system.

The present invention is directed to a logic testing architecture with an improved decompression engine and a method of decompressing scan chains for testing logic circuits.

The invention discloses an automatic calibration simulation testing system for an ECU stand. The system comprises an engine controller unit (ECU), calibration equipment ES590, a calibration PC (Personal Computer) machine for operating calibration software INCA and automatic calibration software ACME, a simulation testing system PC machine for operating simulation testing software HYVAT, PeakCAN/ValueCAN3USBCAN communication equipment, a simulation hardware platform and an electronic throttle valve, wherein the simulation hardware platform comprises one of an HY230 function test bed and a real-time simulation system HY360 capable of simulating various sensor signals required by the ECU and providing a simulation load for the ECU. Test cases are developed on the simulation testing system, so that logic test of automatic calibrated cases on the stand is realized, the automatic calibrated cases are sufficiently verified without occupying precious stand resources, and the calibration cost is reduced; and the automatic calibration simulation testing system can also be used for pre-calibration of the ECU stand, so as to shorten the real stand calibration time.

The invention provides a method for increasing the test coverage of a scan chain and a device thereof; wherein, the method for increasing the test coverage of the scan chain comprises: an input end of built-in self testing control signals of a memory being set to be zero in a scanning mode is connected into one register in the scan chain; scan test vector generated by a test vector generation tool is input into the scan chain comprising the register to test combinational logic; the test response and logic expected value of the combinational logic are compared. The method for increasing the test coverage of the scan chain provided by the invention causes that the built-in self testing control signals of the memory can be controlled when the scan chain tests, and realizes the testability of the built-in self testing logic of the memory in the scan mode, thus increasing the logic test coverage of the scan chain test and further increasing the whole test coverage of a chip.

The invention discloses a voltage time type logic tester and a test method. The tester comprises a distribution terminal logic test module, a section switch opening time test module, a closing peak current test module, and a tele-signaling and telemetry aided test module. The distribution terminal logic test module comprises a control circuit, a contactor in the control circuit is connected with a contactor main output circuit, and the contactor main output circuit is connected with a power output end. The section switch opening time test module comprises an hour meter which automatically records the opening time of a switch. The closing peak current test module comprises a current transformer connected in series to the output port of a distribution terminal, and tests the closing peak current through a current meter. The tele-signaling and telemetry aided test module comprises an adjustable voltage and current output module and an analog switch, and the adjustable voltage and current output module outputs adjustable voltage and current and works together with the analog switch to complete tele-signaling and telemetry function test. Voltage time type distribution terminal logic verification, section switch closing peak current test, section switch opening time test, and tele-signaling and telemetry aided function test can be implemented.

A method and circuit for allowing direct access logic testing in integrated circuits. In one embodiment, an interface between integrated circuit core logic and integrated circuit user-defined logic is exposed, and the integrated circuit core logic and the integrated circuit user-defined logic is tested via the exposed interface. In another embodiment, an integrated circuit has logic selection circuitry connected with core logic and user-defined logic. The logic selection circuitry is used to selectively test the core logic and user-defined logic.

The invention provides a bug-fixing client logic testing method and a bug-fixing client logic testing system, which are used for solving the problem that efficiency is affected due to time wasted for bug-fixing client logic. The bug-fixing client logic testing method includes: scanning the system to find out simulated bugs by a bug-fixing client according to a certain mode; downloading corresponding simulated bug patches from a bug base of a server if the simulated bugs are found, and generating simulated bug fixing identification marks on the basis that original system files of the system are reserved by the simulated bug patches; installing the simulated bug patches and generating corresponding the simulated bug fixing identification marks; traversing all modes to complete the whole testing process by the bug fixing client; determining that the bug-fixing client logic testing passes when the above processes are normally executed. The patches can be downloaded and installed quickly, time of the bug-fixing client logic testing is shortened, and testing efficiency is improved.

The embodiment of the invention discloses a program code testing method and device and aims at reducing massive detection brought by traditional route coverage and solving the problem that the detection has not pertinence. The program code testing method comprises the steps that the testing purpose of a test is obtained; a logic topological tree corresponding to a procedure code is searched to obtain a logic outlet node relevant to the testing purpose and serving as a target logic outlet node; the target logic outlet node is used as a starting point, and logic testing is conducted on a logic path containing the target logic outlet node in the logic topological tree. It is thus clear that in the embodiment, logic testing is conducted on a logic path containing the target logic outlet node relevant to the testing purpose, rather than logic testing conducted on all logic paths. Due to the fact that the test is the logic test based on the testing purpose, the program code testing scheme provided by the embodiment has more pertinence compared with traditional white box testing.

Disclosed is a logic testing system that includes a decompressor and a tester in communication with the decompressor. The tester is configured to store a seed and locations of scan inputs and is further configured to transmit the seed and the locations of scan inputs to the decompressor. The decompressor is configured to generate a test pattern from the seed and the locations of scan inputs. The decompressor includes a first test pattern generator, a second test pattern generator, and a selector configured to select the test pattern generated by the first test pattern generator or the test pattern generated by the second test pattern generator using the locations of scan inputs.

The invention discloses a detection method and system for a one-key sequential control system of an intelligent substation, and the method comprises the steps: a one-key sequential control detection system communicating with a detected system through a switcher, and obtaining the information of the detected system; performing data distribution according to a preset SCD model based on the information of the one-key sequential control detection system and the detected system; the detected system performing equipment state migration based on an equipment state migration method specified by the one-key sequential control detection system; the one-key sequential control detection system issuing a remote control instruction to the migrated detected system, performing positive and negative testson the one-key sequential control anti-misoperation locking logic of the tested equipment, and automatically comparing a test result with an expected result to obtain a comprehensive anti-misoperationlocking logic test result; wherein the SCD model is designed on the basis of a main wiring diagram containing various wiring modes of a one-key sequential control detection system. According to the technical scheme provided by the invention, logic decoupling of the equipment state and the current test equipment is realized through equipment state migration, the test configuration is simplified, and the correctness and the coverage rate of an anti-error logic test are improved.

The present invention provides a relay protection test system and method, the relay protection test system includes a test module and a tester, the test module sends test parameters and control instructions to the tester; the tester outputs test signal and receive the action feedback signal of the device under test, compare the test signal output by the tester, the expected action result with the action feedback signal, and realize the relay protection test; the test module is used to The meta library constructs a test logic diagram, and generates a standardized logic test state sequence according to the logic diagram. The system provided by the invention enables users to establish a test logic model simply, intuitively and accurately so as to conduct professional tests of complex functions and logical relationships, which is the development direction of the specialization and standardization of relay protection testing.

A network switch chip having an expansion port configured for transferring data according to a prescribed bus protocol is tested using an external logic unit (e.g., a field programmable gate array) configured to emulate a connected expansion port. The external logic unit is configured for receiving an expansion port frame from the expansion port via an expansion bus, generating a new expansion port frame, and outputting the new expansion port frame to the expansion port via the expansion bus. Hence, a test engineer can validate the expansion port of the network switch chip by detecting the reception of the new expansion port frame by the expansion port. Hence, the expansion port of the network switch chip can be tested without the necessity of a second network switch chip.

The invention discloses an automated testing running method. The method comprises the steps of loading a test case class needed to run currently according to a configuration file in a TestNG framework, and selecting a test case to be executed from test cases; obtaining a corresponding test environment from an environment pool by utilizing the test case, and if the test environment is obtained successfully, specifying a required advanced test environment by adopting a decorator mode; executing preparation work of a basic test environment and the advanced test environment; and executing case test logic defined in the test case to finish actual logic testing. According to the method, the test environment is effectively utilized and the test time is shortened.

A data processing device, comprising a processing unit and a test control unit connected to the processing unit, is described. The processing unit and the test control unit are arranged to: start a logic test of the processing unit; detect a test abort event; and, in response to the test abort event, perform an event response action which comprises aborting the logic test and booting the processing unit, said booting including executing an event handling routine. The event response action may comprise setting a reset vector to an address of the event handling routine. System availability may thus be improved. In particular, the delay between capturing an asynchronous signal and responding to it may be reduced. The test abort event may, for example, be an asynchronous event having certain pre-defined characteristics.

A method of operating a data processing device is also described.

The invention relates to an intelligent high-voltage switch interlocking logic testing method supporting IEC61850 stipulations. The method comprises the following steps that (1) an interlocking logic formula is input to a high-voltage switch interlocking logic testing software functional module, and a computer automatically generates an interlocking logic testing scheme; (2) the computer sends out a control signal to close a connecting port between an intelligent terminal and a switch; (3) the computer sends a high-voltage switch position signal to a measurement and control device according to the interlocking logic testing scheme, a position variable of an element in interlocking relation with a disconnecting link tool to be measured in the measurement and control device is modified, simulation station level equipment sends an instruction to the measurement and control device to control the disconnecting link tool to be measured to act, the measurement and control device sends out an action instruction or an action rejection instruction, and the computer records the instruction. By means of the method, the problems that manual interlocking logic testing does not conform to the interlocking logic judgment flow in the practical running process of an intelligent high-voltage switch, an operation error is prone to occurrence, the workload is large, and testing time is long are solved, and mechanical wear to primary equipment is reduced.