17 results about "Logic testing" patented technology

Run-time logic built-in self-test (LBIST) may be performed, while ensuring operational continuity. The compute elements in a machine learning accelerator contain LBIST circuitry that performs logic testing of the functional circuitry in the compute element. The LBIST circuitry may be self-sufficient, meaning that it contains the data and instructions needed to run and evaluate these tests. An LBIST manager enables the logic testing during idle time of the functional circuitry between blocks of statically scheduled instructions. As a result, the LBIST circuitry can perform the logic tests without disrupting the computation of the machine learning network.

The invention provides a function logic test case generation method, a test method and a device, and the method comprises the steps: automatically generating a directed conversion diagram containing the conversion relation between different hardware power states, and a test matrix containing the specific information of each software logic function through analyzing a demand document of the device; in the process of generating parameter difference information, hardware power supply states and software logic functions are tightly coupled, all possible state conversion paths are traversed through a directed conversion diagram, and functional parameter changes under different hardware power supply states and software logic functions are automatically identified. Therefore, basic test cases corresponding to different functions in each power supply state can be generated; on the basis, boundary parameters and a conversion relation are further adjusted, and a boundary test case and an abnormal test case are generated, so that the test case capable of realizing full-scene coverage is automatically generated, and high-coverage-rate efficient full-automatic test is conveniently carried out on functional logic of the equipment in a multi-power-supply state.

The invention relates to the technical field of semiconductor testing, and discloses a memory chip FT testing method based on probe contact. The method comprises the following steps: acquiring wafer-level process parameters, layout and wiring topology and historical yield data of a chip; dividing a logic test block; calculating the defect probability score of each block and sorting to generate a test sequence; executing full-function testing in sequence, collecting response signal characteristics in real time, comparing the response signal characteristics with the health reference model, and dynamically triggering proximity extension testing or failure judgment; the test result feedback is used for updating the yield data. Through a risk-oriented adaptive test strategy, the test time is shortened and the test cost is reduced while the defect coverage rate is guaranteed.

The application provides a multifunctional test point allocation method and system based on an adaptive switch matrix, relates to the technical field of electronic testing, and realizes dynamic connection of physical probes and logical test points by acquiring integrated circuit topology information to construct a switch matrix; the same probe is allocated to different test points in different time periods by using time division multiplexing technology, test response signals are collected and deviation values are calculated; a fault point is determined based on the deviation, the influence degree of the fault point on surrounding nodes is analyzed, and a test priority level is obtained; the test timing is dynamically adjusted according to the priority level, high-priority nodes are preferentially tested, the switch state is controlled to realize intelligent allocation of test resources, and the test efficiency and fault coverage are improved.

The application relates to the technical field of semiconductor testing, and discloses a memory chip FT test method based on probe contact. The method comprises the following steps: acquiring wafer-level process parameters, layout and wiring topology and historical yield data of a chip; dividing a logic test block; calculating defect probability scores of each block and sorting to generate a test sequence; performing full-function testing in sequence, collecting response signal features in real time and comparing the response signal features with a health benchmark model, and dynamically triggering adjacent expansion testing or failure determination; and feeding back test results to update yield data. The application shortens the test time and reduces the test cost while guaranteeing the defect coverage rate through a risk-oriented adaptive test strategy.

The calibration method and the test equipment for the detection chip provided by the embodiments of the present disclosure comprise the following steps: controlling a target detection chip to continuously generate a trigger signal according to a preset rule; and controlling the target detection chip to output a logic test signal until the logic test signal flips between a high level and a low level; determining the value of the trigger signal; calibrating the target detection chip by using a calibration algorithm according to the determined value of the trigger signal; wherein an internal calibration circuit is configured to provide a calibration channel between the detection chip and a sampling element in the internal calibration circuit; and the internal calibration circuit is configured to establish a target calibration channel according to a control instruction. The embodiments of the present disclosure adopt a linear search method to find the value of the trigger signal, and then calibrate the level comparator of the detection chip by using a preset calibration algorithm according to the value of the trigger signal. Thus, the problem that the level comparator cannot be calibrated in the related art is solved. The integration of the ATE equipment is improved, and the dependence on external equipment is reduced.

The invention provides a multifunctional test point distribution method and system based on a self-adaptive switch matrix, and relates to the technical field of electronic testing, and the method comprises the steps: building a switch matrix through obtaining the topological information of an integrated circuit, and achieving the dynamic connection of a physical probe and a logic test point; distributing the same probe to different test points in different time periods by using a time division multiplexing technology, collecting test response signals and calculating a deviation value; determining a fault point based on the deviation, analyzing the influence degree of the fault point on surrounding nodes, and obtaining a test priority level; the test time sequence is dynamically adjusted according to the priority level, high-priority nodes are preferentially tested, the on-off state is controlled to achieve intelligent distribution of test resources, and the test efficiency and the fault coverage rate are improved.

The invention relates to the technical field of chips, in particular to a method and device for ensuring UPF model file accuracy based on low-power-consumption simulation. The method comprises the steps of obtaining a power supply architecture file of a to-be-verified RTL model, and generating a first UPF model file according to the power supply architecture file; performing difference analysis on the first UPF model file and a manually written second UPF model file to obtain at least one risk point; compiling a logic test case based on the at least one risk point, and performing dynamic simulation on the RTL model to be verified according to the logic test case to obtain a simulation result corresponding to each risk point; and comparing the simulation result with the second UPF model file so as to selectively modify the second UPF model file. According to the method, possible problems of the UPF model file can be found in the initial stage of a project, and timely modification is performed to reduce manpower and time cost and shorten the chip development period.

The invention provides an interface change detection method and device based on a behavior contract, equipment and a medium, and the method integrates dominant change detection and implicit service logic verification to complete the construction of a comprehensive interface change analysis framework. The dominant change analysis result is generated through structured comparison, meanwhile, the test state data and the behavior contract object are associated, and then the logic test is executed based on the business rule, so that the problem that the internal business logic implicit change cannot be detected under the condition that the interface definition is kept unchanged is solved; and interface change detection inaccuracy caused by business logic modification is avoided, so that the accuracy of an interface detection result is improved. The method can be applied to an interface change detection function in the financial field or the medical field, so that the prediction accuracy of the car insurance claim settlement amount in the financial field is improved, or the accuracy of a medical data analysis result in the medical field is improved.

The invention relates to the technical field of automatic testing of financial and medical scenes, and discloses an automatic interface testing method and device, computer equipment and a storage medium, and the method comprises the steps: obtaining all interface requests and response data triggered when a front-end interface is operated through a proxy gateway; then aggregating the discrete requests into a sequential sequence based on a user session ID, and identifying a dynamic parameter dependency relationship multiplexed by a subsequent interface; therefore, a user behavior path graph can be constructed, nodes in the graph represent interfaces, and directed edges represent calling sequences and data circulation; extracting a core path from the atlas and automatically converting the core path into an executable test script, wherein the script integrates dynamic parameter transfer logic; after the test is executed, if failure is caused by interface change, root cause diagnosis is carried out in combination with change information, and the script is automatically repaired by using effective data in the new recorded traffic, so that the self-healing of the test case is realized. According to the invention, the generation and maintenance cost of the test case is obviously reduced.

This application relates to the field of BMS firmware testing technology, and discloses a BMS firmware logic testing method, apparatus, device, and medium. The method includes: acquiring character test cases composed of character data in natural language form; performing instruction conversion processing on the character test cases to obtain a parameter update instruction sequence; sending the parameter update instruction sequence to the BMS firmware under test, and obtaining firmware response information after the BMS firmware under test updates its parameters based on the parameter update instruction sequence; and performing a logical evaluation on the BMS firmware under test based on the firmware response information to generate a logical test result for the BMS firmware under test. The embodiments of this application can reduce the operational difficulty of BMS firmware logic testing and improve testing efficiency.

This invention discloses a method for testing the interlocking logic of a virtual monitoring and control device. Virtual machine A generates a five-prevention logic rule base; virtual machine B identifies the monitoring and control interlocking logic; virtual machine A generates five-prevention logic test templates and multiple corresponding five-prevention logic test templates that do not meet the permitted operation conditions, and sends them to virtual machine B; virtual machine B determines whether the five-prevention logic test template is a permitted operation based on the monitoring and control interlocking logic, and provides feedback to virtual machine A; virtual machine A compares the feedback from virtual machine B with the expected permitted operation signal state of the corresponding five-prevention logic test template. This invention establishes a monitoring and control interlocking test environment using virtual machines A and B, without relying on the monitoring and control devices and primary equipment in operation at the substation, achieving automatic testing of interlocking logic, avoiding equipment wear caused by multiple modifications to the primary equipment status, and improving the efficiency of on-site interlocking verification.

This invention discloses an integrated field comprehensive testing system and method for shipborne electronic equipment, belonging to the field of microwave testing technology. The system employs a physically isolated intelligent control domain and RF front-end domain. Within the RF front-end domain, the main control module analyzes the logic testing requirements based on a weighted directed graph optimization algorithm, coordinates the online loading of the algorithm kernel by the reconfigurable signal processing module, controls the shared broadband frequency synthesis module to allocate the local oscillator signal in a time-division manner, and directly drives the programmable RF switching matrix to perform non-blocking switching, rapidly instantiating the end-to-end physical test link. This invention, through the coordination of reconfigurable signal processing, shared frequency synthesis, and the programmable RF switching matrix by the main control module, achieves single-connection and millisecond-level fully automatic reconfiguration of test tasks. Combined with a three-level progressive clock synchronization architecture, it significantly reduces equipment size and power consumption while meeting the stringent requirements of multi-channel coherent testing and tactical collaborative verification in complex electromagnetic environments.

The invention relates to a configurable NPU general test framework and test method, electronic equipment and a storage medium. The method comprises the following steps that: an application layer receives a user test demand analysis configuration file, and initializes a scheduling module, a log module and a performance statistics module of a core framework; the hardware layer provides a software development kit SDK of neural network processor NPU hardware; the adaptation layer selects to dynamically load a manufacturer adaptation library according to configuration information analyzed by a user test requirement, and calls a hardware initialization interface of the hardware layer; and the core framework layer carries out common logic testing according to task demand analysis. According to the invention, through parameterization demand configuration, generalization module packaging and differentiation interface adaptation test methods, the problem of existing NPU test pain points is solved; a standardized test process is provided, bottom layer hardware differences are shielded, the method can be applied to NPU hardware tests in numerous scenes, test cost is reduced, adaptation efficiency is improved, unification of test standards is achieved, and NPU test efficiency and compatibility in complicated scenes are remarkably improved.

The application provides a test case CBB design method, comprising: designing a data dictionary according to product specification, adopting a black box test design method according to a CBB idea to design a logic test case, referencing the data dictionary to test data, and realizing separation of application data and logic; a physical case generation method is provided, logic test cases are selected according to scene requirements, and sub-cases are obtained by respectively processing network scene, device type and test data by using different test coverage technologies; different test coverage technologies are used on the sub-cases to obtain final physical cases; a test evaluation method is provided, and the association information in the design method and the generation method is used for test evaluation. The application solves the problem of case normalization, and solves the problems of completing risk-based test execution within a limited test period and evaluating test execution results.

The utility model provides an automatic test device for a dual-power change-over switch controller, relates to the technical field of dual-power switches, and comprises a power supply module, a switch module, a control module, a load module, a user module, a logic test control board and an interconnection line communicated with the controller. The method is clear in logic organization, small in code amount, easy to modify and high in reliability, the research and development efficiency is improved, automatic testing is very suitable for repeated testing of previous test cases after logic modification in the research and development stage, repeated work of manual testing is reduced, meanwhile, the automatic testing can also be used for factory testing of devices, the overall design cost is low, universality is high, and the method is suitable for popularization and application. Manual test errors are reduced, research and development efficiency is improved, research and development verification time can be greatly shortened, program extension is flexible, and the method is suitable for wide popularization.

A static timing analysis method and a static timing analysis system are provided. The static timing analysis methods includes: obtaining a standard cell library file for describing a plurality of standard cells; performing topology mapping on the standard cell library file to find out a target sequential cell from the standard cells, in which the sequential cell includes a logic gate, a selection circuit and a register circuit; executing a logic test process to find out a pin combination that has a mutual non-controllable relationship, and removing timing constraints related to the pin combination that are taken as redundant timing constraints from the standard cell library file, so as to generate an optimized standard library file; and perform a static timing analysis on a target circuit design according to the optimized standard cell library file.