Hardware Trojan horse test system

Abstract

The invention discloses a hardware Trojan horse test system. The hardware Trojan horse test system comprises a PC, an NI high-speed digital I/O board and a test circuit, wherein the PC is used for generating a test vector, conducting programming on an FPGA chip, controlling the NI high-speed digital I/O board, an oscilloscope and the FPGA chip and receiving signals sent by the NI high-speed digital I/O board and the oscilloscope; the NI high-speed digital I/O board is used for outputting the test vector to the FPGA chip, collecting an FPGA response signal and sending back the FPGA response signal to the PC; the testing circuit comprises the FPGA chip and receives the test vector output by the NI high-speed digital I/O board. The hardware Trojan horse test system further comprises a precise resistor R1, a precise resistor R2, the oscilloscope and a precise voltage-stabilized source, wherein the precise resistor R1 and the precise resistor R2 monitor the power consumption change of the kernel voltage and the auxiliary voltage of the FPGA chip, the oscilloscope is used for automatically triggering and collecting signals of power consumption change of the kernel voltage and the auxiliary voltage of the FPGA chip and sending the signals to the PC; the precise voltage-stabilized source is used for supplying power to the test circuit. The hardware Trojan horse test system conducts automatic tests, improves the precision of logic testing and bypass analysis and is high in application value.

Description

technical field [0001] The invention relates to the technical field of integrated circuit testing, in particular to a hardware Trojan testing system. Background technique [0002] With the development of semiconductor technology and manufacturing technology, hardware outsourcing design and tape-out have become a global trend. In recent years, a new type of hardware attack method against integrated circuit chips has emerged, called "hardware Trojan horse". Hardware Trojans mainly refer to artificially maliciously adding some illegal circuits or tampering with original design files during the design and manufacture of ICs (Integrated Circuits), thereby leaving "time bombs" or "electronic backdoors" and opening up for subsequent attacks. The door of convenience. Once a hardware Trojan is artificially and covertly inserted into a complex chip, it is very difficult to detect it. First, hardware Trojans are usually only activated and take effect under very special values ​​or co...

AI Technical Summary

Problems solved by technology

Once a hardware Trojan is artificially and covertly inserted into a complex chip, it is very difficult to detect

First, hardware Trojans are usually only activated and take effect under very special values ​​or conditions, and have no effect on the original circuit functions at other times, and they can escape traditional structural and functional tests; second, with With the development of IP (Internet Protocol, a protocol for interconnection between networks) core reuse technology, the number of IP soft cores, solid cores and hard cores used on SoC (System on Chip) has increased, and a small malicious change can be detected It is extremely difficult, and requires a high resolution of the detection method; third, nanoscale integrated circuits and complex systems are difficult to detect hardware Trojans through physical detection and destructive reverse engineering, and the cost is very high and time-consuming Huge, especially when the Trojan horse is selectively inserted into a part of the overall chip, the destructive reverse engineering cannot guarantee that the remaining integrated circuits are free of Trojan horses; Fourth, because the hardware Trojan horse is relatively small compared to the target circuit, process fluctuations and environmental Noise makes detection very difficult; Fifth, the programming commands of chips such as embedded systems, CPU (Central Processing Unit, central processing unit), FPGA (Field-Programmable Gate Array, Field Programmable Gate Array) are not fully disclosed, so It is easy to have system backdoors, through which attackers can obtain system keys and take over the management authority of the entire system, thus causing security risks

Sixth, recycling or counterfeit chips will also greatly reduce the reliability and credibility of chips

A. For more complex test chips, in order to better activate the Trojan horse, the test vectors are often very large, so FPGA needs to take up a lot of resources to store or generate test vectors

B. Test vector generation FPGA generally can only perform simple data processing, and it is difficult to analyze the returned response signal in detail. In addition, the speed of sending and receiving data in communication with the PC is also slow (usually using RS232, SPI, I2C protocols, etc. ), which will reduce the real-time performance of data processing

C. The driving capability of test vector generation FPGA may not meet the requirements of testing FPGA, and a certain communication protocol is required between the two. If the test interface design is not good, it will lead to an increase in the communication bit error rate

[0011] 2) The external logic analyzer requires high storage depth and acquisition speed, which will increase the cost of the system

Moreover, the communication between the logic analyzer and other test instruments (such as oscilloscopes and PCs, etc.) is relatively complicated, which affects the coordination and simplicity of automatic testing

[0012] 3) The power consumption test is only performed on the core voltage in the circuit, and no power consumption test is performed on the auxiliary voltage of the FPGA

A. The LabWindow software program sends plaintext and stimulus test vectors to the FPGA through RS232, but does not collect the response output of the FPGA and does not perform functional comparisons, which will reduce the accuracy of the Trojan horse test

B. The speed of sending and receiving data between FPGA and PC using RS232 communication is slow, and the test efficiency and real-time performance will be reduced. For a large number of tests, the time cost is high

[0019] 2) The power consumption test is only performed on the core voltage in the circuit, and no power consumption test is performed on the auxiliary voltage of the FPGA

The auxiliary voltage is usually used for the power supply of JTAG interface of FPGA, digital clock management, differential drive and designated configuration pins, etc., and is also vulnerable to the influence of integrated circuit hardware Trojan horse

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