18 results about "Test vector generation" patented technology

The invention relates to a storage test vector generation method and device, equipment and a storage medium, and is applied to the field of semiconductor testing, and the method comprises the steps: obtaining a chip manual and a chip test plan of a to-be-tested chip, and generating a chip description file according to the chip manual and the chip test plan; carrying out abstract processing according to the chip description file, and generating a chip abstract model; converting test logic in a test algorithm into a test sequence according to the chip abstract model; and obtaining a target file format requirement of a target ATE equipment platform, and converting the test sequence according to the target file format requirement to generate a storage test vector. The method has the technical effects that the reusability of cross-platform use of the test vector is improved, the test development efficiency is improved, and the time is saved.

This disclosure provides a chip testing system, method, and apparatus. The system includes: an instruction sequence module for generating corresponding test instruction sequence identifiers based on a test instruction set; a test vector generation module for configuring a mode based on rate mode configuration information to determine the target number of channels; and generating a test vector for each channel based on the test instruction sequence identifier; and a test signal output module for performing signal conversion processing on the test vectors to generate a target test signal to complete the chip testing.

The invention provides an in-speed test design method beneficial to time sequence optimization. The in-speed test design method comprises the following steps: S1, a chip design stage, a comprehensive stage and a test vector generation stage: a buffer is arranged in a netlist; s2, a back-end design stage: no buffer exists in a netlist output by a back end; s3, manually modifying the netlist, and adding a buffer; s4, a form verification stage: comparing that the functions of the netlist are the same before and after the addition of the buffer; s5, a test vector generation stage: inputting a netlist containing a buffer; and S6, a simulation verification stage, wherein no buffer exists in the verified netlist. By using the method, the chip can reach faster frequency; the balance of the clock network can be ensured, the structure of the clock network can be simplified, the possibility of errors is reduced, and the process is simpler; the clock path is inserted into an inverter to optimize the time sequence, and the power consumption is lower than that of an inserted buffer; the size of the chip can be reduced by deleting unnecessary buffers, and the production cost is saved; and the correctness is ensured.

The embodiment of the invention discloses a test vector generation method and device and electronic equipment, and relates to the technical field of data processing, and the method comprises the steps: obtaining a standard test interface language STIL file and a configuration file required by a to-be-tested chip scanning SCAN test; testing information in the STIL file is extracted, and configuration information in the configuration file is extracted; carrying out formatting processing on the test information based on the configuration information so as to enable the test information to accord with an SCAN standard test protocol; and converting the formatted test information to generate a test vector. Therefore, conversion from the STIL file to the test vector file can be realized without participation of an EDA simulation tool, and the efficiency of test vector development is greatly improved. Furthermore, by configuring data, the finally output test vector is simplified, and the occupation of storage resources and the debugging difficulty are reduced.

The invention discloses an MCU burning test vector generation method based on protocol conversion, and relates to the field of integrated circuit testing. According to the method, the standard FLM file representing the Flash programming algorithm of the target chip and the Intel HEX file containing the user firmware are deeply analyzed, and the standard PAT test vector script meeting the requirements of the target ATE platform is automatically generated in combination with strict following of SWD protocol rules. According to the process, seamless conversion from a firmware file to an executable test vector is realized, and an internal mechanism covers cooperative processing stages of parameter configuration and file import, key information analysis and standardization, SWD protocol operation sequence generation, final PAT vector script synthesis output and the like; manual intervention and tedious format conversion links in a traditional scheme are effectively eliminated.

The invention provides a photovoltaic model parameter identification method and system based on a differential evolution algorithm, and relates to the technical field of optimization control. The method specifically comprises the following steps: establishing a photovoltaic model, and determining unknown parameters to be identified in the photovoltaic model; taking unknown parameters to be identified in the photovoltaic model as individuals, performing individual optimization by adopting a double-strategy collaborative deployment framework combining a probability-based test vector generation strategy and a parameter adaptive scheme, and updating stagnant individuals by utilizing a gradient descent strategy in the optimization process to obtain optimal individuals; and taking the parameter value corresponding to the optimal individual as the optimal parameter identified in the photovoltaic model. According to the method, a probability-based test vector generation strategy and a parameter adaptive method are combined, and a differential evolution algorithm is improved by combining a diversity improvement strategy, so that the optimization problem of accurate identification of parameters in a photovoltaic model is solved.

The invention provides a test point collaborative iterative optimization method for testability design based on logic deep optimization, and belongs to the field of integrated circuit digital chip scan chain testing. The invention provides a test point optimization design method for solving the problem that the test coverage rate is too low when a circuit carries out automatic test vector generation. The core method comprises the following steps: screening an initial test point set from an original circuit through a Tesent tool, converting output test point information into a constraint file compatible with a DFTC tool, and dynamically adjusting a scan chain insertion strategy; and performing logic depth value traversal on the inserted test points, evaluating the test values of the inserted test points, and iteratively and optimally inserting the test points with low logic depth values and high signal activeness so as to optimize the test coverage rate. The method is mainly applied to testability design of a digital chip, test point selection and scan chain insertion are collaboratively optimized through an EDA tool, the test coverage rate is improved through test point logic depth, and hardware overhead is reduced.

The present disclosure provides an integrated chip for autonomous testing and redundancy repair of interconnection paths between core particles, comprising: at least one core particle, each core particle having a set of interconnection ports for interconnection between core particles and a port selection module, the interconnection ports including a switching interface, an interconnection port and a standby interconnection port; the port selection module is used for connecting the interconnection port with an internal logic circuit signal port according to a selection signal; the at least one self-testing and self-repairing module is used for autonomously completing testing of interconnection paths among the core particles under the action of the switching signal and generating a selection signal according to a test result; the self-test and self-repair module comprises a control circuit, a port selection signal generation module, a test vector generation module, a test vector comparison module, a core particle exchange module and a storage module.

The invention provides an image sensor test method and system. The method comprises the following steps: constructing a test vector generation model; generating a test vector by using the test vector generation model; testing the image sensor by using the test vector to obtain a test result; feeding back a test result to the test vector generation model to dynamically adjust and generate a new test vector; and testing the image sensor by using the new test vector to obtain a final test result. The test vector is automatically generated by constructing the test vector generation model, and the generated test vector is dynamically adjusted according to the test result, so that the corresponding test vector can be generated according to the real-time test requirement and the test result, the generation efficiency of the test vector is improved, the coverage rate of test defects is also improved, and the test efficiency is improved. Therefore, the test efficiency of the image sensor is effectively improved, the test cost is reduced, and the problem of low test efficiency of the existing image sensor is solved.

The application discloses a kind of electric power electronic virtual controller automatic evolution closed loop verification method, device and equipment, method includes: entity identification generates standardization test intent data;Enhanced prompt is constructed by searching knowledge base based on intent data;V-ECU code and test scene script are generated by inputting enhanced prompt into field fine-tuning large language model;V-ECU code and test scene script are executed multidimensional static constraint check, and are compiled into V-ECU image;V-ECU image is connected with digital power grid model and is accessed HIL and is carried out closed loop simulation test, obtains test response data;According to test response data, fitness function is constructed, and test vector is evolved by genetic variation algorithm iteration, and standardization verification report is generated.The application can solve the technical problems that the reuse rate of existing HIL simulation test is low and the cost is high, the coverage is limited to the definition boundary, and does not have the generation ability of virtual controller.

The invention discloses a test vector generation device and an aging test system, and relates to the technical field of circuits, the test vector generation device comprises a plurality of sequence generators, a multiplexer and a control circuit; the control circuit is used for respectively sending test sequence generation signals to the plurality of sequence generators under the condition that a to-be-tested chip where the test vector generation device is located is connected with the aging test bench; the sequence generators are used for respectively generating candidate test sequences under the condition that the test sequence generation signals are received, each sequence generator generates one candidate test sequence, and the candidate test sequences generated by the sequence generators are different; the multiplexer is used for selecting a target test sequence from the plurality of candidate test sequences, and the target test sequence is used for carrying out aging test on the to-be-tested chip. Compared with the prior art, the method does not need a test board to provide a test vector for the to-be-tested chip, increases the flexibility of the aging test, and improves the user experience.

The invention relates to the technical field of circuits, and discloses a grid distributed ICG control method, structure, device, equipment and medium, and the method comprises the steps: generating a pre-scanning netlist, dividing an original chip layout into grid regions, and obtaining a corresponding ICG list; cLUs are obtained, a CLU scanning chain is generated according to each CLU, and a target scanning netlist is generated according to the CLU scanning chains; and allocating the CLU to the grid area according to the target scanning netlist, and controlling each ICG through the CLU. According to the mode, the chip is physically divided into the multiple grid areas, the independent CLU is deployed for each grid for control, refined and regionalized on-demand starting of the ICG unit is achieved, each CLU serves as an independent control point capable of being configured by the scan chain, and the ICG unit can be started according to needs. A direct and flexible control channel is provided for an automatic test vector generation tool, and the test coverage rate of a chip is improved.

The invention provides an on-chip test clock controller and an on-chip test clock control method, in an RTL design stage, a controllable first register and a controllable second register are arranged in the on-chip test clock controller, and in a scanning test stage, the on-chip test clock controller is connected with the first register and the second register. The automatic test vector generation tool can control the first clock gating device and the second clock gating device to be turned on or turned off by controlling the first register and the second register to output an enable signal or a disable signal; the first clock signal can be controlled to only pass through one time sequence path, the problem that time sequence convergence is difficult due to the fact that time sequence deviation between different time sequence paths is too large is solved, complex optimization depending on later physical design is avoided, the design period is remarkably shortened, and tool resource occupation and labor cost are reduced.

The application discloses a test vector generation device and an aging test system, and relates to the technical field of circuits. The test vector generation device comprises a plurality of sequence generators, a multiplexer and a control circuit. The control circuit is configured to send test sequence generation signals to the plurality of sequence generators respectively under the condition that a chip to be tested where the test vector generation device is located is connected with an aging test platform. The sequence generators are configured to generate candidate test sequences respectively under the condition that the test sequence generation signals are received. Each sequence generator generates one candidate test sequence, and the candidate test sequences generated by each sequence generator are different. The multiplexer is configured to select a target test sequence from the plurality of candidate test sequences. The target test sequence is used for aging test of the chip to be tested. Compared with the prior art, the application does not need the test platform to provide test vectors to the chip to be tested, increases the flexibility of the aging test, and improves user experience.

The application provides a fault detection method and system of integrated chip, and relates to the technical field of semiconductor, comprising: obtaining a scan chain fault dictionary related to inherent properties of the integrated chip, and composing a fault feature matrix comprising different fault state vectors; determining a test vector generation constraint for modulating the fault feature matrix; generating an optimized test vector of the scan chain by solving a convex relaxation optimization function about the test vector; performing fault detection on the integrated chip by using the optimized test vector, and collecting a response matrix; combining the response matrix and the optimized test vector, and solving a fault state estimation vector; measuring the confidence of the fault state estimation vector by residual entropy, and in the case that the confidence is greater than a preset confidence, narrowing the upper limit value of the test vector generation constraint, and returning to update the optimized test vector; otherwise, outputting a fault position and a fault type. The fault ambiguity is eliminated, and the fault type and position can be accurately identified.

The invention provides a test vector generation method and device based on coverage rate driving, equipment and a medium. The method comprises the following steps: acquiring a first test vector population; the first test vector population comprises a plurality of first test vectors; based on the first number corresponding to the first test vectors and the second number corresponding to the first test vectors, potential degrees corresponding to the first test vectors are determined; the potential degree is used for representing the quality degree of the first test vector; determining fitness corresponding to each first test vector based on the coverage rate of each first test vector and the potential degree of each first test vector; and generating a second test vector based on each fitness, each first test vector and a coverage rate driving mode. According to the method, the quality of the selected test vector is improved, and a large number of individuals of unexplored neighborhoods are reserved, so that the problems of too fast population convergence, later repeated search, missing of rare scenes, influence on long-tail coverage point convergence and the like are solved.

Embodiments of the present application provide an error information recording method and device, electronic equipment and storage medium, and relate to the technical field of chip automatic test equipment. The method comprises a plurality of digital boards, a main control card and a memory. First, a test vector is created and run to generate channel data. The main control card controls the digital board to mark error data and corresponding station information according to a preset rule to form first error information. The main control card controls the digital board to convert the first error information into second error information through a data transmission mode. The second error information sent by the digital board is received, and third error information is parsed from the second error information. According to a preset gating condition, fourth error information is screened from the third error information, and the fourth error information is stored in the memory. The method can realize synchronous recording of error information for multiple test stations.

The invention provides a chip testing system and method, and relates to the technical field of chip testing, and the system comprises a to-be-tested chip and at least one testing pin connected with the to-be-tested chip. The chip to be tested comprises at least one function test module and a pin selection module; the at least one test pin is connected with the at least one function test module through the pin selection module; the pin selection module is used for establishing electric connection between the first test pin and the first function test module according to a preset pin distribution scheme; the at least one test pin is used for inputting the test vector to the at least one function test module, and / or receiving a test result generated by the at least one function test module based on the test vector. According to the chip test system provided by the invention, the function test module can flexibly select any test pin to input the test vector and output the test result, and the overall test efficiency is effectively improved.