47 results about "Test vector generation" patented technology

The invention relates to a storage test vector generation method and device, equipment and a storage medium, and is applied to the field of semiconductor testing, and the method comprises the steps: obtaining a chip manual and a chip test plan of a to-be-tested chip, and generating a chip description file according to the chip manual and the chip test plan; carrying out abstract processing according to the chip description file, and generating a chip abstract model; converting test logic in a test algorithm into a test sequence according to the chip abstract model; and obtaining a target file format requirement of a target ATE equipment platform, and converting the test sequence according to the target file format requirement to generate a storage test vector. The method has the technical effects that the reusability of cross-platform use of the test vector is improved, the test development efficiency is improved, and the time is saved.

The invention discloses an integrated circuit scan chain diagnosis method and system based on an artificial neural network, and the method comprises the steps: firstly, injecting two random faults, namely, buck at-0 and buck at-1, into each scan trigger in an integrated circuit scan chain, and generating a random number through a linear feedback shift register to obtain a random period of the fault; then executing automatic test vector generation to obtain a pattern report containing fault information and a corresponding simulation log; and finally, obtaining an integer fault vector and a label vector through the pattern report and the simulation log, inputting the integer fault vector and the label vector into an artificial neural network for training and verification, and predicting through the trained artificial neural network to obtain a fault position in the integrated circuit scan chain. According to the method, random period faults are generated, abnormal data are eliminated, the artificial neural network model is used, the risk of man-made misjudgment and missing detection is effectively reduced, and accurate prediction is achieved.

The invention belongs to the technical field of testability design of super-large-scale integrated circuits, discloses a TSV test and diagnosis circuit and method based on BIST, and provides a hardware circuit architecture for TSV test and diagnosis. The device comprises a test access port controller, a test data register, a test vector generator, a shift register, a double-edge trigger, a TSV (Through Silicon Via) test controller, an improved loading chip packaging register and an improved capturing chip packaging register, and the test access port controller is responsible for configuring a test path, a test mode and a test enable signal; the TSV test controller is activated after the test enabling is synchronized by the double-edge trigger, and the improved chip packaging register based on the lossless compression structure is controlled to execute the test, so that efficient fault detection and diagnosis of different fault types are realized. Through cooperation of test vector generation and response compression, the test time is effectively shortened, and an innovative solution is provided for efficient and reliable TSV test and diagnosis.

A first set of features may be extracted from a first integrated circuit (IC) design. A trained machine learning (ML) model may predict a set of ranked test-case configurations for the first IC design based on the first set of features. A test-case configuration may correspond to a count of scan chain input and output ports and a scan chain length value.

The invention discloses an automatic test vector generation method and system based on backtracking path optimization, and the method comprises the steps: inputting the feature information of each logic gate of a to-be-tested circuit into a trained neural network model, and predicting the state of each logic gate, including success and failure; and performing automatic test vector generation by adopting an ATPG algorithm according to the state of the logic gate, selecting the logic gate to add into a backtracking path for the logic gate with a successful label in the backtracking process, and skipping the logic gate for the logic gate with a failed label. According to the method, backtracking path generation is assisted according to the prediction result, more efficient test vector generation of the ATPG tool is facilitated, and the test time and the backtracking frequency are reduced.

The invention provides a test vector generation method and device in circuit design, and the method comprises the steps: obtaining a scanning chain group in the circuit design, the scanning chain group comprises N scanning chains, and each scanning chain in the N scanning chains comprises at least one register; value constraint is carried out on at least one register of each scanning chain in the N scanning chains according to a preset code pattern, the value constraint is used for limiting the value of the at least one register to be 0 or 1, the length of continuous 0 or the length of continuous 1 in the preset code pattern does not exceed Q, and Q is larger than or equal to 1; and according to the register subjected to value constraint, solving to obtain a test vector corresponding to the scan chain group. The method provided by the invention can realize high-precision diagnosis.

The invention discloses a processing method and device and electronic equipment, and the processing method comprises the steps: generating an initial test vector supported by test equipment according to the test equipment and a test case for a to-be-tested chip; based on the initial test vector, performing simulation verification on the to-be-tested chip, and based on a simulation verification result, adjusting the initial test vector until the simulation verification is passed, and forming a target test vector; and generating a test program of the test equipment based on the target test vector.

The invention discloses an automatic test vector generation method and system based on a decision tree, and the method comprises the steps: firstly extracting the node feature data of a to-be-tested circuit, and then obtaining and calculating the backtracking confidence coefficient of each logic gate through a trained decision tree model; the backtracking confidence is a prediction probability value of the decision tree model for successful fault propagation of the logic gate in the backtracking path; and finally, selecting a logic gate with high backtracking confidence as a node to be added into a backtracking path, and generating a test vector according to the backtracking path. According to the method, the number of test vectors can be effectively reduced, the time complexity of fault detection is reduced, and the problems of high backtracking frequency, high resource consumption, noise data interference and the like in a traditional method are solved.

This disclosure provides a chip testing system, method, and apparatus. The system includes: an instruction sequence module for generating corresponding test instruction sequence identifiers based on a test instruction set; a test vector generation module for configuring a mode based on rate mode configuration information to determine the target number of channels; and generating a test vector for each channel based on the test instruction sequence identifier; and a test signal output module for performing signal conversion processing on the test vectors to generate a target test signal to complete the chip testing.

The present invention relates to the field of circuit security technology and proposes a security assessment method and system for a logic-locked encryption circuit, comprising: extracting key bits, logic gates, and logic cone sets in the logic-locked encryption circuit; searching for logically blockable key bits in the key bits; obtaining an X-state fill object in an automatic test vector generation algorithm based on the logically blockable key bits; traversing the logic cone set, generating a first test vector for the key bits in the logic cone based on the automatic test vector generation algorithm to obtain an ideal response; assuming a stuck-at fault for the current key bit, regenerating a second test vector based on the automatic test vector generation algorithm to obtain an actual response; comparing the actual response with the ideal response to obtain an inferable key; and calculating the proportion of inferable key bits in the key bits and comparing it with a preset threshold to obtain a security assessment result. The present invention significantly improves the efficiency of security assessment of logic-locked circuits.

The invention provides an in-speed test design method beneficial to time sequence optimization. The in-speed test design method comprises the following steps: S1, a chip design stage, a comprehensive stage and a test vector generation stage: a buffer is arranged in a netlist; s2, a back-end design stage: no buffer exists in a netlist output by a back end; s3, manually modifying the netlist, and adding a buffer; s4, a form verification stage: comparing that the functions of the netlist are the same before and after the addition of the buffer; s5, a test vector generation stage: inputting a netlist containing a buffer; and S6, a simulation verification stage, wherein no buffer exists in the verified netlist. By using the method, the chip can reach faster frequency; the balance of the clock network can be ensured, the structure of the clock network can be simplified, the possibility of errors is reduced, and the process is simpler; the clock path is inserted into an inverter to optimize the time sequence, and the power consumption is lower than that of an inserted buffer; the size of the chip can be reduced by deleting unnecessary buffers, and the production cost is saved; and the correctness is ensured.

The utility model provides a test device and system. The test device comprises a vector unit, a switching controller, a first clock controller and a plurality of logic gates, the vector unit is used for being connected to test vector generation equipment to obtain a test vector and outputting an enable vector based on the test vector; the switching controller is connected to the vector unit, and the switching controller is configured to provide a switching signal to the vector unit; the input ends of the logic gates are connected to the vector unit and the first clock controller, and the output ends of the logic gates are respectively connected to a plurality of partitions of a to-be-tested element; and the plurality of logic gates provide second clock signals for the plurality of partitions of the to-be-tested element based on the enable vector and a first clock signal output by the first clock controller, so that a register in the to-be-tested element is selectively overturned based on the second clock signal. According to the scheme, the effects of reducing the test power consumption and improving the coverage rate and the test efficiency are achieved.

The invention relates to a standard cell library test chip and test method, and a computer readable storage medium, the chip comprising: a standard cell set module comprising at least one standard cell in a standard cell library, each standard cell in the standard cell set module being classified according to a preset rule; the test vector generation module is connected with the standard unit collection module and is used for generating a test vector corresponding to each type of standard units according to the preset rule; and the output module is connected with the standard unit collection module and is used for outputting results obtained by the standard units according to the corresponding test vectors input by the input ends of the standard units. According to the invention, the redundancy of the test vectors and the increase of operand caused by the input of redundant test vectors by the sequential logic standard unit can be avoided, and the data storage requirements in the standard cell library test chip are reduced.

The present invention relates to the field of chip testing technology, and in particular to a memory output interface functional path testing method, electronic device, and medium. The method comprises: step S1, obtaining a target output interface functional path in a functional output circuit connected to a memory output interface, and generating a target output interface functional path list; step S2, an automatic test vector generation tool selecting at least one target output interface functional path from the target output interface functional path list, and automatically generating a test vector; step S3, inputting the generated test vector into a memory through an MBIST input circuit; and step S4, creating a conversion at the output interface through the selected target output interface functional path, capturing target output data, and comparing the target output data with a preset value. If they are consistent, the test passes; otherwise, the test fails. The present invention improves the memory output interface test performance and increases the chip operating frequency.

The embodiment of the invention discloses a test vector generation method and device and electronic equipment, and relates to the technical field of data processing, and the method comprises the steps: obtaining a standard test interface language STIL file and a configuration file required by a to-be-tested chip scanning SCAN test; testing information in the STIL file is extracted, and configuration information in the configuration file is extracted; carrying out formatting processing on the test information based on the configuration information so as to enable the test information to accord with an SCAN standard test protocol; and converting the formatted test information to generate a test vector. Therefore, conversion from the STIL file to the test vector file can be realized without participation of an EDA simulation tool, and the efficiency of test vector development is greatly improved. Furthermore, by configuring data, the finally output test vector is simplified, and the occupation of storage resources and the debugging difficulty are reduced.

The invention discloses an MCU burning test vector generation method based on protocol conversion, and relates to the field of integrated circuit testing. According to the method, the standard FLM file representing the Flash programming algorithm of the target chip and the Intel HEX file containing the user firmware are deeply analyzed, and the standard PAT test vector script meeting the requirements of the target ATE platform is automatically generated in combination with strict following of SWD protocol rules. According to the process, seamless conversion from a firmware file to an executable test vector is realized, and an internal mechanism covers cooperative processing stages of parameter configuration and file import, key information analysis and standardization, SWD protocol operation sequence generation, final PAT vector script synthesis output and the like; manual intervention and tedious format conversion links in a traditional scheme are effectively eliminated.

The present invention discloses a method and system for automatic test vector generation based on a decision tree. The method first extracts node feature data of a circuit under test, and then uses a trained decision tree model to obtain the backtracking confidence level for each logic gate. The backtracking confidence level is the predicted probability value of the decision tree model for the successful propagation of a fault by the logic gate in the backtracking path. Finally, the logic gates with high backtracking confidence levels are selected as nodes to be added to the backtracking path, and test vectors are generated according to the backtracking path. The present invention can effectively reduce the number of test vectors, reduce the time complexity of fault detection, and solve the problems of high backtracking frequency, large resource consumption, and interference from noise data in traditional methods.

The embodiment of the invention discloses a test vector generation method and device and computing equipment, and the method comprises the steps: obtaining conversion information, the conversion information comprises pin information, at least one piece of test service information and a conversion rule, each piece of test service information comprises fixed test data and configurable test data, performing parameter value configuration on each piece of first target configurable test data to obtain each piece of first configuration test data, determining first target test service information corresponding to each piece of first configuration test data in the conversion information, converting each piece of first configuration test data by using a conversion rule to obtain a first target test vector, and sending the first target test vector to a server; and executing the first target test vector to test and obtain a first test result. Therefore, when the test vector is generated, only the configurable test data needs to be set, and all test information required by testing does not need to be edited in the test vector template, so that a large amount of manpower is saved, and the accuracy and efficiency of the test vector are improved.

The invention provides a photovoltaic model parameter identification method and system based on a differential evolution algorithm, and relates to the technical field of optimization control. The method specifically comprises the following steps: establishing a photovoltaic model, and determining unknown parameters to be identified in the photovoltaic model; taking unknown parameters to be identified in the photovoltaic model as individuals, performing individual optimization by adopting a double-strategy collaborative deployment framework combining a probability-based test vector generation strategy and a parameter adaptive scheme, and updating stagnant individuals by utilizing a gradient descent strategy in the optimization process to obtain optimal individuals; and taking the parameter value corresponding to the optimal individual as the optimal parameter identified in the photovoltaic model. According to the method, a probability-based test vector generation strategy and a parameter adaptive method are combined, and a differential evolution algorithm is improved by combining a diversity improvement strategy, so that the optimization problem of accurate identification of parameters in a photovoltaic model is solved.

The invention belongs to the technical field of equipment testing, and particularly discloses an automatic test vector generation device and method, and the device comprises automatic test equipment, and a controller and a tested device which are connected with the automatic test equipment. The automatic test equipment provides a working power supply for the controller and the tested device, and sends a trigger signal to the controller to start the test; the controller is used for providing a DUT bidirectional pin indication signal for the automatic test equipment through an interaction state between the controller and the tested device; the automatic test equipment is used for collecting a DUT pin signal of a device to be tested, and automatically generating a test vector for exciting the DUT according to the DUT pin signal and a DUT bidirectional pin indication signal. According to the invention, the generation efficiency and accuracy of the test vector can be improved.

The invention provides a test point collaborative iterative optimization method for testability design based on logic deep optimization, and belongs to the field of integrated circuit digital chip scan chain testing. The invention provides a test point optimization design method for solving the problem that the test coverage rate is too low when a circuit carries out automatic test vector generation. The core method comprises the following steps: screening an initial test point set from an original circuit through a Tesent tool, converting output test point information into a constraint file compatible with a DFTC tool, and dynamically adjusting a scan chain insertion strategy; and performing logic depth value traversal on the inserted test points, evaluating the test values of the inserted test points, and iteratively and optimally inserting the test points with low logic depth values and high signal activeness so as to optimize the test coverage rate. The method is mainly applied to testability design of a digital chip, test point selection and scan chain insertion are collaboratively optimized through an EDA tool, the test coverage rate is improved through test point logic depth, and hardware overhead is reduced.

The present disclosure provides an integrated chip for autonomous testing and redundancy repair of interconnection paths between core particles, comprising: at least one core particle, each core particle having a set of interconnection ports for interconnection between core particles and a port selection module, the interconnection ports including a switching interface, an interconnection port and a standby interconnection port; the port selection module is used for connecting the interconnection port with an internal logic circuit signal port according to a selection signal; the at least one self-testing and self-repairing module is used for autonomously completing testing of interconnection paths among the core particles under the action of the switching signal and generating a selection signal according to a test result; the self-test and self-repair module comprises a control circuit, a port selection signal generation module, a test vector generation module, a test vector comparison module, a core particle exchange module and a storage module.

The invention relates to the technical field of chip testing, in particular to a memory input interface function path testing method, electronic equipment and a medium, and the method comprises the steps: S1, obtaining a target input interface function path in a function input circuit connected with a memory input interface, and generating a target input interface function path list; s2, selecting at least one target input interface function path from the target input interface function path list by an automatic test vector generation tool, and automatically generating a test vector; s3, inputting the generated test vector into a memory through the selected target input interface function path, and creating conversion on an input interface of the memory; and S4, capturing target output data through an MBIST output circuit, comparing the target output data with a preset value, if the target output data are consistent with the preset value, determining that the test is passed, otherwise, determining that the test is not passed. According to the invention, the test performance of the memory input interface is improved, and the chip operation frequency is improved.

The test vector generation method provided by the invention comprises the following steps: acquiring a chip function test instruction, and analyzing task content and task input parameters contained in the function test instruction; selecting a corresponding instruction template based on the task content, calling the instruction template, assigning an instruction register value, and obtaining a TDI data sequence and TDO data according to a corresponding address parameter and write / read data in task input parameters; the instruction template is created based on a jtag protocol, an ADI protocol and a data transmission protocol of a chip test circuit, and the instruction template is associated with a jtag test driving function; calling the jtag test driving function according to the instruction register value, the TDI sequence and the TDO data, and outputting the content of the function test instruction as the combination of the TDI data, the TCK signal, the TMS signal and the TDO signal at different moments. The invention further provides a test vector generation system and a computer readable storage medium.

The invention relates to the technical field of circuit safety, and provides a safety evaluation method and system for a logic locking encryption circuit, and the method comprises the steps: extracting a key bit, a logic gate and a logic cone set in the logic locking encryption circuit; finding a key bit capable of being logically blocked in the key bits; obtaining an X state filling object in an automatic test vector generation algorithm based on the logically blocked key bit; traversing the logic cone set, and generating a first test vector for the key bit in the logic cone based on an automatic test vector generation algorithm to obtain an ideal response; assuming a fixed fault for the current key bit, and generating a second test vector again based on the automatic test vector generation algorithm to obtain an actual response; comparing the actual response with the ideal response to obtain a deducable key; and calculating the proportion of the inferred key bit in the key bit, and comparing the proportion with a preset threshold value to obtain a security evaluation result. According to the invention, the safety evaluation efficiency of the logic locking circuit is obviously improved.

The invention provides an image sensor test method and system. The method comprises the following steps: constructing a test vector generation model; generating a test vector by using the test vector generation model; testing the image sensor by using the test vector to obtain a test result; feeding back a test result to the test vector generation model to dynamically adjust and generate a new test vector; and testing the image sensor by using the new test vector to obtain a final test result. The test vector is automatically generated by constructing the test vector generation model, and the generated test vector is dynamically adjusted according to the test result, so that the corresponding test vector can be generated according to the real-time test requirement and the test result, the generation efficiency of the test vector is improved, the coverage rate of test defects is also improved, and the test efficiency is improved. Therefore, the test efficiency of the image sensor is effectively improved, the test cost is reduced, and the problem of low test efficiency of the existing image sensor is solved.

The application discloses a kind of electric power electronic virtual controller automatic evolution closed loop verification method, device and equipment, method includes: entity identification generates standardization test intent data;Enhanced prompt is constructed by searching knowledge base based on intent data;V-ECU code and test scene script are generated by inputting enhanced prompt into field fine-tuning large language model;V-ECU code and test scene script are executed multidimensional static constraint check, and are compiled into V-ECU image;V-ECU image is connected with digital power grid model and is accessed HIL and is carried out closed loop simulation test, obtains test response data;According to test response data, fitness function is constructed, and test vector is evolved by genetic variation algorithm iteration, and standardization verification report is generated.The application can solve the technical problems that the reuse rate of existing HIL simulation test is low and the cost is high, the coverage is limited to the definition boundary, and does not have the generation ability of virtual controller.

The invention discloses a test vector generation device and an aging test system, and relates to the technical field of circuits, the test vector generation device comprises a plurality of sequence generators, a multiplexer and a control circuit; the control circuit is used for respectively sending test sequence generation signals to the plurality of sequence generators under the condition that a to-be-tested chip where the test vector generation device is located is connected with the aging test bench; the sequence generators are used for respectively generating candidate test sequences under the condition that the test sequence generation signals are received, each sequence generator generates one candidate test sequence, and the candidate test sequences generated by the sequence generators are different; the multiplexer is used for selecting a target test sequence from the plurality of candidate test sequences, and the target test sequence is used for carrying out aging test on the to-be-tested chip. Compared with the prior art, the method does not need a test board to provide a test vector for the to-be-tested chip, increases the flexibility of the aging test, and improves the user experience.

The invention belongs to the technical field of integrated circuit testing, particularly relates to a high-resolution path delay testing system and method for an FPGA (Field Programmable Gate Array), and aims to solve the problem that delay faults are difficult to efficiently detect with high resolution by the existing testing method. According to the invention, a clock input module generates working and clock references and sends the working and clock references to a clock delay module and an output acquisition module respectively; the clock delay module receives a work clock, an initial tap is set to be 0, a delay clock is generated to the test vector generation module, and the test vector generation module generates a test excitation signal to drive a module to be tested accordingly. An output signal returns to the output acquisition module, and the circuit function is evaluated by comparing a reference clock. The sequence detection module monitors the number of taps of the clock delay module, and if the number does not reach a threshold value, the number of taps is circularly increased and the test process is repeated; and if the standard is reached, stopping the test. According to the invention, the test cost is reduced, the product reliability and quality assurance are enhanced, and the method has wide applicability and flexibility.

The invention relates to the technical field of circuits, and discloses a grid distributed ICG control method, structure, device, equipment and medium, and the method comprises the steps: generating a pre-scanning netlist, dividing an original chip layout into grid regions, and obtaining a corresponding ICG list; cLUs are obtained, a CLU scanning chain is generated according to each CLU, and a target scanning netlist is generated according to the CLU scanning chains; and allocating the CLU to the grid area according to the target scanning netlist, and controlling each ICG through the CLU. According to the mode, the chip is physically divided into the multiple grid areas, the independent CLU is deployed for each grid for control, refined and regionalized on-demand starting of the ICG unit is achieved, each CLU serves as an independent control point capable of being configured by the scan chain, and the ICG unit can be started according to needs. A direct and flexible control channel is provided for an automatic test vector generation tool, and the test coverage rate of a chip is improved.