Circuit and method for generating test vectors required by built-in self-test of integrated circuit

Abstract

The invention relates to a circuit for generating test vectors required by built-in self-test of an integrated circuit. The circuit comprises an address counter, a sequence counter, a seed and multinomial coefficient storage unit, a sequence generator, a weight generating logical unit, 4-Line to 1-Line data selectors, an input register and scan chains, wherein the address counter is used for sending address data sequences; the sequence counter is used for sending data sequences; the seed and multinomial coefficient storage unit is connected with the address counter and used for sending output values of compressed vectors difficult and easy to test; the sequence generator is connected with the sequence counter and the seed and multinomial coefficient storage unit and used for outputting 2-bit data; the weight generating logical unit is used for outputting four-channel data values; the 4-Line to 1-Line data selectors are connected with the weight generating logical unit and the sequence generator and used for outputting one-channel data; the input register is connected with the 4-Line to 1-Line data selectors and used for registering data and loading updated data; the scan chains are connected with the input register and a tested circuit combinatorial logic unit and used for outputting the updated data. A tested circuit is connected with the scan chains and used for detecting faults of the tested circuit. The invention further provides a method for generating the test vectors required by built-in self-test of the integrated circuit.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to deterministic test vector compression and decompression technology for integrated circuit built-in self-test, and test vector generation technology in pseudo-random test. Background technique [0002] An integrated circuit is tested and diagnosed at several different times in its life cycle. Testing and diagnostics must be fast and have high fault coverage. Built-In Self-Test Technology (Build-In Self-Test, BIST) realizes the self-test of the integrated circuit by adding a small amount of logic circuit inside the integrated circuit, which can reduce the test cost and test at the circuit frequency, so it is widely used in the industry . An example of built-in self-test is disclosed in Japanese Patent No. 2007-240390A. The built-in self-test circuit generates test vectors through a linear feedback shift register (LFSR), compresses the test response of the circuit under test th...

AI Technical Summary

Problems solved by technology

[0007] In order to solve the problem that a large amount of test time is occupied by useless data sequences in the prior art, and at the same time in order to solve the problem that a large number of storage units are occupied by deterministic test vectors in the prior art, the purpose of the present invention is to provide a built-in integrated circuit Method and circuit for generating test vector required for self-test

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