448 results about "System verification" patented technology

The invention comprises a laying, semi-vertical, or seated patient positioning, alignment, and/or control method and apparatus used in conjunction with multi-axis charged particle or proton beam radiation therapy of cancerous tumors. Patient positioning constraints are used to maintain the patient in a treatment position, including one or more of: a seat support, a back support, a head support, an arm support, a knee support, and a foot support. One or more of the positioning constraints are movable and/or under computer control for rapid positioning and/or immobilization of the patient. The system optionally uses an X-ray beam that lies in substantially the same path as a proton beam path of a particle beam cancer therapy system. The generated image is usable for: fine tuning body alignment relative to the proton beam path, to control the proton beam path to accurately and precisely target the tumor, and/or in system verification and validation.

The invention comprises a semi-vertical or seated patient positioning, alignment, and/or control method and apparatus used in conjunction with multi-axis charged particle or proton beam radiation therapy of cancerous tumors. Patient positioning constraints are used to maintain the patient in a treatment position, including one or more of: a seat support, a back support, a head support, an arm support, a knee support, and a foot support. One or more of the positioning constraints are movable and/or under computer control for rapid positioning and/or immobilization of the patient. The system optionally uses an X-ray beam that lies in substantially the same path as a proton beam path of a particle beam cancer therapy system. The generated image is usable for: fine tuning body alignment relative to the proton beam path, to control the proton beam path to accurately and precisely target the tumor, and/or in system verification and validation.

The invention comprises a semi-vertical patient positioning, alignment, and/or control method and apparatus used in conjunction with charged particle or proton beam radiation therapy of cancerous tumors. Patient positioning constraints are used to maintain the patient in a treatment position, including one or more of: a seat support, a back support, a head support, an arm support, a knee support, and a foot support. One or more of the positioning constraints are movable and/or under computer control for rapid positioning and/or immobilization of the patient. The system optionally uses an X-ray beam that lies in substantially the same path as a proton beam path of a particle beam cancer therapy system. The generated image is usable for: fine tuning body alignment relative to the proton beam path, to control the proton beam path to accurately and precisely target the tumor, and/or in system verification and validation.

Some embodiments provide a verification system for automated verification of entities. The verification system automatedly verifies entities using a two part verification campaign. One part verifies that the entity is the true owner of the entity account to be verified. This verification step involves (1) the entity receiving a verification code at the entity account and returning the verification code to the verification system, (2) the entity associating an account that it has registered at a service provider to an account that the verification system has registered at the service provider, (3) both. Another part verifies the entity can respond to communications that are sent to methods of contact that have been previously verified as belonging to the entity. The verification system submits a first communication with a code using a verified method of contact. The verification system then monitors for a second communication to be returned with the code.

The presented inventions concern communication systems with services. The services provided by the presented systems are invisible to port scans, allowing security critical data to be stored on units without any permanently open connection endpoints. Existing network systems according to the client/server-principle require the permanent provision of open connection endpoints to be accessible on a 24h base. The large number of services implies a large number of open connection endpoints, where each open connection endpoint presents a potential point-of-attack for malicious clients. The object of the present invention is to securely provide services in communication systems. The present invention overcomes the prior art by triggerable invisible services, which during normal operation do not provide any permanently open connection endpoint. Connection endpoints are only opened after prior client authentication and authorization validated by an independent logon sub-system. Connection endpoints can be opened for previously authenticated and authorized clients either on the service side during a predefined short time interval or on the client side. If opened on the client side, the invisible service is triggered to initiate the connection build-up to the open connection endpoint on the client side. Services opening temporary connection endpoints are for port scan during normal operation invisible. Services connecting to connection endpoints opened on the client side, at no time provide any open connection endpoints and are therefore for port scan absolutely invisible. In networks on the base of TCP/IP the id of an opened connection endpoint (port) may be selected pseudo or absolutely randomly. In addition, it is possible to dynamically select the service unit out of a set of multiple service units in dependence of the actual system load distribution "load balancing", connection quality, geographical, topological or other criteria. After the establishment of a connection between an invisible service and a client, both partners may authenticate each other using random access data (tickets).

A multiprocessor system (40) includes a MPU subsystem (12), with master MPU (16) and shared memory (24), and a DSP/Coprocessor subsystem (14), with one or more slave DSP/Coprocessors (26). The system memory (20) is accessed by each DSP/Coprocessor subsystem (14) through a cache (28) and external memory interface (30). A verification interface (42) is used in verification mode to isolate the DSP/Coprocessor subsystem (14) from the MPU subsystem (12) and to translate system memory requests from the external memory interfaces (30) (through an arbiter (52), where multiple external memory interfaces are used) to a protocol which can be used to access the data from the shared memory (24).

The invention is applicable to the technical field of verification code generation, and provides a method and system for generating a picture verification code. The method comprises the following steps: randomly generating verification code characters; randomly clearing part of the strokes of the verification code characters; processing the verification code characters whose partial strokes are removed into picture format verification code pictures. The method also includes the following steps: randomly generating verification code characters; dividing an area as the background area of ​​the verification code characters; filling the background region and the verification code characters in different ways; The background area and the verification code characters are processed into a verification code picture in picture format. The invention enables the verification code generated by the method for generating the picture verification code provided by the invention to reduce the difficulty of human eye recognition while increasing the difficulty of machine recognition.

A technique for optical inspection verification implements a number of steps. Initially, a simulated solder paste material, including a solder powder and an organic resin, is provided. Next, the simulated solder paste material is printed in a desired pattern on a base material to provide a reference test board. Then, the test board is cured to stabilize the simulated solder paste material. Next, the test board is utilized to train the optical inspection system to reject defective product.

According to one embodiment, the present invention generates a test vector for verification of a video encoder or decoder by encoding video data using a permissible combination of parameters. One embodiment of the present invention provides for verification of a video decoder by performing at least one video decoding operation and comparing a resulting partially or fully decoded test vector to an expected value. Another embodiment of the present invention provides for verification of a video encoder by performing at least one video encoding operation using a selected combination of parameters, and comparing a resulting partially or fully encoded test vector to an expected value.

A method and apparatus for verification of coherence for shared cache components in a system verification environment are provided. With the method and apparatus, stores to the cache are applied to a cache functional simulator in the order that they occur in the trace information from the canonical tracers. However, rather than updating the cache simulator with the actual data stored, the performed time of the store event is applied to the simulator as data. The cache simulator stores the latest performed time for each byte of each cache line in the simulated cache, in an associated data structure. For each load event that is encountered in the trace information for a byte, a comparison is made between a global expected data age of the data in the cache and the performed time associated with the byte. If the data age in the simulated cache for the byte is less than the global expected data age, i.e. a latest previously encountered data age, then a cache coherence violation has occurred.

This invention discloses a logic verification system including an excitation generating module, a tested logic module, a result analysis module, a test interface module, a storage module a bus functional module realized by hardware. A method for logic verification includes: generating exciting data necessary for test, writing the exciting data into the needed verified logic chips via different interfaces when carrying out emulation and hardware system verification verifying if the logic is correct based on the output result of the logic chips.

The invention relates to the technical field of virtual network simulation, in particular to a simulation method and system for simulating a real network environment based on virtualization, electronic equipment and a storage medium. The simulation method comprises the following steps: starting to create a target range; setting basic information; setting topology information; creating resources; setting full-scene startup; storing the scene; and completing shoot range creation. According to the simulation method and system for simulating the real network environment based on virtualization, the electronic equipment and the storage medium, network attack and defense parameters such as a topological structure, the number of nodes and rule parameters can be configured according to needs; multi-mode drilling can be carried out to meet different application requirements, including red and blue confrontation, individual soldier drilling and equipment system verification; in the drilling process, the target range can support rapid deployment of different attack and defense scenes in the aspects of operation resources and management resources, so that safety evaluation is conducted on thetarget range in an omnibearing mode, and weak links are perfected in an emphasized mode.

A gate-level power consumption analysis device comprises a vector capture module, a control module, a storage module and a power consumption analysis module, wherein the vector capture module, the control module and the storage module are arranged on a hardware platform, and the power consumption analysis module is arranged in a principal computer; the control module supplies a clock control signal to the work and the signal capture of the hardware platform, the vector capture module captures a real-time signal state under the clock control, the storage module is used for storing a captured signal, and the power consumption analysis module generates a gate-level waveform conversion file according to the captured signal, establishing a gate-level power consumption model and completing the power consumption analysis. Correspondently, the invention also provides a power consumption analysis method based on an on-chip system verification platform. The power consumption analysis device can evaluate the running state of the entire system before the realization of the rear end of a system on chip (SoC), can estimate the power consumption level of a tested module in real time and finally gives an entire performance index of the system. The success rate of a SoC disposable chip can be greatly improved.

The invention discloses a rate matching method in an LTE (Long Term Evolution) downlink system, wherein specific to a 3GPP (The 3rd Generation Partnership Project) LTE downlink system, a transmission channel model based on Turbo codes is proposed, and circulatory filling and interlaced punching are adopted in the rate matching method in the LTE downlink system. In the invention, the rate matchingmethod comprises the steps of: firstly, performing bit collection by adopting a system-verification information bit stream interlaced combination method, and then adding or removing a corresponding number of bits to obtain corresponding code rate by adopting a circulatory filling or interlaced punching method specific to the collected bit stream, thereby realizing rate matching. Experimental tests show that compared with the traditional LET rate matching method, the rate matching method disclosed by the invention can be used for effectively increasing a false bit error rate (BER) performance.In addition, the rate matching method in the LET downlink system has the advantages that the positioning and deleting of dummy bits are omitted, the computational complexity is lowered, and the realizability of an algorithm on software and hardware is increased.

The invention discloses a finger vein recognizing system which belongs to the technical field of biometric identification. The invention further discloses equipment which comprises a finger vein image collecting device, an image processing device and an image recognizing and storing device. The image collecting device is connected with the image processing device through a USB interface, and the image processing device is connected with the mage recognizing and storing device through the USB interface. The finger vein recognizing system comprises two modes: an authentication mode and a recognition mode, wherein, the authentication mode is used for verifying whether a person to be verified is a designated person or not, that is, a user first selects a corresponding user number when the system verification is performed; after finger vein images of the person to be verified are collected, a comparison is made between the finger vein images and the template which is stored in a database and corresponds to the user number, so that whether the user is valid or not can be determined; the recognition mode is used for verifying which registered person the person to be verified is, that is, a comparison is made between finger vein image characteristics of the user and the template of the user in the database; and then a template number with the greatest similarity is found, so as to determine the identity of the person to be verified.

The embodiment of the invention provides a logic design segmentation method and system, and belongs to the technical field of logic array prototype system verification, and the method specifically comprises the steps: collecting an RTL design file for describing a logic circuit; performing grammatical analysis processing on the RTL design file, extracting an always object and an assign object in the logic model object, respectively packaging, constructing and generating a hypergraph data structure, performing attribute analysis, processing according to the clock domain information to obtain operation frequency information, and performing associated storage on the clock domain information domain and the operation frequency information and corresponding nodes; and performing segmentation processing to obtain corresponding grouped data. By means of the processing scheme, other processing at the back end of the process is not affected, the segmentation duration is shortened, the segmentation efficiency is improved, meanwhile, efficient, reasonable and correct segmentation processing is conducted on the chip design logic content, the performance and efficiency of design segmentation aregreatly improved, then the process of user front-end function verification is accelerated, and the appearance of integrated circuit products is accelerated.

Some embodiments provide a verification system for automated verification of entities. The verification system automatedly verifies entities using a two part verification campaign. One part verifies that the entity is the true owner of the entity account to be verified. This verification step involves (1) the entity receiving a verification code at the entity account and returning the verification code to the verification system, (2) the entity associating an account that it has registered at a service provider to an account that the verification system has registered at the service provider, (3) both. Another part verifies the entity can respond to communications that are sent to methods of contact that have been previously verified as belonging to the entity. The verification system submits a first communication with a code using a verified method of contact. The verification system then monitors for a second communication to be returned with the code.