Real-time simulation validation system and method for communication system integrated circuit design

Abstract

The invention provides a real-time simulation verification system and a real-time simulation verification method for the design of an integrated circuit of a communication system, which are used for the verification of the design of the integrated circuit of the communication system. The system and the method can be used for real-time verification of the front end and the rear end in the design of the integrated circuit of the communication system. The system and the method comprise that: a test module generates excitation data with the frame format required by a tested system by calling a related task, collects response regenerated by the tested system, compares the response value and the reference value in a verification module, and obtains a verification conclusion, and the two modules are communicated with each other in the mode of text. The system and the method can be transplanted into different system verifications as required aiming at communication systems with fixed frame format, and simultaneously the system changes the execution sequence of basic steps of verification, can be operated in real time, and reduces the time required by simulation verification. Moreover, the system not only can be applied to the simulation verification of a simple system provided with a standard serial port but also can be applied to the simulation verification of a large-scale complex communication system of a navigation receiver.

Description

technical field [0001] The invention belongs to the field of integrated circuit design, and relates to the field of digital integrated circuits. Specifically, it relates to a real-time simulation verification system and method for integrated circuit design of communication systems. Background technique [0002] Communication and information processing systems usually process data with a fixed frame structure. In the verification work, the uncertainty of the channel and the source is difficult to use the hardware description language to model; at the same time, because the simulation of a large number of signal processing algorithms by the simulator usually wastes a lot of computing resources, the speed is not optimistic. Therefore, in most cases, actual on-site verification is required to ensure the correctness of the system. Therefore, for the verification of integrated circuit chips in communication systems, most field-programmable gate arrays (Field-Programmable Gate Arra...

AI Technical Summary

Problems solved by technology

[0003] However, there are two problems in the verification using FPGA: on the one hand, Application Specific Integrated Circuit (ASIC for short) technology is developing towards system on chip (SOC for short) and embedded, Designers cannot design all cores and modules, but purchase mature cores from third parties. If these cores are only hard cores, they only include the final GDS2 and behavior-level simulation models, rather than providing FPGA verification If the soft core in the FPGA cannot be verified, artificially replacing the core in the FPGA with a module in the ASIC design, the risk of failure caused by the replacement will be huge; among them, a file of the GDS2 circuit layout format is

Duplication and waste of time and resources

At the same time, in the above method, the test vector must be compiled and simulated together with the test platform, and the test vector cannot be added to the simulation process in real time according to the needs of the designer, which lacks real-time performance.

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