Logic design segmentation method and system

Abstract

The embodiment of the invention provides a logic design segmentation method and system, and belongs to the technical field of logic array prototype system verification, and the method specifically comprises the steps: collecting an RTL design file for describing a logic circuit; performing grammatical analysis processing on the RTL design file, extracting an always object and an assign object in the logic model object, respectively packaging, constructing and generating a hypergraph data structure, performing attribute analysis, processing according to the clock domain information to obtain operation frequency information, and performing associated storage on the clock domain information domain and the operation frequency information and corresponding nodes; and performing segmentation processing to obtain corresponding grouped data. By means of the processing scheme, other processing at the back end of the process is not affected, the segmentation duration is shortened, the segmentation efficiency is improved, meanwhile, efficient, reasonable and correct segmentation processing is conducted on the chip design logic content, the performance and efficiency of design segmentation aregreatly improved, then the process of user front-end function verification is accelerated, and the appearance of integrated circuit products is accelerated.

Description

technical field [0001] The present application relates to the technical field of logic array prototype system verification, in particular to a logic design segmentation method and system. Background technique [0002] With the continuous improvement of chip integration and circuit complexity, the current mainstream digital chips contain a large number of IP cores, CPU cores, firmware codes, microcontroller microcodes, embedded software, etc. One billion or even tens of billions of gates, the increase in the logic scale of the logic array (FPGA) puts forward higher requirements for functional verification, and an efficient and reasonable design segmentation method can greatly improve the performance and efficiency of design segmentation, thereby accelerating user front-end functions The verification process accelerates the launch of integrated circuit products. [0003] In the prior art, most of the segmentation tools based on graph theory algorithms for logic array (FPGA) p...

AI Technical Summary

Problems solved by technology

This leads to a large number of graph nodes that need to be processed, time-consuming process, long segmentation adjustment and iteration cycle, which seriously affects the design and development cycle of the chip

In addition, there is no or lack of timing-related information in the circuit during the processing of the traditional segmentation method, which often leads to unreasonable circuit structure of the segmentation result, degraded operating performance, or incorrect operation of logic functions

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