A logical design segmentation method and system

Abstract

The embodiment of the present application provides a logic design segmentation method and system, belonging to the technical field of logic array prototype system verification, specifically including: collecting RTL design files used to describe logic circuits; performing syntax analysis on RTL design files, extracting logic The always object and the assign object in the model object are encapsulated separately to construct and generate a hypergraph data structure, perform attribute analysis and process the operating frequency information according to the clock domain information, and associate the clock domain information domain and operating frequency information with the corresponding nodes storage; performing segmentation processing to obtain corresponding grouped data. Through the processing scheme of this application, other processing at the back end of the process is not affected, the segmentation time is reduced, and the segmentation efficiency is improved. At the same time, the logical content of the chip design is efficiently, reasonably and correctly segmented, which greatly improves the performance and efficiency of design segmentation, and then Accelerate the process of user front-end function verification and accelerate the launch of integrated circuit products.

Description

technical field [0001] The present application relates to the technical field of logic array prototype system verification, in particular to a logic design segmentation method and system. Background technique [0002] With the continuous improvement of chip integration and circuit complexity, the current mainstream digital chips contain a large number of IP cores, CPU cores, firmware codes, microcontroller microcodes, embedded software, etc. One billion or even tens of billions of gates, the increase in the logic scale of the logic array (FPGA) puts forward higher requirements for functional verification, and an efficient and reasonable design segmentation method can greatly improve the performance and efficiency of design segmentation, thereby accelerating user front-end functions The verification process accelerates the launch of integrated circuit products. [0003] In the prior art, most of the segmentation tools based on graph theory algorithms for logic array (FPGA) p...

AI Technical Summary

Problems solved by technology

This leads to a large number of graph nodes that need to be processed, time-consuming process, long segmentation adjustment and iteration cycle, which seriously affects the design and development cycle of the chip

In addition, there is no or lack of timing-related information in the circuit during the processing of the traditional segmentation method, which often leads to unreasonable circuit structure of the segmentation result, degraded operating performance, or incorrect operation of logic functions

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