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71 results about "Iteration cycle" patented technology
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Iteration is a cycle-once you measure the results of the change and decide whether or not to keep it, you go back to beginning to observe what’s happening, and the cycle repeats.
Filter structure for iterative signal processing
InactiveUS20080317150A1Reduce disadvantagesEasy to useError preventionTime-division multiplexMulti user interferenceIterative method
The present invention relates to improved multiple access communications. In one form, the invention relates to an improved signal processing method and apparatus for an iterative method of determining the reception of a signal in a multi user packet based wireless OFDM (Orthogonal Frequency Division Multiplexing) communication system. In other forms the present invention provides recursive filtering for joint iterative decoding in a variety of systems and functions such as linear multiple access channel decoders, iterative equalisation, iterative joint channel estimation and detection / decoding, iterative space-time processing, iterative multi user interference cancellation and iterative demodulation. In one particular form the present invention provides an iterative decoding circuit for a wireless multiuser communications receiver comprising a first signal processing means for receiving at least one received signal, said first signal processing means comprising at least two linear iterative filters such that the first linear iterative filter provides an estimate of a selected received signal to an estimated signal output and a second linear iterative filter provides estimates of at least one other received signal, delayed by one iteration cycle, to an input of said first linear iterative filter, a second signal processing means for receiving the estimated signal output of the first linear iterative filter and providing a further received signal estimate to the input of the first signal processing means in a succeeding iteration cycle of the decoding circuit.
Owner:COHDA WIRELESS
Method for realizing task data decoupling in spark operation scheduling system
ActiveCN104360903ASimplified dependency configurationCollaborative development capability enhancementMultiprogramming arrangementsOperation schedulingModularity
The invention relates to a method for realizing task data decoupling in a spark operation scheduling system, wherein the method comprises the following steps that in one iteration cycle, a system reads the iteration RDD (resilient distributed datasets) information of an iteration state object through a task context object example, and in addition, the iteration RDD information is stored into a task context object; the system finds the corresponding RDD information from the task context object through a Spark task object example, and stores the corresponding RDD information into a task result object; the system analyzes the RDD information in the task result object through the task state object example, and respectively stores the corresponding RDD information into the corresponding state object. When the method for realizing task data decoupling in the spark operation scheduling system is adopted, the RDD can be transmitted among all tasks, or the RDD transmission can be carried out between a former period and a later period of the task, so that each task can be complied in a modularized mode, and a wider application range can be realized.
Owner:北京赛特斯信息科技股份有限公司
Frequency-domain multi-user access interference cancellation and nonlinear equalization in CDMA receivers
ActiveUS20050249269A1Reduce accessImprove performanceModulated-carrier systemsSoil-shifting machines/dredgersCommunications systemInterference cancelation
A method for canceling interference at a wireless code division multiple access (CDMA) communication receiver is provided. The wireless CDMA communication system receiver receives a stream of chips generated by spreading data symbols formed by grouping bits of information at a wireless CDMA communication transmitter which are broadcast at a certain chip-rate. The received chips are de-spread and symbols pertaining to respective users are reconstructed. The method includes formatting the stream of chips into blocks of chips, and performing an iterative block decision feedback equalization in a frequency domain at the chip-rate of the broadcast stream of chips to remove inter-symbol interference by defining a transfer function. The transfer function is defined based upon iteration cycles as a function of data detected in a preceding iteration cycle. The chips generated are interleaved by spreading each data symbol being transmitted before broadcasting the stream of interleaved chips in distinct blocks of chips.
Owner:STMICROELECTRONICS SRL
LDPC post-processor architecture and method for low error floor conditions
ActiveUS20170149446A1Reduce error rateSolve the real problemError correction/detection using multiple parity bitsCode conversionComputer architecturePost processor
Post-processing circuitry for LDPC decoding includes check node processor for processing shifted LLR values, a hard decision decoder circuitry for receiving processed LLR information and performing parity checks on the processed LLR information. Post-processing control circuitry controls updating of LLR information in the check node processor. The check node processor, hard decision decoder, and control circuitry cooperate to identify check nodes with unsatisfied parity checks after an iteration cycle, identify neighborhood variable nodes that are connected with unsatisfied check nodes, identify satisfied check nodes which are connected to neighborhood variable nodes, and modify messages from neighborhood variable nodes to satisfied check nodes if needed to introduce perturbations to resolve decoding errors. Neighborhood identification circuitry determines which variable nodes are connected with unsatisfied check nodes, that have failed a parity check, and produces a signal indicating which variable nodes are connected to unsatisfied check nodes.
Owner:TEXAS INSTR INC
Game theory-based power control method of multi-antenna CDMA system
InactiveCN101321004ASolving Distributed Power Control ProblemsReduce bit error rateTransmission control/equalisingTransmitter/receiver shaping networksChannel state informationTransmitted power
A solving method of the power control based on the game theory in the multi-antenna code division multiple access system is disclosed, wherein a game function based on the receiving end average bit error rate is designed, to realize the minimum of the user union transmitting power and the bit error rate, meanwhile, a punishment mechanism is inducted based on the link quality and the transmitting power to solve the 'far and near effect' in the CDMA system, and the punishment factor is adjusted real-time according to the different operation requirement. Each user performs the precoding treatment on the signal, divides the signal at the receiving end into N branches for processing. Each branch is multiplied by a receiving vector corresponding to the precoding vector, to cause the information update only depending on the feedback of part channel state information. The transmitting power and the signal to interference and noise ratio of each iteration by the user is computed, and the feasibility judgement is completed, till the obtained transmitting power through two times of iteration by the user satisfies that the 2-norm is smaller than the given small number after being adjusted continuously, the algorithm jumps out of the iteration cycle.
Owner:PLA UNIV OF SCI & TECH
Primary estimation on obc data and deep tow streamer data
ActiveUS20130242696A1Improve computing efficiencySmall sizeSeismic signal processingSeismology for water-covered areasImpulse responsePressure data
Method for correcting OBC or deep-towed seismic streamer data for surface-related multiple reflections. The measured pressure data, preferably after conditioning (71), are simulated using a forward model that includes a water propagation operator between source locations and receiver locations and a term representing primary impulse responses (72). Other terms include direct arrivals and source wavelets. Iterative optimization of an objective function is used to minimize the difference between measured and simulated data, updating the primary impulse response term and optionally the source wavelets term each iteration cycle (73). The converged primary impulses (74) are used to construct simulated multiples and direct arrivals (75), which can be subtracted from the measured data. Optionally the measured data might be blended during the forward simulation (72), to save computational costs in the forward simulation (72) and in the inversion (73).
Owner:EXXONMOBIL UPSTREAM RES CO
Temperature solving algorithm of insulated gate bipolar transistor (IGBT) module
ActiveCN105825019AGuaranteed calculation accuracyWork lessSpecial data processing applicationsInformaticsCapacitanceComputer module
The invention discloses a temperature solving algorithm of an insulated gate bipolar transistor (IGBT) module. The temperature solving algorithm of the IGBT module comprises the following steps of firstly, extracting the fitting parameters of a power loss model, thermal resistance and thermal capacitance parameters of a seven-order equivalent Cauer heat transfer network model and an ambient temperature of the IGBT module, afterwards, judging the states in which an IGBT and a freewheeling diode (FWD) are in a current iteration cycle according to gate triggering signals, which are detected from an electrical network model, of the current iteration cycle and a previous iteration cycle, subsequently, calculating the power losses of the IGBT and the FWD in the corresponding states of the current iteration cycle, and finally, calculating the temperature of the IGBT module by the heat transfer network model of the IGBT module through synthesizing the power loss and the ambient temperature of the current iteration cycle. By using the temperature solving algorithm of the IGBT module, which is provided by the invention, not only can the real-time calculation of the temperature of the IGBT module be realized, but also foundations can be laid for the aspects of the heat radiation design, the performance optimization, the reliability evaluation and the like of the IGBT module.
Owner:BEIJING SENFU SCI & TECH CO LTD
Mobile game server-side frame system based on microservices architecture
ActiveCN107995169AImprove reusabilityImprove collaborative development efficiencyTransmissionData accessMicroservices
Owner:厦门点触科技股份有限公司
Retention time violation repair method, device and equipment
ActiveCN110377922AWill not affect placementDoes not increase routing resourcesSpecial data processing applicationsRetention timeNetlist
The invention provides a retention time violation repairing method, device and equipment. The method includes: before layout time sequence optimization, calculating a retention time violation value ofa scanning time sequence path in an integrated circuit in advance according to a netlist of the integrated circuit; determining a buffer combination required for repairing the retention time violation of the scanning time sequence path according to the retention time violation value of the scanning time sequence path; generating a layout constraint according to the layout space corresponding to the buffer combination, and performing layout time sequence optimization according to the layout constraint to reserve the layout space corresponding to the buffer combination for the scanning time sequence path; during a hold time repair phase, inserting the buffer corresponding to the buffer combination into the layout space corresponding to the reserved buffer combination, and the newly insertedbuffer is located in the reserved layout space, so that the placement of the original unit is not influenced, too many wiring resources are not increased, the influence on the design is minimum, andthe iterative period of the design can be remarkably shortened.
Owner:LOONGSON TECH CORP
Method for combined bone hardening and scattered radiation correction in X-ray computed tomography
InactiveUS20080159469A1Accurate methodGood compensationMaterial analysis using wave/particle radiationRadiation/particle handlingSoft x rayArithmetic logic unit
The invention relates to a method for combined bone hardening and scattered radiation correction in X-ray computed tomography of a heterogeneous object with a CT system comprising an X-ray source moved around an object, a flat detector with a large number of distributed detector elements which detect measuring beams from a focal point of the X-ray tube, and a control and arithmetic-logic unit—by iterative reconstruction and segmented vectorial reprojection calculation, wherein a scattered radiation correction and a radiation hardening correction are carried out in each iteration cycle for at least two different material components of the object being examined. The invention also relates to an X-ray CT system for carrying out this method.
Owner:SIEMENS HEALTHCARE GMBH
Highly automatic software testing method based on UML diagram
InactiveCN105022691ASimple iterative cycleShort iteration cycleSoftware testing/debuggingUltimate tensile strengthComputer science
The present invention provides a highly automatic software testing method based on a UML diagram, which comprises the test case automatic generating step and the test case automatic executing step. According to the present invention, by analysis on the UML diagram, combination of a combined coverage algorithm and a keyword calling rule, a test case with higher error-detecting capacity and high coverage completeness is automatically generated; and the testing process is highly automatic, the testing speed is greatly improved, testing omission is reduced, error detection is high, the coverage rate is large,a response speed is high, the case is simple to maintain, the highly automatic software testing method is particularly suitable for the agile development mode with a short software iteration cycle and high testing working intensity, and working intensity of software function testing personnel can be greatly reduced.
Owner:STATE GRID CORP OF CHINA +3
Method for comparing hierarchical net list of integrated circuit
The invention discloses a method for comparing a hierarchical net list of an integrated circuit, which belongs to the field of semiconductor integrated circuit design automation, and is mainly used for layout versus schematic consistency check during a rear-end layout design. Hierarchical units are compared by transmitting matching information of a port and a pin, and the iteration cycle of the rear-end layout design is shortened. The method is implemented by the following steps of: performing hierarchical preprocessing on the hierarchical net list, comparing the hierarchical units in turn according to a reverse topological sequence, and adding hierarchical units which cannot be completely matched in the comparison process to the tail part of a suspended queue; and processing the hierarchical units in the suspended queue by using a topological sequence induction method and a reverse topological sequence broadcasting method circularly, processing by a hierarchical random matching method when the induction method is ineffective to all suspended units, and repeating until the suspended queue is empty.
Owner:北京华大九天科技股份有限公司
Method and system for evaluating EDA tool
InactiveCN106502642ASpeed up the iteration cycleMeet needsVersion controlSpecific program execution arrangementsRegression testingDEVS
The invention relates to a method and a system for evaluating an EDA tool. The method provided by the embodiment of the invention comprises the following steps: compiling in a timing manner according to the source code of an updated version submitted by a developer by a server, and generating an executable file; starting configurable regression testing; distributing corresponding computing resources to a plurality of tasks according to a load condition; controlling automatic parallel running of the tasks through scripts, and acquiring running results; collecting the running results and generating a testing report according to the running result of each task; determining whether the function of version development is correct according to the received testing report by the developer, if the function is correct, storing the testing report in a report database; comparing the current testing report with history testing reports stored in the testing report database, and acquiring a comparison result; and judging whether the quality of the version meets the requirement or not according to the received comparison result by the developer, and if the quality of the version meets the requirement, releasing a new version. According to the method, the iteration cycle of the EDA tool can be quickened, and quantitative guidance is provided for the development of the EDA tool.
Owner:HERCULES MICROELECTRONICS CO LTD
Label propagation community finding algorithm based on node importance degrees
InactiveCN107194818AQuality improvementShorten the iteration cycleData processing applicationsNODALLabel propagation
The invention relates to a label propagation community discovery algorithm based on node importance, and its main technical features are: initializing the unique label of each node; calculating the importance of each node, and sorting the nodes according to the node importance from high to low, Generate an ordered sequence; set the number of iterations t=1; for any node in the ordered sequence, update the label of the node to the label with the greatest influence in the label set of adjacent nodes according to the label selection method and label update rule; if the number of iterations t==max Iter or the label of each node is the most influential label, then the nodes with the same label are classified into the same community, and the process ends; otherwise, the number of iterations t is increased by 1, and the update is continued. The present invention has reasonable design, can significantly improve the quality of community discovery under the condition of similar complexity, shorten the iteration cycle, has high accuracy and stability, and can be widely used in community discovery, social network and other fields.
Owner:TIANJIN UNIVERSITY OF SCIENCE AND TECHNOLOGY
Generating method and device for training corpus, equipment and storage medium
ActiveCN109949797AShorten the iteration cycleSave resourcesSpeech recognitionNegative feedbackSpeech sound
The invention discloses a generating method and device for a training corpus, equipment and a storage medium. The method comprises the following steps: exploiting a plurality of corpus data to be marked in a user behavior log associated with a target application, wherein the corpus data comprise a first behavior log including a user voice and a corresponding voice recognition result, and a secondbehavior log associated with first behavior log time and belonging to a same user; determining the user voice and the corresponding voice recognition result in various corpus data to be a positive feedback corpus or negative feedback corpus according to an incidence relation of the first behavior log and the second behavior log in the corpus data to be marked. The embodiment of the invention can automatically and purposefully exploit the positive feedback corpus and the negative feedback corpus of speech recognition to be provided to subsequent training of a speech recognition model based on user behaviors to effectively improve the effect of the speech recognition, thereby being capable of greatly shortening the iteration cycle of the speech recognition model and then saving a lot of resources.
Owner:BEIJING BAIDU NETCOM SCI & TECH CO LTD
LDPC Post-Processor Architecture and Method for Low Error Floor Conditions
ActiveUS20170353194A1Reduce error rateFix bugsError correction/detection using multiple parity bitsCode conversionComputer architecturePost processor
Post-processing circuitry for LDPC decoding includes check node processor for processing shifted LLR values, a hard decision decoder circuitry for receiving processed LLR information and performing parity checks on the processed LLR information. Post-processing control circuitry controls updating of LLR information in the check node processor. The check node processor, hard decision decoder, and control circuitry cooperate to identify check nodes with unsatisfied parity checks after an iteration cycle, identify neighborhood variable nodes that are connected with unsatisfied check nodes, identify satisfied check nodes which are connected to neighborhood variable nodes, and modify messages from neighborhood variable nodes to satisfied check nodes if needed to introduce perturbations to resolve decoding errors. Neighborhood identification circuitry determines which variable nodes are connected with unsatisfied check nodes, that have failed a parity check, and produces a signal indicating which variable nodes are connected to unsatisfied check nodes.
Owner:TEXAS INSTR INC
Simulation system and simulation method of AFDX (Avionics Full Duplex Switched Ethernet) network
ActiveCN106161117AConvenient statisticsSimple designData switching networksSystems designSystem verification
Owner:BEIJING RUNKE GENERAL TECH
Virtual machine on-line migration optimizing method capable of sensing compound application characteristics and network bandwidth
ActiveCN106775949AImprove transmission efficiencyReduce competitionSoftware simulation/interpretation/emulationDirty pageBandwidth reservation
The invention discloses a virtual machine on-line migration optimizing method capable of sensing compound application characteristics and the network bandwidth and belongs to the technical field of software. The method comprises the steps that firstly, an application characteristic environment and network bandwidth environment of a virtual machine are sensed, and the number of memory dirty pages is collected; secondly, the number of memory dirty pages is forecasted by means of a grey prediction model; thirdly, the dirty page rate of an iteration cycle of the virtual machine is calculated; fourthly, the use conditions of the network bandwidth are collected; fifthly, according to the network bandwidth required for applications in the virtual machine, whether the virtual machine is a network-intensive virtual machine or not is judged, and then network bandwidth reservation is conducted. In the face of virtual machine migration of network-intensive applications or memory-intensive applications, extra overhead in the migration process can be reduced, the transmission efficiency in the migration process is improved, and the migration time is effectively reduced.
Owner:GUANGXI UNIV
Efficient message passing scheme of iterative error correcting decoders
A decoder and method for implementing an iterative error correcting decoder are provided for decoding a codeword consisting of a N-bit messages. In one implementation, the decoder includes a first set of nodes, and a second set of nodes, each having N bits of resolution. Each node of the second set is coupled to at least one node of the first set, each node of the second set being coupled to a node of the first set by a corresponding set of M wires. Each of the first set of nodes is operable to transfer the bits of a given N-bit message of the codeword over the corresponding set of M wires to a coupled node of the second set during a single iteration cycle, each of the M wires carrying i bits, where N is an integer greater than M, and N=M*i.
Owner:MARVELL ASIA PTE LTD
Method and apparatus for detecting a packet error in a wireless communications system with minimum overhead using tail bits in turbo code
InactiveUS20060059402A1Code conversionAmplitude-modulated carrier systemsError checkingCommunications system
The need for separate CRC bits is eliminated by taking advantage of what has been determined to be an embedded error detection capability of the tail bits generated by the constituent encoders of a turbo coder to perform error detection following turbo decoding. Specifically, it has been recognized that the tail bits are similar to CRC bits that would be generated by a CRC encoder that uses as its generating polynomial the feedback polynomial used by the turbo encoder. At the turbo decoder, after a final turbo decoding iteration cycle, a check is performed on the decoded systematic information bits by calculating the tail bits from the decoded information bits using that generating polynomial and bit-by-bit comparing the calculated tail bits with the systematic tail bits decoded by the turbo decoder. If a mismatch occurs at one or more bit positions, an error is indicated and the packet is marked as having failed. Advantageously, by using the tail bits for error checking, no additional bits need to be allocated and transmitted for packet error detection purposes.
Owner:LUCENT TECH INC +1
Method for iterative image reconstruction for bi-modal CT data
InactiveCN103366388AImprove signal-to-noise ratioReconstruction from projectionImage analysisComputed tomographySignal-to-noise ratio (imaging)
The present invention provides a method for iterative image reconstruction for bi-modal CT data. The present invention relates to a method for the reconstruction of image data (PIC) of an examination object from measurement data, wherein the measurement data is acquired in the case of relative rotational movement between a radiation source (C2, C4) of a computed tomography system (C1) and the examination object. First image data (PIC A) with first image characteristic and second image data (PIC B) with second image characteristic, and SNR with the second image characteristic improved relative to the first image characteristic are calculated from the measurement data. The improved image data (PIC) is calculated by using the first image data (PIC A) and the second image data (PIC B) and using an iterative algorithm. In the iterative algorithm, a low pass is applied to a difference between the first image data (PIC A) and image data of an iteration cycle, and a high pass is applied to a difference between the second image data (PIC B) and the image data of the iteration cycle.
Owner:SIEMENS AG
Optimizing the trajectory of an aircraft
InactiveUS20180239364A1Increase fuel consumptionReduction in operational flight costEnergy saving arrangementsNavigational calculation instrumentsFlight vehicleNoise level
A method for optimizing the trajectory of an aircraft comprises the steps of determining one or more reference criteria CiRef on the basis of a non-optimized initial trajectory; determining one or more initial constraints K′j on the basis of the initial trajectory; determining a criterion Ci according to an analytical function of the criteria CiRef; and, per iteration cycle, determining an optimized trajectory; determining intermediate constraints K′j on the basis of the optimized trajectory; minimizing the criterion Ci determined under the initial constraints K′j and the intermediate constraints K′j; determining q takeoff parameters Pi. Developments describe an incremental iteration of the method, an interruption by the pilot, the use of criteria comprising the fuel consumption, the acoustic noise level, the emission of chemical compounds, the level of wear of the engine, the use of a gradient descent and of diverse optimizations. System and software aspects are described.
Owner:THALES SA
Domain adaptation method based on deep network and confrontation technology
InactiveCN108921281AStrongStrong characteristicNeural architecturesNeural learning methodsData setAdversarial network
The invention discloses a domain adaptation method based on a deep network and a confrontation technology, and relates to deep learning, migration learning, domain adaptation, convolutional neural network, anti-network technologies. On the basis of fine-tuning Alexnet, we added two confrontation subnets to correct the differences between samples in different fields and to learn shareable featuresat the high-level layer. This method can effectively reduce the cost of manual marking in a big data environment, and has certain practical significance. The algorithm proposes innovation based on theupper bound of a new target risk error. The algorithm mainly includes an initialization phase and a network training phase. In the initialization phase, a new neuron layer is constructed based on thenew error upper bound, and the corresponding loss and regularization terms are added, and the network and a data set are initialized. In the training phase, an original hyperparameter is replaced bya probability threshold, and a plurality of iteration cycles are run according to the probability iterative SGD algorithm until a condition is met, and the training ends. The final trained network caneffectively replace the manual marking process to obtain more and more accurate marked samples.
Owner:CHINA UNIV OF MINING & TECH
Method for estimating the number of nuclei of a preselected isotope in a molecular species from and NMR spectrum
ActiveUS7009394B2Measurements using NMR spectroscopyAnalysis using nuclear magnetic resonanceTrial numberIsotope
Owner:F HOFFMANN LA ROCHE & CO AG
Temperature control method for continuous casting billet induction heating process, based on iterative learning control
ActiveCN104407642ASuppress uncertaintySuppress mismatchTemperature control using electric meansIterative learning algorithmTemperature control
The invention discloses a temperature control method for a continuous casting billet induction heating process, based on iterative learning control. The method comprises the steps that historical process data is preprocessed, and an input and output trajectory of the latest operation process is taken as a reference trajectory; a historical data trajectory subtracts the reference trajectory, a large amount of nonlinearity is removed, and a perturbation model variable is obtained; a revised dataset is processed through the partial least-squares regression method, and a linearized perturbation model around the reference trajectory is obtained; the control input voltage of the operation is calculated according to a learning law of iterative learning control; the control input voltage obtained through calculation is applied to the induction heating process, so that the billet outlet temperature of the process is obtained; newly obtained process data is added into a historical database, an old data is removed, and the next iteration cycle begins. The method sufficiently utilizes the characteristic of the repeatability of the induction heating process, introduces the iterative learning algorithm, and enables an output temperature trajectory to furthest track an expected temperature trajectory.
Owner:杭州四达电炉成套设备有限公司
Comb-type pilot OFDM system receiver
ActiveCN105471802AAccurate estimateChannel estimationMulti-frequency code systemsTime domainCommunications system
The invention discloses a comb-type pilot OFDM (Orthogonal Frequency Division Multiplexing) system receiver, comprising a setting module used for presetting an iteration cycle index threshold and a cycle index counting initial value; a synchronous module which employs a short preamble to realize coarse synchronization, and a long preamble to realize fine synchronization and frequency offset estimation; an estimation module which employs extracted pilot frequency in each data symbol to estimate the coefficient of a base expansion model, and then calculates the channel estimation value of a time domain corresponding data symbol; an equalization module utilizing a received frequency domain data symbol and a channel estimation result to perform frequency domain equalization; a demodulating, de-interleaving and channel decoding channel used for demodulating, de-interleaving and decoding equalized data; and a determination module used for determining whether an iteration cycle index reaches a preset iteration cycle index threshold; if not reaching the preset iteration cycle index threshold, performing a new cycle of channel estimation by utilizing decoded data, and if reaching the preset iteration cycle index threshold, further determining whether an iteration circulating forward-backward algorithm converges; if an iteration circulating forward-backward algorithm converges, completing a data receiving process, and otherwise, adjusting a synchronous position and performing channel estimation again. The Comb-type pilot OFDM system receiver is suitable for a high speed wireless communication system.
Owner:SHANGHAI UNIV OF ENG SCI
SINS (Ship's Inertial Navigation System)/GPS (Global Position System) high-precision gravity disturbance method based on system states estimation
InactiveCN109186591AHigh measurement accuracyBest gravity perturbation valueNavigation by speed/acceleration measurementsSatellite radio beaconingModel systemInertial navigation system
The invention discloses an SINS (Ship's Inertial Navigation System) / GPS (Global Position System) high-precision gravity disturbance method based on system states estimation. The method comprises the following steps: performing differencing calculation on specific force information measured by the SINS and motion acceleration information measured by the GPS so as to acquire gravity disturbance information with a random error; establishing an autoregressive statistical model of the gravity disturbance field; taking the gravity disturbance as a novel quantity of state to perform combined system filter state augmentation, and establishing an SINS systematic error equation according to a statistical model of the gravity disturbance field so as to obtain an error model system equation for filtering estimation; and selecting the position, speed and acceleration information of the GPS as external quantities to measure, establishing a Kalman filter to perform optimal estimation on the SINS / GPSsystem state (comprising gravity disturbance) so as to acquire an accurate gravity disturbance value, and performing high-precision gravity disturbance compensation in each iteration cycle of an inertial navigation equation. The method disclosed by the invention is capable of efficiently and accurately performing SINS / GPS gravity disturbance compensation.
Owner:GUIZHOU INST OF TECH
LDPC post-processor architecture and method for low error floor conditions
ActiveUS9793923B2Reduce error rateFix bugsError preventionError correction/detection using multiple parity bitsComputer architecturePost processor
Post-processing circuitry for LDPC decoding includes check node processor for processing shifted LLR values, a hard decision decoder circuitry for receiving processed LLR information and performing parity checks on the processed LLR information. Post-processing control circuitry controls updating of LLR information in the check node processor. The check node processor, hard decision decoder, and control circuitry cooperate to identify check nodes with unsatisfied parity checks after an iteration cycle, identify neighborhood variable nodes that are connected with unsatisfied check nodes, identify satisfied check nodes which are connected to neighborhood variable nodes, and modify messages from neighborhood variable nodes to satisfied check nodes if needed to introduce perturbations to resolve decoding errors. Neighborhood identification circuitry determines which variable nodes are connected with unsatisfied check nodes, that have failed a parity check, and produces a signal indicating which variable nodes are connected to unsatisfied check nodes.
Owner:TEXAS INSTR INC
Mobile software development system and method based on Web technology
InactiveCN107562478AShorten the iteration cycleSpecific program execution arrangementsMobile appsOperability
The embodiment of the invention provides a mobile software development system and method based on the Web technology, and relates to the technical field of computers. The system comprises a JS interface unit for allowing a developer to call basic functions provided by an iOS SDK and an Android SDK, a bridging library unit for connecting the JS interface unit with a platform frame unit and providing an expansion interface of an assembly, and the platform frame unit for integrating the SDK at the iOS end and the SDK at the Android end and allowing the developer of the corresponding platform to call create project engineering. By means of the unity and operability of the Web technology, the development cycle and project iteration cycle of a mobile APP are shortened.
Owner:成都市九阵科技有限公司
Big urban power grid homochronous compensator optimization method
ActiveCN107332232ASmall degree of violationExtended reactive power rangeAc network voltage adjustmentReactive power compensationLower limitLow load
The present invention provides a big urban power grid homochronous compensator optimization method, belonging to the electric power system optimization technology field. The method comprises: establishing linear function relations between the upper limit and the lower limit of reactive power of a synchronous generator and the active power of the synchronous generator, and obtaining relevant parameters; determining the number of scenes where the generator is subjected to operation of a homochronous compensator in a low-load phase, and establishing a homochronous compensator optimization configuration model; decomposing the model into a main problem model and a subproblem model; performing solution of the main problem model, and obtaining a homochronous compensator optimization result; and taking the solution of the main problem model into the subproblem model, in each scene, allowing the subproblem model to perform verification of exchange feasibility for the solution of the main problem model, and performing iteration cycle solution until obtaining the optimal solution of the main problem model. The reasonable configuration of the homochronous compensator enhances the voltage control means of an urban power grid, better develops the voltage reactive power regulation potential of the urban power grid itself and guarantee the safe and stable operation of an electric power system.
Owner:TSINGHUA UNIV +1
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