71 results about "Iteration cycle" patented technology

The invention relates to a method for realizing task data decoupling in a spark operation scheduling system, wherein the method comprises the following steps that in one iteration cycle, a system reads the iteration RDD (resilient distributed datasets) information of an iteration state object through a task context object example, and in addition, the iteration RDD information is stored into a task context object; the system finds the corresponding RDD information from the task context object through a Spark task object example, and stores the corresponding RDD information into a task result object; the system analyzes the RDD information in the task result object through the task state object example, and respectively stores the corresponding RDD information into the corresponding state object. When the method for realizing task data decoupling in the spark operation scheduling system is adopted, the RDD can be transmitted among all tasks, or the RDD transmission can be carried out between a former period and a later period of the task, so that each task can be complied in a modularized mode, and a wider application range can be realized.

Method for correcting OBC or deep-towed seismic streamer data for surface-related multiple reflections. The measured pressure data, preferably after conditioning (71), are simulated using a forward model that includes a water propagation operator between source locations and receiver locations and a term representing primary impulse responses (72). Other terms include direct arrivals and source wavelets. Iterative optimization of an objective function is used to minimize the difference between measured and simulated data, updating the primary impulse response term and optionally the source wavelets term each iteration cycle (73). The converged primary impulses (74) are used to construct simulated multiples and direct arrivals (75), which can be subtracted from the measured data. Optionally the measured data might be blended during the forward simulation (72), to save computational costs in the forward simulation (72) and in the inversion (73).

The invention provides a retention time violation repairing method, device and equipment. The method includes: before layout time sequence optimization, calculating a retention time violation value ofa scanning time sequence path in an integrated circuit in advance according to a netlist of the integrated circuit; determining a buffer combination required for repairing the retention time violation of the scanning time sequence path according to the retention time violation value of the scanning time sequence path; generating a layout constraint according to the layout space corresponding to the buffer combination, and performing layout time sequence optimization according to the layout constraint to reserve the layout space corresponding to the buffer combination for the scanning time sequence path; during a hold time repair phase, inserting the buffer corresponding to the buffer combination into the layout space corresponding to the reserved buffer combination, and the newly insertedbuffer is located in the reserved layout space, so that the placement of the original unit is not influenced, too many wiring resources are not increased, the influence on the design is minimum, andthe iterative period of the design can be remarkably shortened.

The present invention provides a highly automatic software testing method based on a UML diagram, which comprises the test case automatic generating step and the test case automatic executing step. According to the present invention, by analysis on the UML diagram, combination of a combined coverage algorithm and a keyword calling rule, a test case with higher error-detecting capacity and high coverage completeness is automatically generated; and the testing process is highly automatic, the testing speed is greatly improved, testing omission is reduced, error detection is high, the coverage rate is large,a response speed is high, the case is simple to maintain, the highly automatic software testing method is particularly suitable for the agile development mode with a short software iteration cycle and high testing working intensity, and working intensity of software function testing personnel can be greatly reduced.

Post-processing circuitry for LDPC decoding includes check node processor for processing shifted LLR values, a hard decision decoder circuitry for receiving processed LLR information and performing parity checks on the processed LLR information. Post-processing control circuitry controls updating of LLR information in the check node processor. The check node processor, hard decision decoder, and control circuitry cooperate to identify check nodes with unsatisfied parity checks after an iteration cycle, identify neighborhood variable nodes that are connected with unsatisfied check nodes, identify satisfied check nodes which are connected to neighborhood variable nodes, and modify messages from neighborhood variable nodes to satisfied check nodes if needed to introduce perturbations to resolve decoding errors. Neighborhood identification circuitry determines which variable nodes are connected with unsatisfied check nodes, that have failed a parity check, and produces a signal indicating which variable nodes are connected to unsatisfied check nodes.

The invention discloses a virtual machine on-line migration optimizing method capable of sensing compound application characteristics and the network bandwidth and belongs to the technical field of software. The method comprises the steps that firstly, an application characteristic environment and network bandwidth environment of a virtual machine are sensed, and the number of memory dirty pages is collected; secondly, the number of memory dirty pages is forecasted by means of a grey prediction model; thirdly, the dirty page rate of an iteration cycle of the virtual machine is calculated; fourthly, the use conditions of the network bandwidth are collected; fifthly, according to the network bandwidth required for applications in the virtual machine, whether the virtual machine is a network-intensive virtual machine or not is judged, and then network bandwidth reservation is conducted. In the face of virtual machine migration of network-intensive applications or memory-intensive applications, extra overhead in the migration process can be reduced, the transmission efficiency in the migration process is improved, and the migration time is effectively reduced.

A decoder and method for implementing an iterative error correcting decoder are provided for decoding a codeword consisting of a N-bit messages. In one implementation, the decoder includes a first set of nodes, and a second set of nodes, each having N bits of resolution. Each node of the second set is coupled to at least one node of the first set, each node of the second set being coupled to a node of the first set by a corresponding set of M wires. Each of the first set of nodes is operable to transfer the bits of a given N-bit message of the codeword over the corresponding set of M wires to a coupled node of the second set during a single iteration cycle, each of the M wires carrying i bits, where N is an integer greater than M, and N=M*i.

The need for separate CRC bits is eliminated by taking advantage of what has been determined to be an embedded error detection capability of the tail bits generated by the constituent encoders of a turbo coder to perform error detection following turbo decoding. Specifically, it has been recognized that the tail bits are similar to CRC bits that would be generated by a CRC encoder that uses as its generating polynomial the feedback polynomial used by the turbo encoder. At the turbo decoder, after a final turbo decoding iteration cycle, a check is performed on the decoded systematic information bits by calculating the tail bits from the decoded information bits using that generating polynomial and bit-by-bit comparing the calculated tail bits with the systematic tail bits decoded by the turbo decoder. If a mismatch occurs at one or more bit positions, an error is indicated and the packet is marked as having failed. Advantageously, by using the tail bits for error checking, no additional bits need to be allocated and transmitted for packet error detection purposes.

A method for estimating the number of nuclei of a preselected isotope in a molecular species starts with an NMR spectrum of a sample containing said molecular species as a predominant substance, said NMR spectrum comprising a plurality of signal peaks corresponding to said nuclei. By applying inclusion and ordering criteria one obtains a set of ordered signal peaks, the integration of which leads to a set of ordered integrals. Nested outer and inner iteration cycles are carried out, wherein for each cycle a trial number of nuclei is assigned to one of said ordered integrals whilst the other ordered integrals are rescaled accordingly and rounded to the next integer value, so as to yield a candidate total number of nuclei. An estimated total number of nuclei is obtained by taking the lowest one from the plurality of candidate total numbers of nuclei that have the highest number of occurrences.

The invention discloses a comb-type pilot OFDM (Orthogonal Frequency Division Multiplexing) system receiver, comprising a setting module used for presetting an iteration cycle index threshold and a cycle index counting initial value; a synchronous module which employs a short preamble to realize coarse synchronization, and a long preamble to realize fine synchronization and frequency offset estimation; an estimation module which employs extracted pilot frequency in each data symbol to estimate the coefficient of a base expansion model, and then calculates the channel estimation value of a time domain corresponding data symbol; an equalization module utilizing a received frequency domain data symbol and a channel estimation result to perform frequency domain equalization; a demodulating, de-interleaving and channel decoding channel used for demodulating, de-interleaving and decoding equalized data; and a determination module used for determining whether an iteration cycle index reaches a preset iteration cycle index threshold; if not reaching the preset iteration cycle index threshold, performing a new cycle of channel estimation by utilizing decoded data, and if reaching the preset iteration cycle index threshold, further determining whether an iteration circulating forward-backward algorithm converges; if an iteration circulating forward-backward algorithm converges, completing a data receiving process, and otherwise, adjusting a synchronous position and performing channel estimation again. The Comb-type pilot OFDM system receiver is suitable for a high speed wireless communication system.

Post-processing circuitry for LDPC decoding includes check node processor for processing shifted LLR values, a hard decision decoder circuitry for receiving processed LLR information and performing parity checks on the processed LLR information. Post-processing control circuitry controls updating of LLR information in the check node processor. The check node processor, hard decision decoder, and control circuitry cooperate to identify check nodes with unsatisfied parity checks after an iteration cycle, identify neighborhood variable nodes that are connected with unsatisfied check nodes, identify satisfied check nodes which are connected to neighborhood variable nodes, and modify messages from neighborhood variable nodes to satisfied check nodes if needed to introduce perturbations to resolve decoding errors. Neighborhood identification circuitry determines which variable nodes are connected with unsatisfied check nodes, that have failed a parity check, and produces a signal indicating which variable nodes are connected to unsatisfied check nodes.

The embodiment of the invention provides a mobile software development system and method based on the Web technology, and relates to the technical field of computers. The system comprises a JS interface unit for allowing a developer to call basic functions provided by an iOS SDK and an Android SDK, a bridging library unit for connecting the JS interface unit with a platform frame unit and providing an expansion interface of an assembly, and the platform frame unit for integrating the SDK at the iOS end and the SDK at the Android end and allowing the developer of the corresponding platform to call create project engineering. By means of the unity and operability of the Web technology, the development cycle and project iteration cycle of a mobile APP are shortened.