Method for comparing hierarchical net list of integrated circuit

Abstract

The invention discloses a method for comparing a hierarchical net list of an integrated circuit, which belongs to the field of semiconductor integrated circuit design automation, and is mainly used for layout versus schematic consistency check during a rear-end layout design. Hierarchical units are compared by transmitting matching information of a port and a pin, and the iteration cycle of the rear-end layout design is shortened. The method is implemented by the following steps of: performing hierarchical preprocessing on the hierarchical net list, comparing the hierarchical units in turn according to a reverse topological sequence, and adding hierarchical units which cannot be completely matched in the comparison process to the tail part of a suspended queue; and processing the hierarchical units in the suspended queue by using a topological sequence induction method and a reverse topological sequence broadcasting method circularly, processing by a hierarchical random matching method when the induction method is ineffective to all suspended units, and repeating until the suspended queue is empty.

Description

technical field [0001] The invention belongs to the field of automatic design of semiconductor integrated circuits, and mainly relates to back-end layout design and verification, especially the consistency check (LVS-Layout Versus Schematic) between layout (Layout) and schematic diagram (Schematic). Background technique [0002] Layout design and verification are an important part of the integrated circuit design process. Efficient and accurate verification can effectively improve the efficiency of integrated circuit design and greatly reduce the risk of design failure. However, as the technology continues to progress toward the nanometer level, the layout scale expands rapidly in the design of ultra-large-scale or even very large-scale integrated circuits. The traditional layout verification methods are far behind the user's needs in terms of computing speed and memory usage. Therefore, the hierarchical layout verification method has been paid attention to. Its advantages a...

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Problems solved by technology

[0004] Hierarchical LVS verification, in an ideal situation, all units can complete the LVS comparison only once according to the smooth comparison, but in practice, the symmetrical circuit causes the exchangeability of the unit PORT (port) and the PIN (pin) does not match when referencing the unit Circular waiting and other problems caused by the time will lead to failure to match, enter an infinite loop or wrong match, and report a large number of repeated errors

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