Method for comparing hierarchical net list of integrated circuit

An integrated circuit, layered technology, applied in electrical digital data processing, special data processing applications, instruments, etc., can solve problems such as repeated errors, incorrect matching, and inability to match

Active Publication Date: 2012-04-04
北京华大九天科技股份有限公司
View PDF4 Cites 12 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Hierarchical LVS verification, in an ideal situation, all units can complete the LVS comparison only once according to the smooth comparison, but in practice, the symmetrical circuit causes the exchangeability of the unit PORT (

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Method for comparing hierarchical net list of integrated circuit
  • Method for comparing hierarchical net list of integrated circuit
  • Method for comparing hierarchical net list of integrated circuit

Examples

Experimental program
Comparison scheme
Effect test

specific Embodiment approach

[0011] The specific implementation includes two steps:

[0012] 1) Hierarchical preprocessing, including sub-steps such as automatic identification of hierarchical units, breaking up units that cannot be one-to-one in the layout and schematic diagrams, dealing with short-circuit problems, device reduction, filtering of useless floating devices, and identification of gate circuits;

[0013] 2) Hierarchical comparison, as attached figure 1 As shown, the comparison process is as follows: ①Traverse the hierarchical units according to the reverse topological order of the hierarchy, and compare each unit in turn. The internal comparison of the unit uses the signature method to compare the internal devices, unit references and nets. If there are devices directly or indirectly connected to the PORT , unit reference or line network can not determine the matching relationship, this unit will be added to the pending queue; ② if the pending queue is not empty, then traverse the hierarchic...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention discloses a method for comparing a hierarchical net list of an integrated circuit, which belongs to the field of semiconductor integrated circuit design automation, and is mainly used for layout versus schematic consistency check during a rear-end layout design. Hierarchical units are compared by transmitting matching information of a port and a pin, and the iteration cycle of the rear-end layout design is shortened. The method is implemented by the following steps of: performing hierarchical preprocessing on the hierarchical net list, comparing the hierarchical units in turn according to a reverse topological sequence, and adding hierarchical units which cannot be completely matched in the comparison process to the tail part of a suspended queue; and processing the hierarchical units in the suspended queue by using a topological sequence induction method and a reverse topological sequence broadcasting method circularly, processing by a hierarchical random matching method when the induction method is ineffective to all suspended units, and repeating until the suspended queue is empty.

Description

technical field [0001] The invention belongs to the field of automatic design of semiconductor integrated circuits, and mainly relates to back-end layout design and verification, especially the consistency check (LVS-Layout Versus Schematic) between layout (Layout) and schematic diagram (Schematic). Background technique [0002] Layout design and verification are an important part of the integrated circuit design process. Efficient and accurate verification can effectively improve the efficiency of integrated circuit design and greatly reduce the risk of design failure. However, as the technology continues to progress toward the nanometer level, the layout scale expands rapidly in the design of ultra-large-scale or even very large-scale integrated circuits. The traditional layout verification methods are far behind the user's needs in terms of computing speed and memory usage. Therefore, the hierarchical layout verification method has been paid attention to. Its advantages a...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): G06F17/50
Inventor 李桢荣李志梁戴文华
Owner 北京华大九天科技股份有限公司
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap